MB8441-55

MB8441-45 FUJITSU | Alldatasheet

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Aprit 1991 (2) eo FUJITSU SSS SaaS DATA SHEET MB8441-45/-55 V———e—oCOCOoOooOoOree era 8K x 8-BIT CMOS DUAL PORT STATIC RANDOM NY ACCESS MEMORY ss® ‘The Fujitsu MB8441 is an 8K words x 8 bits dual-port high-performance Static Random ye ‘Access Memory (SRAM) fabricated in CMOS. The SRAM uses asynchronous circuitry and xy 19 external clocks are required, The MB8441 provide the usar with two separately controlled WW vopers With independent addresses, Chip Solect (CS), Write Enable fe), Output Enable ), and VO functions. This arrangement permits independent access to any memory location for either @ Read or Write operation — 2 usetul feature for shared data processing applications, These devices have an automatic powor-down feature controled by OS. The MB8441 can be usedas either a master operation or slave operation by selecting the BE pin. Celotta cee eoss, a (SY) fg it provided for acess arbitration; In addition, the MB8441 utilizes an (INT) flag which allows communication between systems on either side of the RAM. The MB8441 uses a single S-volt power supply and al pins are TTL-compatible. ‘Some typical applications for these memory devices are multiprocessing systems, distributed networks, extemal register files, and peripheral controllers. % Features ae © Organization: 8,192 words x 8 bits. — © Static operation: No clocks or timing strobes required. © Access Time: 1AA = tACS = 4508 max. (MB8441-45) TAA @IACS = 55ns max. (MBE441-55) © Power Consumption: ‘Both ports active = 660 mW (max) Both ports standby CMOS « 1.1 mW (max) ‘TTL = 27.5 mW (max) © =TTL-compatible inputs and outputs. © Three-state outputs with Or-tie capability, © Electrostatic protection for all inputs and outputs. © Addres arbitration: (BUSY) flag output (Master Operation: BE = *L) FPT-64P-MOS (BUSY) fag output (Stave Operation: BE = *H") © Interrupt function for communication between systems: INT fag. © Data retention voltage: 2,0V min. © Single +5V (410%) supply. de lotgtualewtage dees ee eee that normal precautions be taken to avoid application of any © 64-pin plastic quad fiat package Whage Moher shan masimum rated voRages fo fie nigh ree Copyrigh® 1901 by FUJITSU LIMITED:

Fig.1 - BLOCK DIAGRAM of MB8441 vo 1L o ill O vo1iR . WE TTI... . Column . _ He oo THT ae Lo 4 mill - or HTL © INTL cs

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‘The MB8441 provides two ports with separate contro! signals, address inputs, and inpuvoutput data pins that allow asynchronous read and write operation to any memory location. This device has an on-chip automatic power-down feature controlled by CS that places the respective port in the standby mode when the chip is deselected (CS is HIGH). ‘When a port is enabled, access to the entire memory array is permitted. Each port has an independent Output Enable (OE) control that is active in the read mode and enables the output drivers. ARBITRATION LOGIC. 1. Master busy function ( BE = "L") ‘The arbitration logic resolves an address match or chip~enable match and debermines the access priority, In both cases, an active BUSY flag is set for the port-in-waiting. Since both ports are asynchronous, there is the possibility of accessing the same memory location from both sides. In the read mode, this condition Is nat a problem. However, this is a problem when both ports are in the write mode with different data words or when one port is reading and the other is writing. When both ports access the same memory location, the on-chip arbitration logic determines which port has access and the BUSY flag for the delayed port is set activa LOW and af operations on that fort are inhibited. The delayed port can be accessed when the BUSY flag becomes inactive. Basic modes of abitration are described in subsequent paragraphs, (refer to timing diagram of “contention cycie*.) ‘Access to delayed port is enabled as following, fist set BUSY from “L" to “H" and then retain wrile mode (CS = WE = *L") during taw. BUSY signal dose not affect the read mode of delayed port normally. But in case that write operalion is done from opposite port during BUSY signal output, read data may change. So itis recommended to read output data atter t 80 passes from reset of BUSY signal CPUL . GPUR . ' RDY 1/0 A v A 170 RADY sare AL AR 4 per Fe | VOL (Mae) orf | frase : = i “a — susyi Busyrn-—| —, = al Fas x AL AR pee) age MB8441 Fen (Slava) . et? nd WoL W0R BUSYL ‘BUSY A Fig. 2—16 Bit Dual Port Memory System Configuration

— ee 2. Slave busy function ( BE = "H") When the MB8441 is used with larger bit width than 8 bits, it is necessary to use more than two chips in paralell. In this case, each chip may output BUSY signal to other ports. It wi be a problem if both CPU get BUSY signal. But the slave busy function can solve this prob- lem. By this function, only the master chip operates the master busy function and the other chip obeys the master chip's BUSY signal. ‘This function is operated by setting BE =°L" on one master chip and setting BE = "H" on the slave chips. By way of example, the compo- sition of the 16 bit dual port memory system is showen in fig. 2, In this systom the master MB8441 with BE = °L" decides which port is first, and outputs the result to BUSY pin. This data is sent 10 the CPU and slave MB8441, then the CPU incurs the "wait" condition. . 3. Interrupt function ‘The interrupt (INT) function provides communication between systems on both sides of the dual-port RAM. INT is set to “L" when the processor on the right port writes to address 1FFE (AO =°L* and A1-A12="H"). When the left port acknowledges by reading address 1FFE, INT is then reset to "H". In essence, address 1FFE serves as an &-bit mailbox that transfers information from the right port to the left port. When INTR is set°L*, the processor on the left part writes to address 1 FFF (AO-A12="H"). When the right port acknowledges by reading address 1FFF,INTRis then resetto "H". Hence, address 1FFF serves as a second 8-bit mailbox, transferring information from the left port 40 the right port. All voltages are referenced to GND. Pimavoupeonaven | vw | __-eseverses «| y= utat Vtige on any [emparsreundorsie | tA | tomees | te [sora Tonge | tera | towers | te [Powerdivgaon | ro | | Note ; Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may atfect device reliability { All voltages are referenced to GND.) [ sumyvetwce | veo Tas | co | ss | | surpyvorge fc | fe | | cmnereommm fate P| me

1, BASIC FUNCTION (AOL to A12L=AORtO A12R nes [esi] wee] cee | GSA WER] CER! pe eee CEES ESE ES Eee ee ee Se ee ee pe fe [fe | | x] eettramniy | sats Pepe fe [oP [aieeecame [ae peat fe fw fe] eamsenms | tm Lx |x [x fe fe] x] emote [tte | NOTES: X= Don't Care, L = Low, H = High 2. ARBITRATION FUNCTION (AOL to A12L = AQRto A12R) x ws See ee ee ee 8 a ec a ee ee ee fee ee [fc | [a | te pefef wr fo) [ef er ee eee ee epee Serer Right operation not permitted Pefef « [oe ep x fe [ete seman | SgPogeere tte. Hea - ad Betore Right, VBL = Valid Before Left, LBR = Low Before Right, LBL = Low Before Left, » Incase that LAPS (min.) Is aot satisfied, the on-chip srbitration logic decides which port has access. And the busy flag for the delayed port is set "L” and all operations on that port are inhibited. But it is undefined which port has access or not. ( Rieter to timing diagram )

(Recommended Operating Conditions unless otherwise noted.) ae ay i es ee foresees [ee [=| = [| ma] orm erm ice | ee ee ee [tse [= [=] fm] Peat vn curso | Stancby Supply Current : EGSoGh ae BE2VCC-0.2 Vor BES GND+0.2V ‘One Full S' ; | is [=|] [] eetivecsesvioureom | | trowresiaecorene | iu | ot =| ofa] vmeciowves | uvutteaiage curent | io | of — | 0 | wa] Savin vour-onowvec | | tomer vote | vm | ae | — [Yes vv CCS ee Se Loot yy Pete fo tv [ton sem — p— [Jol vi arcom 1 -0.3 V Min. for pulse width less than 20 ns. #2 The BUSY and INT pins require pull-up resistors because they are open-drain outputs. VO CAPACITANCE (ta-25°c,1=1 Miz) Fan A Oe piece | ee [ -— [= [oe [ew | (V0 =0V)

READ CYCLE ( Recommended operating conditions unless otherwisw noted. ) |_Resdcyetine | tn [as | | ss | Adcess Access Time | tag | ese s s | TSAccssTime | tac | es ss | OE Access time [tac Pe [OviputHold Time ton fe es ee | GStoOurpurtligh-zet tc Ps ss | GE we Ourputtigh-Zet | tonz fe ets ns | Poweruptine | teu | co PP [ PowerDowntime | tro | oe READ CYCLE TIMING DIAGRAMS. (WE =VIH) Read Cycle No. 1 ( Address controlled) (CS = OF =V IL) tac Address WA DOUT Previous Date Valid Data Valid Read Cycle No. 2 (6S controlled) ** tre -—— cS —— . io WAAAY ALLYLLLLLYLLLL 1 ee pout CXOOK Data vaid tee teu > F160 VCC current 50% 50% 1sB Legend : QQ] undefined KXK] Don't care +1 :Transition is measured at the point of + 500 mV from a steady state voltage with CL = 6 pF. *2: Address should be fixed before high-to-low transter of CS.

( Recommended operating conditions unless otherwise noted. ) | Write Cyole Time two Ts Pm cs eT [ Addoss VaidioEndotwite | taw | gg | — | — | [— [— [om | | chipselectoendotwite | tow [ao | = [Tso Pf = Te | | AdcrossSompting | tas | oo | | To P= Ts | Write Pulse Width twee Ps eee | Write Recovery Time twa fo or rs | Data Setup Time tow fe es ee ee | Data Hold Time to ee ee [WE to Ourputtow-z ei | tow To PT — To PT WRITE CYCLE TIMING DIAGRAMS Write Cycle No.1 (WE Controlled) 2-3 +4 twe: Address CF 1tAW a NS tow TMA j<—— tas twp: wr: We AXANN . High-Z OW ‘OH High-Z OWN 3 (baa YF x | om pout SSDS SSS ASDBN|H High-Z LEELA LLILLLLILILILILLLLLL LLL L2/ ANRARERL Legend: \\\\] Undefined +1: Transition is measured at the point of + 500 mV from a steady state voltage with CL = 5 pF. «2: WE must be high during address transition. #3; IGE and CS are in the READ Mode, VO pins are in the output state so that the input signals of the opposite phase to the output must not be applied, «4: If TS goes high prior to, or coincidently with, WE transition to high, the output remains in high impedance state.

i Write Cycle No.2 (CS Controlled) *1°2 «3 two Accross CY - oh 7 LS AMANNNANNNNNNUNNANANATS LLL , tow 10H , OWN “ee |_| an a. tL, wz pout High-Z Legend : L\\\\] Undefined +1: WE must be high during address transition. «2: If OF and GS are in the READ Mode, then UO pins are in the output state so that the input signals of opposite phase to the output must not be applied. +3:: 16S goes high prior to, of coincidently with, WE transition to high, the output remaing in high impedance state.

BUSY TIMING (BE ="L" ; Master Function ) ( Recommended operating conditions unless otherwise noted. ) [BUSY Accoss TimotromAcdress | teaat —— | — [| 9% [— [| — Jos [om | [BUSY AccossTwmotomeS | tpac| —- | — | % [— | —To [om | [SUSY OuoutHih-Z trom Address | repat — | — [ 3% [— | —TJ[ oo [om | [ WiteHoldTimeromBusy | ssw | 25 | — {[— | a [—]—Toos | CONTENTION READ CYCLE TIMING DIAGRAMS ( WE = V 1H )( BE = VIL ; Master Function ) Data Contention Cycle No.1 (Address Controlled) (CS = OF = VIL)"' °? (Aedes Fy tap: (eee iy Address L = Address RL tBAA ‘BDA: BUSY R mee Data output R = WUVVVY VVYVV YY YY YY VV VV 7 (Data outputL) _ Previous Data Valid XXXXXXXXXXXXXXXXXXKKK Data ais HOH: . 1tAA Data Contention Cycle No.2 (CS Controlled) “!°? (esky Addrass L = Address A. sem sna BA Address L = Address R }7777Z ae i lc ae a ee ae Ati CAAA k LALELLL Pe yb z Data output R eermetiton (Bata ouput 1 AOE tow LACS —— Legend : KXNJ undefined KXX] Don'tcare "1: In case of dual access at the same memory location, the port that accesses the RAM first sets the BUSY flag high. * 2: GS must be tow before, or coincide with, transition of address. * 3: Address is valid prior to, or coincidently with, high-to-tow transition of TS,

MB8441~55 en Y CONTENTION WRITE CYCLE TIMING DIAGRAMS ( BE = V IL : Master Function) Contention Write Cycle No.1 (WE Controlled) *1 *2°3-4 Ads hy tAP dseess tBAM: 41 BDA: BUSYA (BUSY, ) t BW tA 1 WR WER us Uwe (WEL) ANAS: 7 Data Input (Data Input L) Wwe K Data valid Data Ouiputh “SSQOSSSOSSS SSS SSS be tow -V7Z777 (Data Output) "YS TLLLLLLL LALLA ALLL ALLL INAAANS #1920304 05 Contention Write Cycle No.2 (CS Controlled) cSt (Sn) Address L » Address A 3a ef | acerans Ln accross ETT 77/17 (CSL) BAG tepe BusYA (BUSYL) ew tow: we 1 WP ca ANNANARRRRLRAANY: ALLLLLL LL tow to Datainput A (beavis (Gata input L) ee “Ta Data output R SS VUE L eee (cata output L) HEA, NAURAER Legend : Undefined +1: WE must be higti during address transition. *2: WOE end GS aren the READ Mode, then VO pins are in the output state, and the input signals of opposite phase to the outputs must 3 : in case of dual access at the same memory location, the port that accesses the RAM first sets the BUSY flag high, +4: 63 must be low before, or coincide with, transition of CS, +8 : IF CS goes high prior to, or coincidently with, WE transition to high, the output remains in high impedance.

——— BUSY TIMING ( BE = "H” ; Slave Function ) ( Recommended operating conditions untess otherwise noted. ) ee eee ee ee | warouroenonsoy | iw |» |—-[-[«[-[-[ = | CONTENTION READ CYCLE TIMING DIAGRAMS (WE = V IH , BE = VIH : Slave Function ) Contention Read Cycle No.1 (Address controlled) (CE = OE = VIL)? Address A (Address L) BUSYR (BUSY) t tAA tOH (bam outer Previous Data Valid Data Vaid Contention Read Cycle No.2 (CS controlted) *2 Br ITT (es) BUSYR (BUSYL) BO tCHZ VYYYYYYYYWY " aia Out XXX XXX KKK DateVaid (Data Output L) Legend : SQN] uncefined RXR) don't care +1 : It takes 30 ns'to output BUSY signal trom the master side, and €0, the tAS (address sot up time) of the slave side must be 20 ns or more. +2: CS must be low betore, or coincide with, transition of address,

CONTENTION WRITE CYCLE TIMING DIAGRAMS ( BE = V IH : Slave Function) Contention Write Cycle No.1 (WE controlled) “! ‘2 *3°4 Address R ee | <—— (Address L) tas 1wR BUSYR (BUSYL ) t uy 1DW=-Ple— ¢0H (Data Input Lp Contention Write Cycle No.2 (GS controlled) "' *2 °9"4 ogA {Csy) BUSYR (BUSYL) 4 R (WEL) ALLLLLLLLL tow toH tt Koma > {Date Input L) Legend : Undefined +1: WWE must be high during address tranition. 2: VO pins ave in the output atate, £0 the input signals of opposite phase must not be applied. +3: GS must be kaw belore, of coincide with, transition of address. +4: During BUSY input is low, write operation can not be excuted even H WE is low.

{INTERRUPT TIMING ( Recommended operating conditions unless otherwise noted. ) Cee ee frmreme | =f [ oe |-[- [eo | [amtrwatoe | tm | | [| -] os] | INTERRUPT CYCLE TIMING DIAGRAMS frat a (Address L) tas twr WER WEL) degest, 7) (wR my TTT TLE = ANANNANANARAAAN ANNUANANARRURRLULE RRR U RUN INTL tINS: ‘INR, (NTA) Legend : Undefined

Fig.3 — AC Test Conditions a5V +5V Input Pulse Levels :0W30V 1250.0 68 a ¢ Input Pulse Rise and Fail Times :tR ath Sns Timing Reference Levels HSV v0 Bue, Output Loads im He ma int sop al (Nowe) Note : Includes jig and stray capacitance

DATA RETENTION CHARACTERISTICS ( Recommended operating conditions unless otherwise noted.) [ona Reentonsunny votage | YR | 29 | ss [| v [| BE 2 VCC -0.2 V or BES GND +0.2V | DataRownionsenp Tine | tons | o | — | = [ | Loperton recon Ting | ta [| te [ — fo o~ Po DATA RETENTION TIMING Data retention (CS contolled) vec. Data retention mode asv RLU OR Fay BS SS voR-0.2v 2.2V 22 POWER ON/RESET CHARACTERISTICS {Recommended operating conditions unless otherwise noted.) [ natatoecswnrwne| we | ows [= | = | a POWER ON/RESET TIMING ; vec a5V \\ / o2V

1 OFF

tA. Note : Rise power slowly

Note; — 1: This is required to keep normal operation for the power on/reset citcudl which intialize INT output to "H" aulomatically when Vecie spplied. In order to operate power-on-resel circuit normally, inpul conditions to set INT (refer to below) must not be eppiied during tVR period. And when input conditions are undefined during tva period, INT may be set. So itis necessary to Tes! with a dummy read (reler to below). << INTL set conditions > < INTL reset conditions > ight side address : #IFFE att side address: #1FFE er 1 LS level => L TL evel RA 2 "LU level iL < H* level iL 17k" bevel <INTR set concitons > < INTA reset conditions > side address: #1FFF ight side ackiress : HIFFF eh Level 2 SU level be 3 °L" tevel A : *H' level OER "Level

64-LEAD PLASTIC FLAT PACKAGE (Case No. ; FPT-64P-M06) 132 (3.35) MAX (MOUNTING HEIGHT) & -767 (20.00) 8 {STAND OFF HEIGHT) DOOCODODDORONOEONOE 5 @ FAL COLE BLS Chit 2 $2 Fi = — a = = i= 642.016 = O oO = ki8.70+0.40) ia S| inpex == a =| S a = == a is ==\\ | i G TT oe 3 ‘< tea No. OP PUD DOO DUCT ODT HOO 08.002 039411. “G04 @ of}. 008.002 ea oo _|| aise Oe (00810201 @ | (0.180.085) Trem een nnn rng nner [ Dewsits of “A” part o10 u Dewils of “8” part | - =e i ' ee . 1 SIN TTT UUL UU : t 012 (0.30) i H 709 (18.00) REF ' oa i 047 +.008 | 878 +.016 (22.300.40) H TAX tt 11202020); bee nee en need bane ee ne eee eee ed Dimensions it ©1990 FUIITSU LIMITED F64013S-2¢ inches titimaters) All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of iustrating typical semicon- ductor applications. Complete Information sutficient for ‘construction purposes Is not necessarily ‘The information contained in this document has been carefully checked and is believed to be reli- able. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the his, patent rights or trademarks claimed and owned by Fulltsu. uy cong Fujitsu Teserves the right fo change products or specifications without notice. No ‘of this publication may be copied or reproduced in any form or means, of trans- fered any third party without prior witien consent of FuUltsv. byany