MB8431-12

MB8432 FUJITSU | Alldatasheet

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October 1989 fo) ott FUJITSU ee 2K x 8 Bits CMOS Dual-Port Static Random Access Memory The Fujtsu MB8431 and MB&432 are 2,048 words x 8 bits dual-port static high performance, random access memories fabicated wih CMOS technology MBAS! ‘and MB8432 provide the user with two separately controlled independent ” daressas, Gn Selec! (CS), We Enable (WE), Output Ena (OE), and VO functions. This arrangement permits independent access to any memory location for DIP-52P-Mo1 other a Read or Wie operation — a seful feature for shared data processing (MBe431) applications. These devices have an automatic power-down feature controlled by CS. To avoid data contention on the same address, a BUSY input is provided for address oS arbitration; in addition, MB8431 utilizes an interrupt (INT) flag which allows 2 ‘communication between systems on either side of the RAM. Both devices use a single ° 4 +5.V power supply and al pins are TTL-compatible. A simplified block diagram of the : SRAM is shown in Figure 1. ‘Some typical applications for these memory devices are multiprocessing systems, FPT-64P-M01 distributed networks, external register files, and poriphoral controllers. (MB8431) | 4 | © Organization: 2,048 words x 8 bits ‘© Static operation: no clocks or timing strobe required © Accesstime: — tyx=tace=90ns max. (MB8431/32-90) tan lacs = 120 ns max. (MB8431/32-12) (MB8431/2-12/-12LL) DIP-48P-M02 ‘© Power consumption for the standard version: (MB8432) Soa femmes mW max. 38.5 mW max. (Both ports standby, TTL) Pin Assignment 11 mW max. (Both ports standby, CMOS) * Power consumption for the L and LL-versions: 495 mW max. (Both ports active) 275 mW max. (One port active) 27.5 mW max. (Both ports standby, TTL) 4.4 mW max. (Both ports standby, CMOS) © Single +5 V supply +10% tolerance ‘* TTL compatible inputs and outputs See page 4-81 © Three-state outputs with OR-tie capacity ‘* Electrostatic protection for all inputs and outputs * Data retention voltage: 2 V min. © Address arbitration function: BUSY input ‘© Interrupt function for communication between systems (MB8431 only): INT tlag ‘© Expansion capability using MB8421/22 (Master) and MB8431/32 (Slave) * Standard Plastic Packages: 48pin DIP MB8432-xx(L/LL)P S2-pin DIP MBB431-xx(ULL)P 64-pin QFP MB8431-xx(ULL]PFO tices contra crt ope e re sat Sed na raat pecans anol appcain Sian er tan rr ed vg gh rocdance Compre © 1980 by FUITEU LMITED ad Fup Metco ne

ABSOLUTE MAXIMUM RATINGS (See NOTE) es

1 Voltage on with ros 05

Lremenemmrmre| [a | | Cutput Voltage on any UO pin with 05 es oe [ tomesnonn Oe Pew | ee Note: Permanent device damage may occurit ABSOLUTE MAXIMUM RATINGS | excoudod. Functional operation. should be restncied fo he. conavons: ae <otailed in the operational sections of this data shoot Exposure to absolute maximum rating conditons for extonded periods may affect device reliability _4 | ee [|_veteon ]mowrvonr | wanes | _ — Chip os oe Select Input Output Enable Input __ Interrupt * iNT Flag Output way suey, Busy BUSY. BUSY Flag Input [eam | ane [| ee es *: Apples to MBB431 only

Fig. 1 — MB8431/32/31L/32L BLOCK DIAGRAM ~ffl5s eis letOaa Ee VO Butter 3 Right Data _ | er _ ) INT, (Noto) < T WNTa (Note) ' Note: — MB8431 only. | CAPACITANCE ¢,- 25°c, t= 1mHz) ee a 4-69

RECOMMENDED OPERATING CONDITIONS (Referenced to VSS) [rome Termes [me Te Tm Tm a A DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) se Condition (MB8432-90/12 (M88432-90L/90LL/12L12LL [win [Mex [Min [Max | Se. Se TCC ‘Supply Current Duty=100% (Both ports Active) lour=OmA = SC Se = Standby lowr=OmA ‘Supply Current = emcee [| [= =| CS. & CSa2Vec-0.2V Se CS, oF CSp2Vec-0.2V, 70 logr=OmA a ee ee Seer eee) ee ee ee es ee eee ele | ef Pete dd *1 Undershoot -3.0V min at less than 20ns pulse width. *2 The INT pins require pull-up resistors because they are open-drain outputs. 4-70

I AC TEST CONDITIONS + Input Pulso Lovets: oVte3.0v * input Pulse Rise & Fall Times: AR, F508 + Timing Reference Levels 18v + Output Load +5V +5V 12500 S75. vo Wt 100pF * 7750. SOpF* * Including Jig and stray capacitance 4-71

— SSS AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted) READ CYCLE MB8432-60/90L/90LL | MBB432-12/121/12LL [win [Mex [win Tex | | Reed Creo tine te me ee | Aecross Accwes Tine ee | | Chie Sect Access Tino Te TE me oe | | Qupunabie Access time we oe me | LC SE a [upstate oOuputtow2@ | es | 8 PP | Se A | PoworuptomGhipSewet Tw dT oe fT | CU [Power dow ton cnpseet dT te | Pe] 4 | READ CYCLE TIMING DIAGRAMS (WE=Vm) READ CYCLE No. | (ADDRESS CONTROLLED) (C5-OE=Vi) te ‘ADDRESS tu ton = Dawe PREVIOUS DATA VALID DATA VALID. READ CYCLE No. Il *1 (CS CONTROLLED) tee es tw we KAMAN ALLL LLL 7 thes tear"2 toa'2 > co = =XAAAAAAAS 4 ALLLLL LLL | i I ‘ae? Dow x KXXXKDaTAvauiD > Le = Vee CURRENT 's8 50% lee 50% KX -ooncwe ZZ ines Note: "1 Address should be fixed betore high-to-low transition of €S. *2. This parameter is specified at the point of 4500mV trom steady state voltage with output capacitance SpF. 4-72

4B.432-00/90L/90LL | MB8432-12/12U12LL| [win [vex [in] ox | Lo fe Ts [[Ascross Vath Endotweio | tw tes PT to Ps [chp Soweto gnaatwitn |e |e || of |» | [ write Puewath Tw OT wT Ts | Write RecovenyTime Te Ps [oatavowtime dT tT 2 | Po | dd [write Enable Ouputtow2r¢ [mw fo fo Ts [win Enatiow Ovputigrz-e dT ww | | «| | » | «| WRITE CYCLE TIMING DIAGRAMS (OE=Don't care} WRITE CYCLE No, 1*1*2*3 : (WE CONTROLLED) ADDRESS: tw tow a SQA dd\\ ALLLLLLLL tw L be we We FANS as don ORXXXXXXXXXXXXXXKXKXKY KXXXX Note: *1 WE must be high during addross transition. *2. ITOE, CS are in the READ Mode, 1/0 pins are in the output state so that the input signals of opposite phase to the outputs mustnot “3 1168 gor high prior tor coincident wih WE tansiton high, he ouput mains in tighimpodance tte "4 Transiton is measured at the point of +500mV trom steady state voltage with C.=5pF. 4-73

WRITE CYCLE No. Il *1 *2°3 : (CS CONTROLLED) two sooness _} tw ton be ow s AN: w = \\AAMAYAAYS ALLLLLLL 11 tow tow HIGH-Z HIGH-Z 4 | Daw KXXXXXX) DX :ovtcan ZZ) nests Note: °1 WE must be high during address wansiton “2 fe. ‘CS are in the READ Mode, 1/0 pins are in the output state so that the input ‘signals of opposite phase to the outputs must not *3 ICS goes high prior to or coincidont with WE tansiton to high the ouput remain in igh impedance state *4 This parameter is specified at the point of +500mV from steady state ‘voltage with output capacitance SpF. 4-74

(MB8431-90/90L/90LL | MB8431-$2/12L/12LL | (MB8432-G0/90L/90LL | MB8432-12/12L/12LL | [min [ex [in [ex [Busy Accessing TT Os [ wite SotpTine Toby oP Od od [[wrta Hots Time From Busy | tw TTT ts Ps CONTENTION CYCLE TIMING DIAGRAMS (WE=Vn) CONTENTION READ CYCLE No. |*t *2 : (ADDRESS CONTROLLED) (CS-OE=Va) ADDRESS « (ADDRESS ,) BUSY. (BUSY) be rn “ i 4 | Dou PREVIOUS DATA VALID DATA VALID ound CONTENTION READ CYCLE No. I1*1 *3 : (GS CONTROLLED) cS * fp BUSY, VVYVVYYVYVYrYrVrrrnrvryry Bem KXXXXXXXXXXXXXXXK ——ovTavauio Note: ‘1 Incase of dualaccess at the same memory location, the port that access the RAM first sets the BUSY flag high. *2 CS must be low before or coincident with transition of address. *3. Address is valid prior to cincident with high-to-tow transition of CS. “4 This parameter is specified at the point of 4500mV from staady state voltage with output capacitance SpF. 4-75

CONTENTION CYCLE TIMING DIAGRAMS CONTENTION WRITE CYCLE No, 1*1 *2°3 (WE CONTROLLED) ADDRESS » (ADDRESS) es —— fen BUSY, . — we WE; Wey toe ton one (Ona 4) CONTENTION WRITE CYCLE No. 113 :*1 *2°3 (CS CONTROLLED) Se (eS) BUSY, (BUSY) Wwe tw we we ALLLLLLLL1 tow tow os (Ona) Note: *1 WE must bo high during address transition ‘2 VO pins are in the output state, so tho input signals of opposite phaso must not be applied. “3. During BUSY input is low, write operation can not be excuted even it WE is low. 4-76

INTERRUPT TIMING *1 ‘(MB8432-90/90L/90LL | MB8432-12/12L/12LL | ) [win [wax [min [ax | a FS OO ET [intRestTme | te ST tm ts INTERRUPT CYCLE TIMING DIAGRAMS *1 INTERRUPT CYCLE roopess. (ADDRESS ,) WE WE) (ADDRESS a) | ten WE, We, | &, ANNNANUAAAANANNANUUUAAARAAS bw Le mm {UNTA) V7A Undefined Note: “1 Applies to MB8431 only. 4-77

DATA RETENTION CHARACTERISTICS (Recommended operating conditions unless otherwise noted. a So ee ee ce | bet Ren Si Ca ee ee re ee ee [_oxaRewnton Setip Tene Te Pe [_operatonacoven tine we Note: 11 VeceVone3V, CS. & TSeVec-0.2V "2 Vowe3V, TaxO°C 10 40°C, DATA RETENTION TIMING DATA RETENTION DATA RETENTION MODE Vee sv Vor 45v 4 . . = Dav TB2Von-0.2V 22 POWER ON/RESET CHARACTERISTICS (Recommended operating conditions unless otherwise noted. MB8432-90/90/90LL | MB8432~12112L/12LL [win [Mex [win [mex | | Power UpTime*t tm fos Tso fos Tso Ts | LPoweron Time te a Ps ‘11 This is required to keep normal operation for power on/reset circuit which initialize INT output to “H” automatically when Voc is applied, "2 This i required to keep normal operation for powor on/reset circuit which Voc is repeatly tum orvott POWER ON/RESET TIMING a5v Vee o2v torr ca 4-78

‘Eunction Description: 1. ORGANIZATION: MB843 1/32 are 2K words x 8 bit Dual port Static Random Acoass Memory. Each port has independent addresses, chip eolect (C5), write enable (WE), output enable (OE) and data inpuvoutput (V0) functions. 2. SLAVE BUSY FUNCTION: In order to do bit expansion using 6 bit width dual port RAM such as MB421/22, wo or more parts should be connected paralel. But such case, there is a possibility, which depends on arbitration timing, of outputting BUSY signal to ditferent ports and put both CPUs in waiting state. This causes a trouble. Using MB8431/32 which have slave busy function (busy input) is one of the solutaion for such trouble, Bit expansion is easily achievable to pair-use slave type dual port RAM such as MB8431/32 and master type dual port RAM such as MB8421/22. (Example) As an example, Fig! shows 16 bit dual port memory system. inthis systom, master type Dual port RAM (MB8421/22} judge atitraton for address contention and output rest ofthe judgement from BUSY pin. This output retumed to CPU and make the CPU in waiting state and also the output is applied to slave type dual port RAM (MB843 1/32). Though slave type dual port RAM (MB8431/32) do not judge for arbitration, they have BUSY input pin and inhib writo operation of the correspondent port during “signal form BUSY output of master type dual port RAM (MB8421/22) is appli to the BUSY input. A system consists of one master dual port RAM (MB8421/22) and three slave dual port RAMs (MB8431/32) is harmonized for 32 bit application. cpu CPU ROY 0 A A vo ROY A Ae MB8421 or Maeze ee La Ae B8431 or wae432 vo, (Slave) VOn ‘BUSY, BUSY 4-79

1. INTERRUPT FUNCTION: _ ‘The interrupt function (INT) is provided to allow communication betwoen the systems on either sides of the dual-port RAM. INT. is set to low, when the processor on the right port writes to address 7FE (AO=L and At to A10=H). INT. is thon reset to High, whon tho left port acknowledges by reading the same address 7FE. Thus the address 7FE is like a 8 bit word mail-box transferring information from the right-port to the fett-port INT. on the other hand is set to low, when processor on the left port writes to the address 7FF (A=0 to A10=H). INTs is reset to High, when the right port acknowledges by reading this address. Hence, the address 7FF is a socond 8 bit word mail-box transferring informaton form the left port tothe right por. ‘The INT, and INTs are set to High on power-up. Ifthe ports in the standby mode, it can stil get interrupted by the processor on the other sido In case he BUSY flag is set to low, then the pertinent port can not set or reset the INT flag. 4-80

fe = ses & & fas = #5 = E> bey. Es cB we toy, 3 ES we AIO C4 45 [7] BUSY, INT, Cis 49(>) BUSY, OE cis 44) A108 NC. cis 48) INTh AOL cjé 43(E) OE, Ai C6 473 NC. an Gq 2 Aon oe = 2B Adm an je 41 Atm A. Ee 45 (2) O&n Aa cis 40 FF) Ad, Al cio 445 Ad, & os SB ie mE 4B te me fe SBS m ore SB i AB Cji2 37EED Ady AA Cji2 415 Ade AN C413 36) Abn ASL C413 40) Ada AB, Chia 35(E5 Ayn AB, C14 395 ASa AS C15 340) AS, AX C15 38() Abe % Be 3 ie a ie SB vo. C417 32) vO7_, AS C417 36 fE) AB, vor. Cj18 31) vo6, von Cys 355 Aan vos, C19 30) vOS, vo. C19 34) VO0, vos. 20 29) vO4, von, C420 33F VOtn vos, C2 28) vO3, vos. C21 327) Wen vos, Cj22 273 vee, vou, Gj22 31 vos, vo7, C423 26 Win vos, Cj23 30) VOd_ wy Be 2B ise ee ie oft oh (oe Bae ae I oo Ses 25 ton | 4 | ryan p ra og Sues oslo yadda? nonnnngnponon G'ea"61" 59” 5755 53° ne. Ct S515 NC. oR C2 50f=) NC. AQ, C43 49) OE Ay C4 48 Adw Aa C45 470 Ata ax Ce 46S Ady aa 7 fo an ax Gls af aan Aa C9 436 Ada an Gro TOP VIEW 265) Aen AR Ct 415 Ata a, G2 405) Ase eo Ge sae NC. (4 33 NC. ne Gu SE Ks vo, jis 36 No. yn Ee SENS vor, Cj1e 34) OG, vos, C419 333 VOG_ ely Bby yey 1 UOUDUUUDU0UCU vagwoo ogtaee 388533 3985983 wen 4-81

52-LEAD PLASTIC DUAL IN-LINE PACKAGE (Case No, : DIP-52P-M01) [ ~~ 1.880 998147 25 +920) i AAAAAAAANAAAAAAAAAAAAAAAAA - oii 15" MAX Kx (380% Pru? O poe | Fi TP UUUUUUUUUUU UU Lt —f 029° 020 : o10+ 002 11.0075 5% o251005 AUT POA OTT TET TT 207(8.25) MAX 1 one 770) oros007 || ore+00e =| czas mn 1.750444 45) REE Dimensions in ©1988 FUNTSU LIMITED D52002S-2¢ inches (imeters) 4-82

48-LEAD PLASTIC DUAL IN-LINE PACKAGE (Case No, : DIP-48P-M02) [ 198: Ben paanonansansanananaaanas mors t 15 Max / 543+ 010 p (13.80+0 25) L TP to20 +920 010+ 002 || ost G20 oso" en | AAR SPURagupapagagayagegepagagagagalm 19514 96) MAX | 11813 00) MN 05041 27) | 1012.54) || ore+ 003 MAX TYR (0.45 +008) 020(0 51) MIN, Dimensions in ©1988 FUJITSU LIMITED 048003S-3¢ inches (millimeters) 4-83

64-LEAD PLASTIC FLAT PACKAGE Cone MFP) rg > 972 + 016124 7040.40), . \\ 787.20 00) ——- 55 _O0210.05) MIN * | (STAND OFF) TAA ADRR ARRAN ANA DE _ 2) MUUUUMUUUUULUUU 2 Ss — i — ES 6422 016 a ES | 736+ 016 (16.300 40) =! O © [BB _ lero = Pied E= | | “ TITMUTTN NUMAN HUH » { = _| vero wo» SODDODODDDOD ODD BOUL - 0s» oo 03941100) 016+ 004 (| 0081020") L008 + 002 TR (04020 1071 0081020) Hj NSE re i tn {By 00810 757 i} ‘ 00710 18) | | . i 02510.63) (120020) | Dimensions in ©1988 FUJITSU LIMITED F64005S-6C inches (milhmeters) 4-84