MB84256A-70 FUJITSU | Alldatasheet
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November 1992 foe) Sere FUJITSU SSS ara SHEET = 32,768 WORD x 8-BIT CMOS STATIC RANDOM ACCESS MEMORY WITH DATA RETENTION Zz ‘The Fujitsy MB84256A is a 32,768-word by 8-bit static random access memory fabricated with A Ze a 2 CMOS silicon gate process. The memory utilizes asynchronous circuitry and may be Za Aa maintainedin any state for an indefinite period of ime. Allpins are TTL compatible, anda single Cer AW +45V power supply is required. Nh en ‘ Hy SV The MB&4256A Is ideally suited for use in microprocesser systems and other applications. y where fast access time and ease of use are required. All devices offer the advantages of low power dissipation, low cost and high performance. PLASTIC PACKAGE DIP-28P-MO2 © Organization: 32,768 x 8 bits ¢ Fast acooss time: 70nsmax. _ (MB84256A-70/-70L/-7OLL) LZ» 100ns max. (MBB4256A-10/-10L/-10LL) LIE, <a '* Completely static operation: No clock required L- oN V | y ‘© TTL compatible inputs/outputs Aa oil | Three state outputs Ge V © Single +5V power supply, +10% tolerance sy i} © Low power standby: <a) CMOS level: 5.5 mW max. (MB84256A-70/-10) Y 5 0.55 mW max. (MB84256A-70L/-70LL/-10L/-10LL) PLASTIC PACKAGE TTLievel: 165mWmax, _(MB84256A-70/-70L/-70LU-10/-10U-40LL) DIP-28P-Mo4 © Data retention: 2.0 min SOP PACKAGE; Soe Page 5-14 © Standard 28-pin Plastic Packages: TSOP PACKAGE; See Page 5-15, 5-16 DIP (600mit) MB84256A-xx(ULL)P Skinny DIP (200 mil) MB&4256A-xx(L/LL)P-SK soP MB84256A-xx(L/LL)PF TSOP (normal bend) MB84256A-xx(L/LL)PFTN PIN ASSIGNMENT TSOP (reverse bend) MB84256A-xx(U/LL)PFTR: Au Oi 285 Veo ABSOLUTE MAXIMUM RATINGS (see NOTE) Aa= bs b= Ne eee eee & di eB De rowew 22 OE input Voltage iN 0.5 t0 Voc 40.5 v A Cs 2s, Ao 10 wh GNOC] 14 18 WO, Storage Temperature Teta 40 to +125 °C NOTE: Permanent device dar ‘occur if the above Absolute Maximum Rath Thle device conmane Grout to prowect te nove oat ae eecadod” Eunstonal operation should bo resicted to the congitons as | $1nn%s ese eaeca noe ees Naka om Setalled in the operational sections of this data sheet. Exposure to absolute | apptation any votage higher han maximum aiedvolages maximum rating conditions for extended periods may affect device reliability. to this high Impedance ciroul. ee Ccovyrgnt © 1982 by FUJITSU LMITED 5-3 mm 3749756 0005991 117 a
Fig. 1. MB84256A BLOCK DIAGRAM AD O -_ovcc Alo ne f Hl o.oo A3 0 ADDRESS ROW (256 x128x8 AsO BUFFER DECODER MEMORY CELL ARRAY AS © 46 © A7 © cs | te: | ABO aoe VOGATE & S ADDRESS A130 Al40 : 7 Weo wo2 wos OS «08 ‘TRUTH TABLE [es [ee [we] woe TSN | toon | fou [x [xT Notseteciea [se] ign z | pe [on] cour pisate [cc igh-z_ | ee ee a ee CAPACITANCE ra = 25°C, # = 1mtz) ee a a WM 3749756 0005992 053
RECOMMENDED OPERATING CONDITION (Referenced to GND) [ie pee TT sete ee eae a a ec a DC CHARACTERISTICS (Recommended operating conditions otherwise noted.) ERE oe dee eel Gbeaeeeset omeeeeeal aoa Sandy Supt Cunt [eo fosevecoav [fs ff [im | a cS Dc ee de operanasurey |__| y= Mo | fe | fey, carent [| tour = Oma Pf ef ee Vio = 0V 10 Voo Output Leakage Current lwo BS = Vay or OE = Vay oF pa WE = Vi. I CD [ettonene we Perf oe Pe oe [| [_oumurrin veteve [vow tovemsama [ee [Tee TT [owptowvetace [va [ txnema Toe TT I Note: All voltages are referenced to GND. Fig. 2—-AC TEST CONDITIONS @ Output Load ‘© Input Pulse Levels: O6V 10 2.4V +v © Input Pulse Rise & Fall Times: ns (Transient between 0.8V and 2.2V) ‘© Timing Reference Levels: Input: Vi20.8V, Viy=2.2V hy Output: Vox=0.8V, Vou=2.0¥ Dou * Including Jig and stray capackance (7) ; a I Se [eat [raxea] sine [ro0or [escort tz andi | Ed 5-5 me 3749756 0005993 TIT ml Lee...
Seca _xi AC CHARACTERISTICS (Recommended operating conditions otherwise noted.) READ CYCLE *? |__Read Cycle Tne ta [__Adcross Access Tine @ [wa tee] | C81 Access Timo | thos Pte | TT CO as | OutpurHei trom Across Charge | ow | | it~ i | |_Chip Selectto Output LowZ"¢ [tax [10 | ouruénabie we Ovputlow2* | wz | sf | 8 |] _] |__ chip SelecttoOurputhigh-2@ [tae [asd de | READ CYCLE TIMING DIAGRAM *1 READ CYCLE 1: ADDRESS CONTROLLED*2 tRc ADDRESS TAR. 10H DOUT PREVIOUS DATA VALID DATA VALID READ CYCLE 2: TS CONTROLLED*3 RC. ADDRESS ws SSSNPs i LOLOL tACS. hi i= = oE SSSSSSSs Vk OLA VL 10H72- a pee at pout —_ <a ERX: undennes Note: "1 WEis high for Read cycle. "2 Device is continuously selected, CS = OE = VIL. "3 Address valid prior to or coincident with CS transition low. *4 Transition is measured at the point of +500mV from steady state voltage with specified Load IT in Fig. 2. 5-6 Mm 3749756 0005994 2b ml
WRITE CYCLE *1*2 | eeaaseacro-rou-70L | | mpeezsertorrou-ioi | [Write cyclo Time? we J tc ns [Atos vais ndorwte [ww [sof | i | Chip Select o End of Write ee | DataHoisTme tw Po Pl ns | [Address Soupting tus | ng | Pt [We wouputowzs ftw | sf Ts Tn [WE woupurnighz swe | Ps ws | WRITE CYCLE TIMING DIAGRAM *1 *2 WRITE CYCLE 1 : WE GONTROLLED two. sooness > “ “ | 5 le ee 8 1AS 1we I we KAS oN — a oxnvao [oo tWHZ wiz HIGHZ vot XXX XXX XD CXX KX] : Undefined Note: *1 If OE, TS are in the READ Mode during this period, /O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. *2 It CS goes high simultaneously with WE high, the output remains in high impedance state. *3 All write cycle are determined from last address transition to the first address transition of the next address. *4,WR is defined from the end point of WRITE Mode.. *5 Transition is measured at the point of +500mV from steady state voltage with specified Load [in Fig. 2 5-7 Mm 3749756 0005995 462 ————eeeeeOeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee SS...
WRITE CYCLE TIMING DIAGRAM “1 *2 WRITE CYCLE 2: TS CONTROLLED two's ee ee us ee tow z AANI a eee a a= oe eee HIGH-Z YY HIGH-Z vou .X_X) KX] :urcetines Note: *1 If 3E, GS are in the READ Mode during this period, VO pins are in the output state go that the input signals of opposite phase to the outputs must nat be applied. *2.if OS goes high simultaneously with WE high, the output remains in high impedance state. "3 All write cycle are determined from last address transition to the first address transition of the next address. *4 tWR is defined from the end point of WRITE Mode. *5 Transition is measured at the point of 500mV from steady state voltage with specified Load IT in Fig. 2 ‘ 5-8 mm 3749756 o00599%6 775 a ee
DATA RETENTION CHARACTERISTICS (Recommended operating conditions otherwise noted.) i So aaa | fe | me | ste Pf pA Pe [mame pm P| a Note: +1652 VDR-0.2V *2VDR = 3.0V,CS2 VDR-0.2V *3 IDR = 5 LA max. at VOR = 3.0V, TA = 40°C DATA RETENTION TIMING DATA RETENTION [5 Data Retention Mode vee 45) vor 4.5V We + -- - - --Y/ tORS. tS > VOR-0.2v fa 22V 22V 5-9 Mm 3749756 0005997 635 a
TIPICAL CHARACTERISTICS CURVES Fig. 3— NORMALIZED POWER SUPPLY Fig. 4 - NORMALIZED POWER SUPPLY « CURRENT vs. SUPPLY VOLTAGE CURRENT vs. AMBIENT TEMPERATURE f Geert), eet TTT a“fTtoa) & Seep eeCooa oe SCN eSCCZECr) 8 SCONE Be SCverrr) 8 Scere p“Choory} ® “Cee 40 5.0 6.0 0 20 40 60 80 VCC, SUPPLY VOLTAGE (V) ‘TA, AMBIENT TEMPERATURE (°C) Fig. 5— NORMALIZED POWER SUPPLY Fig. 6 - NORMALIZED POWER SUPPLY CURRENT vs. FREQUENCY CURRENT vs. SUPPLY VOLTAGE i Vin Se i ini ae een eSB SO in ee a7 PTAs “CMC 1 23 10 2030 4.0 5.0 60 {, FREQUENCY (MHz) VCC, SUPPLY VOLTAGE (V) Fig. 7— NORMALIZED POWER SUPPLY Fig. 8- NORMALIZED ACCESS TIME vs. CURRENT vs. SUPPLY VOLTAGE ‘SUPPLY VOLTAGE ESOT SONECET a 82 of BLA ee of | TOPS I e SOOT eB CCr rR PORTE? “COE 2 0 20 40 60 80 40 45 5.0 55 60 + TA, AMBIENT TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V) 5-10 Me 3749756 0005998 S57] a
TIPICAL CHARACTERISTICS CURVES (Continued) g fet TET g fete OGG? dee een BCA) 8 Or eC Arr) = “Cer eecroor 8 Jae e°CPPPPA) # “CEPT 0 20 40 60 80 100 200 300 400 500 T,, AMBIENT TEMPERATURE (°C) ,, LOAD CAPACITANCE (pF) Lo 5-11 me 3749756 0005999 408 mm
0 EE EEE eee
(Suffix: P) 26-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-26P-M02) 15°MAX AOA | et -() | an (13,800.26) .600(15.24) TP Sd PEPER PEPE eee ee SS5= 7? ee rea (98,73122) aa o10+,002 (0.25+0.05) 099 +;220 H .062(1.58) MAX I come, 5 | CTF STEER SEGRE Ge aamaeae ir, .195(4,96) MAX YOR OOO OOOO OY ao [| 118(3.00) MIN re 0909 018.003 Dimensions in ©1991 FUJITSU LIMITED D28006S-26 inches (milimeters) 5-12 MB 3749756 0006000 625 ml
PACKAGE DIMENSIONS (Continued) - (Sutfix: P-SK) 28-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DiP-28P-M04) +.008 (95, 9649.20 [ 1.902 908 (35.9619 -29 ) | 1 0 rr Ee cy Io (6soto25) TYP ere ava TET eTETE Tere TES eo a a | NH AAA AA ARR AAR AA .207(5.25)MAX .050(1.27) 018.003 MAX 00124) oll omen .020(0.51)MIN Dimensions in ©1991 FUJITSU LIMITED D2e018S-2¢ inches (milimeters) 5-13 Wm@ 3749756 OO0b001 7b4 mm ee
PACKAGE DIMENSIONS (Continued) (Suffix: PF) 28-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-28P-M02) .110(2.80) MAX +010 40.25 _ (MOUNTING HEIGHT) 699” 998 (17-789 20) (0) MIN Noonnp00n0o0nnAAAA | (STANO OFF HEIGHT) Ey HHHHRHHHHHHAHHH | i 465+,012 a Pseaeed (102040:30) > t POH AA RAR RR AHH ‘oot8.008 UOGOHUoGCoOoeood ——F oscto20 1 _ Dotails of "A" part | ”" | 0000.20) | a ! | TOO \\ oonotey” | [SL a0] 1 Lf oftBie | I Dimensions in ©1991 FUJITSU LIMITED F28011S-4C inches (millimeters) 5-14 Me 3749756 OOOL00e LTO mm
PACKAGE DIMENSIONS (Continued) (Suffix: PFTN) PIN ASSIGNMENT (NORMAL BEND) eds Py =i An oo Py =T aa vP wm aq 5 Ds "pi eda 3B 1, Yeo | 20 162 mod 4B oxo Av 2 196) WO, wos 2B ae now, ads wpa ace ops FPT-28P-MO3 “cq? she TOP VIEW 28-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-28P-M03) | Details of "A" part | @ @ ! .006(0.15) | “ | aK @s INDEX \\ | D O = I 1 toe Ts §28+.008 3184.08 .281(7.15) | (MOUNTING HEIGHT) .0217(0.55) ! ace (STAND OFF HEIGHT) rr oe — Dimensions in ©1991 FUJITSU LIMITED F28018S-4C inches (milimoters) 5-15 @@ 3749756 0006003 537 a a
PACKAGE DIMENSIONS (Continued) (Suffix: PFTR) PIN ASSIGNMENT (REVERSE BEND) = = ate sb, ACs wha as npw, fp =P pio, a= Ps 13,500, aes tufa0no Yoo EF 28 1sPavo. eda sue Ao Cl 20 vB, aga 110, am vO, =F) nbs. FPT-28P-M04 =cle apt TOP VIEW 28-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-28P-M04) poo ot === =5 5 | Details of “A part ! @ @ ! 006(0.15) | INDEX = \\ Vol et. r = 014(035) | LEAD No. . a7 ' Ta ! \\ ! —} \\ \\ Lorn Ae -281(7.15) 408t.008 o20+.004 REF [<7] _som10 TYP [ (STAND OFF HEIGHT) 4854.08 poet.002 043" 92% 1.102087 ) (11.80£0.20) (0.180.065) L 3154008 (MOUNTING HEIGHT) | 528+.008 ~ {8.00+0.20) (13.4040.20) / Dimensions in | ©1901 FUNTSU LIMITED F28019S-4C inches (millimeters) 5-16 Mm 3749756 OOOLO04 473 Mm