MB8421

MB8421 FUJITSU | Alldatasheet

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2K x 8 Bits CMOS Dual-Port Static Random Access Memory The Fujitsu MB8421 and MB8422 are 2,048 words x 8bits dual-port high-performance ‘static random access memories (SRAMs) fabricated in CMOS. The SRAMs use asynchronous circuits; thus, no external clocks are required. MB8421 and MB8422 provide the usor with two separately controlled VO ports with independent addresses, Chip Select (CS), Write Enable ), Output Enable (OE), and VO functions. This arrangement permits independent access to any memory location for either a Read or Wt operation — a veel feature for shared data processing sppications. These dovices have an automatic power-down feature controlled by CS. \\ To avoid data contention on the same address, a BUSY input is provided for address arbitration; in addition, MB8421 utilizes an interrupt (INT) flag which allows ‘communication between systems on either side of the RAM. Both devices use a single DIp—tap_moz +5 V power supply and all pins are TTL-compatible, (haee422) Some typical applications for these memory devices are multiprocessing systems, distributed networks, extarnal register files, and peripheral controllers. | 4 | * Organization: 2,048 words x 8 bits * Static operation: no clocks or timing strobe required * Accesstime: — taa=tacs = 90ns max. (MB8421/22-90) (MB8421/22-90L) (MB8421/22/-90LL) tars tacs = 120 ns max. (MB8421/22-12) (MB8421/22-12L) (m@8421/22/-12LL) Dip-s2p-Mo1 * Power consumption for the standard version: (58421) 660 mW max. (Both ports active) ‘385 mW max. (One port active) ‘38.5 mW max. (Both ports standby, TTL) 11 mW max. (Both ports standby, CMOS) * Power consumption for the L and LL-versions: ‘495 mW max. (Both ports active) S 275 mW max. (One port active) a wae 27.5 mW max. (Both ports standby, TTL) pe 1.1 mW max. (Both ports standby, CMOS) 2S * Single +5 V power supply +10% tolerance © TTL compatibie inputs and outputs © Three-state outputs with OR-tie capacity PMC * Electrostatic protection for all inputs and outputs, rrlaaeean) * Address arbitration function: BUSY flag * Interrupt function for communication between systems (MB8421 only): INT flag . * Data retention voltage: 2 V min. * Standard Plastic Packages: 48-pin. DIP MB8422-xx(ULL)P S2-pin DIP MB8421-xx(ULL)P Tye Gone Gone oy & ? ray pt pin QFP MB8421-xx(ULL)PFO cara os Wo se eager cu ewe: tay wage ign’ tan manure voages tae Nk rpadance crt, ‘Coprigh © 1680 by FULITSU LBTED and Fits Melero, 4-53

ABSOLUTE MAXIMUM RATINGS ' ? a NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device relablity. 4-54

Fig. 1 ~ BLOCK DIAGRAM OF MB8421/22 aor) Chath Wen ct a, D Ct K—] dEa . WO0E-VOTL ps ill Vo vO HM ew 008 “07a Lett data © it eutier Buiter A rignt Data ™ | || . a Cotumn . Ic AIO Til eek in Ata” A1Oq 4 | woe il eres imerrept {50 WT. (Note) <7} {> Wir (Note) NOTES: MB8421 oniy | VO CAPACITANCE «za = 25 °c. = 1. mz) | [parameter | svmbet ——| tye ox Tun : [input Capacitance (vn=ovy | ONT Tt ) [wo capacitance (wo=ovy | ovo] tr 4-55

MB8421 ~ Rew MB8421 — aR iew MB8422 - Top View (DIP-52P-Mo1) (FPT-64P-M01) (D1P-48P-M02) ; : a, 9 ees egebee Bq Fp vee § ese rae fede sipasa 2 eklalsis $ SWE IR < Bu Oa veo neq 5 apintr gods SP No "aioe + pics Ao. G6 7B nc. de. Ge sof No Orcs “6B Don aocg e “spoeq aig 8p aon ang? 42 aon Aad 12 Paar asda 4B ata ascQir 38D Aen ascq 3 oP) Aan, seco oP Asa Ac G12 a7 Dasa vosu 23 30B vosk vost 19 33 Pos, vos. Gee 27B voan $8oS55> 7259838 allow asynchronous read and write operations to any memory able (OE) control that is active in the read mode and enables feature controlled by TS that places the respective port in the shown in the following Truth Table; a simplified block diagram standby mode when the chip is deselected (CS is HIGH). _of the dual-port SRAM Is shown in Fig. 1 4-56

MB8421/22-90/-90L/-S0LL. LEFT PORT INPUTS! | RIGHT PORT INPUTS! FLAGS: FUNCTION [_riwi] cs. | oe: | rive] GS] en | Busy. | BUSA . [x [oa [x x x x TT Let Port in Power Down Mode fox [x [x x Ta x Tn TT ight Port in Power Down Mode Poe x x xx TT ata on Lett Port written into Memory | [ow fo ex x xT ata in Memory Output on Lett Port (x x x xT ata on Right Port Written Into Memor Px a TT ata in Memory Output on Right Port NOTES: 1. AQL-A10.# AOR - A10a 2. H= HIGH, L = LOW, X= Don't Care The arbitration logle resolves an address match or chip-enable 1, When addresses for both the left and right ports match match and determines the access priority. In both cases, an and are valid before CS Is active, the on-chip control active BUSY flag is set for the port-in-waiting. Since both logic arbitrates between TS and Ta for device ports are asynchronous. there is the possibility of accessing access. Refer to the following Truth Table for signal the same memory location from both sides. In the read mode, states: timing detail Is shown later In this data sheet this condition is not a problem. However, this is a problem under “Data Contention Cycle No. 2 (CS controled) .” when both ports are in a write mode with different data words 2, when TS, and TEaare LOW before an address match, ‘or when one port is reading and the other is writing. When both ‘on-chip control logic arbitrates between the left and right ports access the same memory location, the on-chip addresses for device access, Signal states for this arbitration logic determines which port has access and the condition are shown in the following Truth Table: timing BUSY flag for the delayed port Is set active LOW and all detail |s shown under “Data Contention Cycle No. 1 operations on that port are inhibited. The delayed port can be (Address Controlled) .” accessed when the BUSY flag becomes inactive. Basic modes of abitration are described in subsequent paragraphs. ARBITRATION WITH ADDRESS MATCH BEFORE CS LEFT [RicHT Port TFtacs | ___teFT PORT = SHT PORT FLAGS, FUNCTION ivi] Be | Oe: | Ao.-A10 | wwe Sn | Cen [Adm-AtO.q BUSY. | BUSYA . Left Operation Permitted Right Operation Permitted } x Le [oe [inwron [oc Peet [oc [aren [| Rarer ee NOTES: X = Don't Care, L = Low, H = High, LST= Low Same Time, LBR = Low Before Right. LBL = Low Before Left ADDRESS ARBITRATION WITH CS LOW BEFORE ADDRESS MATCH LEFT PORT, RIGHT PORT FLAGS ae ET <= aT LASS FUNCTION ) Loft Operation Permitted Right Operation Permitted Dee De De DLT on ocr i NOTES: X = Don't Care, L = Low, H = High, VST = Valid Same Time, VBR = Valid Before Right. VBL = Valid Before Left 4-57

oe SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSe Whon both TS. and TEa are low at the same time For the Intel 8086 and Fuliteu"s MBL8086 as woll as most othor (TS controlled) or when both left-and-right addresses are microprocessors, the asynchronous ‘BUSY signal can be valid at the same time (address controlled), the BUSYatlag for directly tled to the READY Input, providing setup-and-hold the right port is set to the active LOW state and access Is time requirements are mot granted to the left port. The Interrupt (INT) function provides communication between acknowledges by reading address 7FF, TN Is then reset to systems on both sides of the dual-port RAM. iNT, Is set HIGH. Hence, address 7FF serves as a second 8-bit mailbox, LOW when the processor on the right port writes to address transferring information from the left port to the right port TFE (AO = L and At-AIO = H). When the left Port on power-up, iW, and Wja are set to @ HIGH state acknowledges by reading adéross 7FE, INTL Is then reset t2 However, ane nar Is the Standby mode, the standby sort HIGH. ‘ln essence, address 7FE serves as an 8-bit maibox can gti be Interrupted by the processor on the other port. But that transfers Information from the right port to the left port. if the BUSY flag is set to the LOW state, the port associated \\Wnen IN is set LOW, the processor on the left port writes with that flag cannot set or reset the THT flag to address 7FF (A0-A10-H). When the right port (Referenced to Vss) a a Recommended Operating Conditions unless otherwise noted. pea217 Maeea1aeaz2 symbol Condition 8422-90 /12 =900/-90UL/nt2L /-12UL [Min [Max [Min [Max | Operating Supply Current | ICC | Gycle= Min (Both ports Active) fOr Wm 120 ma ‘Both parts at Standby ‘Qne portat Standby 8, or CSq =VIH, 7 Standby 1OUT = 0 ma. Supply Current 1583 |” Both ports at Full Standby S__& CSq> Vee -0.2V 0.2 ine pork gt Full Standby four = Oma, troutrignvorage | vin [aa veo a [a2 [vowel v | Outout Low Voltage (OUT = 3.2 ma a ee NOTE: The BUSY and iNT pins require pull-up resistors because they are open-drain outputs. 4-58

[Recommended Operations Conditions unless otherwise noted. Parameter symbot |_mabeze-ovsocsou | hgseze-tenau nett [min [Max [min [Max | [nea cycotime S| tee | fT TT [Aderess Access time | th! | ToT t20 ne [chip seisct Access time |S tucs =| foo pons [output Enable Access Time | tue =| | wo TT cone [Output Hold from Address Changs | ton | to [To Tre [Chip Select to Output tow-z (Note) | ta fs | Ts Te [Output Enabio to Output Low-2(Note | oz | os | [| s [ns | Chip Select to Output high-z (Note 1) a O [output Enabie to Output High-ziNote) | tow | | ao | [so] rs [Power up trom chin soot | Ste TS | fT rs [Power down trom Crip Sect | te | To TT eo Ts Read Cycle No. 17" *: | 4 | eT tac | fr to | cour awambaavae Ws Read Cycle No. 27: cE Wiis i H LLLYTILTELLTLTL : Po fe tor + >} be tone! a ee: Rte | pout Hire TOE tava > | ec ee ee oe Current 50% 50% : IsB ‘ tegena: [KRW Don't Care Undefined NOTES: 1. Transition s measured at a point of 500 mV from steady-state voltage with an output capacitance of SPF. 2. WE Is High during read cycle. 5. Device is continuously selected (CS = OE = VIL) 4-59

————SSSSSSSSSSSSSSSsSSSSSSSSSSSSSSSSSSSSsSsssseseseseSese AC CHARACTERISTICS (Continued ‘Weani-o0/e0\\ aot | waaeei—variaLnae symbor |_Msseze-so/sou/saut | Masez2—te/taL/tatt [Min [Max] Min Tax | Write Cycle Parameters & Timing Diagrams. | Write Cycle Time two T9080 Ts | Address Valid to End of Write tw as 00 rs | “Chip Select to End of write tow as | dT 100 | id rs +d [Address Setup Time tas oo rs] |__Write Pulse Width 7 tw 600s | Write Recovery Time twa 0 rs | Data Vaid to End of Write tow aot rs Yt [Data Hote Time ton oo rs |_Write Enable to Output Low-Z (Note) [tow oo rs Wate Enable to Output High=Z_ (Note 4) __t_tw2 {es | Write Cycle No. 1 (WE Controlled) ':? <i i : $= tow H a sg me be— tas bp we ———+}o twa H Hi tow. ty i Hloh-z be tow hee tO ign % ZTE MMT Ke tonz—ay i PYYYYYVYY YY YY LYTLE High-Z our EXXXERXXKXXKERRRKK are Write Cycle No. 2 (CS Controlled) 1-2-3 Aaaresg KT >=—R eo oe i pL ag ty, + tashery jf /}—-——_ twr, oh wr i i J tow oe ton 9} High-z H b ° He TOK High-2 tz twet—e| * tow warreeccnnt High-2 WH bouT KXKXXEKEXERKX > TRAX Legend: [XXX] Don't care Undefines NOTES: _ 1. The Write Enable (WE) signal must be high during an address transition. 2, If the Output Enable (OE) and Chip Select (CS) signals are in the Read Mode, the associated 1/0 pins are in the output state: accordingly, input signals of opposite phase must not be applied to the outputs. 3. If GS goes high prior to or coincident with the low-to-high transition of WE, the output remains in high-impedance state 4, This parameter is specified at a point + 500 mV from steady-state voltage with an output capacitance of 5 pF. 4-60

AC CHARACTERISTICS (Continued, qwpeazt-oorgo. | mpedzt-12/12L symbot |__MBsdaz-so/s0c_| masdz2—12/120 _ [min [Max] in | Max_ | BUSY Parameters & Data Contention Timing [BUSY Access Time from Address [| taaw TT a5 TT 60s | [BUSY Output High-Z trom Address «dt twas Tas Peo ns [BUSY Access TimetromcS | twa [Tas ons [BUSY Output High-Z from CS] toe Pas go ns [arbitration Prionty Setup Time Tans [20 Ts Te | Data Contention Cycle No. 1 (Address Controlled)": ?: ' y be tees —>} i WS, j i (BUSY,) BS x Data Contention Cycle No. 2 (CS Controlled)’: *: (Ga) X_ Address t= Address R OO Be) ———x,__ ravens L = Aacress R | ee | ‘BS¥a : : (BUSY) a | NoTEs: 1. Incase of dual-access at the same memory location, the port that accesses the RAM first sets the BUSY flag HIGH. 2. Chip Select (GS) signal must be low before or coincident with an address transition 3. Address Is valid prior to or coincidence with the high-to-low transition of GS 4-61

AC CHARACTERISTICS (Continued, Symbol Mp8422-90/90L_| _MB8422-12/120 [min [max [min [max | [TT set time (wotey ts we v0 ne [_int Reset time wotey Tt Tw TT tc Ts id WT Reset Time (Note) | _*n ff 8} 100 fins __] Interrupt Cycle Timing i a A ee be ns >} fe wn} Wa { : i WEY) <_# ‘ - L

4 TEE = - ——

(Wer) i i i EL p AAAAUUUANANARUVANRURRURERRURRNTRUNRRRRRNE i (OER) ; r H B -—— te Legend: Undefined NOTE: MB8421 onty 4-62

AC CHARACTERISTICS (Continued) DATA RETENTION PARAMETERS & TIMING symbol §8422-90/12_|_MB8422-90L/12L Data Retention Parameters & Timing - [ata Retention supp votage | ORT .0 [ss [ 20 [oss [ov | [bata Retention Supply Curent (Note) | or | | oe | oor [ma | [Data Retention Setup Time | tons, =f Po ns [Operation Recovery time Eta Ete | tno Ts | }Speration Rec owe NR IEEE t Data Retention Mode t Vee i } av KU ORL Fa as 1 TS2> Voo-0.2V NWN f2.2v 22v' Legend: Undefined NOTE: Vce = VOR = 3V TSL&TSaz Veo - 0.2 AC TEST CONDITIONS Input Pulse Levels: 0 to 3.0 wv +5V Input Pulse Rise & Fall Times: ty. te= Sns Timing Reference Levels: 1.5V 1250 2 ss a Output Loads vo Byer, 100pF wt (Note) > 775.0 a (hete) NOTE: Includes jig and stray capacitance 4-63

(Suffix: P) 48-LEAD PLASTIC DUAL IN-LINE PACKAGE (Case No. : DIP-48P-M02) ent ——— [noes 7 t 4 ) Prone 20 O 50011528 ls POT TOOT TOTTI U TTT TY t ULL ost 9 050" 8 010+ 002 (0.65795, 27985) (0252005) 4 | ——— Na a a alaararatataentalatnraletetarateteeatat 19514 96) MAX J il VEU T Tey 1183.00) min 05011 27) $4) [ores a ee 020051) MIN ©1988 FUITSU LIMITED 048003S-3¢ techs ater) 4-64

PACKAGE DIMENSIONS (Continued) (Suffix: PFQ) 64-LEAD PLASTIC FLAT PACKAGE (Case No. : FPT-64P-M06) aes —— 972 016194 707040 - conicos an je 729120001 2 | | (gtamoeorr TRO TORO DD RO DODO DORE 7. | x) SUMMIT | = = } = = \\ | 642+ 016 =o) OEE here-ee0 | a ES ss1114.00 472(12.00) Se] inoex = | = ef | + | ar TITTUNN TON UN TOUT OD a | = t ceno no pPUODDDODUDDDEODOOOO oa 002 £ Detais of “A” part H Details of “B" part i oro eo 7 rt a Page slallalnialalalalaialaisialsiainie-vem : 012(0.30) |! i a ax " 709 (18.00) REF———~. 1 T cae tt 422.08 ©1990 FUJITSU LIMITED F64013S-2¢ inches trenters) 4-65

PACKAGE DIMENSIONS (Continued) (Suffix: P) 52-LEAD PLASTIC DUAL IN-LINE PACKAGE (Case No. : DIP-52P-MO1) AnAAAAAAAAAAAAAAAAAAAAMAM a3 15 MAX oo it 543+ 010 | \\ 2 600115 24) | 0397 $20 ee — 010 002 19.0073 °% 10252005) TITEL AUTUFTACOE TEU U UTD PCE TTT ETD 207(8.25) MAX. i \\ Vy 118(3.00) main | | 07011 778) cros.o01 _||_ 018+ 004 (02010 51) MIN wax TW F7ez018 ~~ Toas-01 L 1 750144 45) REF ~ Dimensions in ©1988 FUJITSU LIMITED 0520028-20 inches (millimeters) 4-66