MB82DP02183D

MB82DP02183D FUJITSU | Alldatasheet

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DS05-11436-1EFUJITSU SEMICONDUCTOR DATA SHEET Copyright©2006 FUJITSU LIMITED All rights reserved MEMORY Mobile FCRAMTM CMOS 32M Bit (2 M word × 16 bit) Mobile Phone Application Specific Memory MB82DP02183D-65L CMOS 2,097,152-WORD x 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface ■ DESCRIPTION The Fujitsu MB82DP02183D is a CMOS Fast Cycle Ra ndom Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 33,554,432 storages accessible in a 16-bit format. MB82DP02183D is utilized using a Fujitsu advanced FCRAM core technology and improved integration in com- parison to regular SRAM. This MB82DP02183D is suited for mobile applications such as Cellular Handset and PDA. *: FCRAM is a trademark of Fujitsu Limited, Japan ■ FEATURES

• Asynchronous SRAM Interface  Fast Access Cycle Time : t AA = tCE = 65 ns Max  8 words Page Access Capability : t PA A = 20 ns Max  Low Voltage Operating Condition : V DD = + 2.6 V to + 3.5 V  Wide Operating T emperature : T A = − 30 °C to + 85 °C TJ = − 30 °C to + 90 °C  Byte Control by LB and UB  Low Power Consumption : I DDA1 = 30 mA Max IDDS1 = 100 µA Max  Various Power Down mode : Sleep 4M-bit Partial 8M-bit Partial  Shipping Form : Wafer/Chip

■ PRODUCT LINEUP ■ PIN DESCRIPTION Note : Refer to “■ P ACKAGE FOR ENGINEERING SAMPLES” for additional pin descriptions of FBGA package supply. Parameter MB82DP02183D-65L Access Time (Max) (tCE, tAA) 65 ns Active Current (Max) (IDDA1) 30 mA Standby Current (Max) (IDDS1) 100 µA Power Down Current (Max) (IDDPS) 10 µA Pin Name Description A20 to A0 Address Input CE1 Chip Enable 1 (Low Active) CE2 Chip Enable 2 (High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Control (Low Active) UB Upper Byte Control (Low Active) DQ7 to DQ0 Lower Byte Data Input/Output DQ15 to DQ8 Upper Byte Data Input/Output VDD Power Supply VSS Ground

■ BLOCK DIAGRAM VDD VSS CE2 CE1 WE LB UB OE A20 to A0 DQ7 to DQ0 DQ15 to DQ8 Address Latch Buffer Row Decoder Memory Cell Array 33,554,432 bit Output Data ControlSense/Switch Column Decoder Address Latch Buffer Input Data Latch & Control I/O Data Buffer Power Control Timing Control

■ FUNCTION TRUTH TABLE Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance *1 : Should not be kept this logic condition longer than 1 µs. *2 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Refer to “■ Power Down” for the detail. *3 : Can be either VIL or VIH but must be valid before Read or Write. *4 : OE can be VIL during Write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. Refer to “(12) READ/WRITE Timing #1-1 (CE1 Control)” in “■ TIMING DIAGRAMS”. (2) OE stays VIL during Write cycle. Mode CE2 CE 1W E OE LB UB A20 to A0 DQ7 to DQ0 DQ15 to DQ8 S t a n d b y ( D e s e l e c t ) HHXXXX X H i g h - Z H i g h - Z Output Disable*1 HL H H X X *3 High-Z High-Z Output Disable (No Read) HL H H Valid High-Z High-Z Read (Upper Byte) H L Valid High-Z Output Valid Read (Lower Byte) L H Valid Output Valid High-Z Read (Word) L L Valid Output Valid Output Valid No Write LH * 4 H H Valid Invalid Invalid Write (Upper Byte) H L Valid Invalid Input Valid Write (Lower Byte) L H Valid Input Valid Invalid Write (Word) L L Valid Input Valid Input Valid Power Down*

2 LXXXXX X H i g h - Z H i g h - Z

■ POWER DOWN Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down mode. This device has three power down modes, Sleep, 4M-bit Partial and 8M-bit Partial. The selection of power down mode can be programmed by series of read/write operation. Each mode has following data retention features. The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. Power Down Program Sequence The program requires total six read/write operations with unique address. Between each read/write operation requires that device be in standby mode. Following table shows the detail sequence. The first cycle is to read from most significant address (MSB). The second and third cycles are to write to MSB. If the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. It is recommended to write back the data (RDa) read by first cycle to MSB in order to secure the data. The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle are don’t-care. If the forth or fifth cycle is written into different address, the program is also cancelled but write data may not be written as normal write operation. The last cycle is to read from a specific address key for power down mode selection. And read data (RDb) is invalid. Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored in a memory cell array may be lost. So, it should perform this program prior to regular read/write operation if Partial power down mode is used. Address Key The address key has following format. Mode Data Retention Retention Address Sleep (default) No N/A 4M-bit Partial 4M bits 00000h to 3FFFFh 8M-bit Partial 8M bits 00000h to 7FFFFh Cycle # Operation Address Data 1st Read 1FFFFFh (MSB) Read Data (RDa) 2nd Write 1FFFFFh RDa 3rd Write 1FFFFFh RDa 4th Write 1FFFFFh Don’t care (X) 5th Write 1FFFFFh X 6th Read Address Key Read Data (RDb) Mode Address A

20 A19 A18 to A0 Hexadecimal

Sleep (default) 1 1 1 1FFFFFh 4M-bit Partial 1 0 1 17FFFFh 8M-bit Partial 0 1 1 0FFFFFh

■ ABSOLUTE MAXIMUM RATINGS * : All voltages are referenced to VSS. WARNING: Semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS *1 : All voltages are referenced to VSS. *2 : This device supports both VDD(31) and VDD(26) voltage ranges on an identical device. VDD range is divided into two ranges as VDD(31) and VDD(26) on the table due to VIH varied according to VDD supply voltage. *3 : Maximum DC voltage on input and I/O pins is VDD + 0.2 V . During voltage transitions, inputs may overshoot to VDD + 1.0 V for the period of up to 5 ns. *4 : Minimum DC voltage on input or I/O pins is -0.3 V . During voltage transitions, inputs may undershoot VSS to -1.0 V for the period of up to 5 ns. WARNING: The recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Min Max Voltage of VDD Supply Relative to VSS*V DD − 0.5 + 3.6 V Voltage at Any Pin Relative to VSS*V IN, VOUT − 0.5 + 3.6 V Short Circuit Output Current I OUT − 50 + 50 mA Storage Temperature T STG − 55 + 125 oC Parameter Symbol Value Unit Min Max Supply Voltage*1, *2 VDD (31) 3.1 3.5 V VDD (26) 2.6 3.1 V VSS 00 V High Level Input Voltage *1, *2, *3 VIH (31) VDD × 0.8 V DD + 0.2 ( ≤ 3.6) V VIH (26) VDD × 0.8 V DD + 0.2 V Low Level Input Voltage *1, *4 VIL − 0.3 V DD × 0.2 V Ambient Temperature T A − 30 + 85 °C Junction Temperature T J − 30 +90 °C

■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes : • All voltages are referenced to VSS.

• IDD depends on the output termination, load conditions, and AC characteristics.
• After power on, initialization following POWER-UP timing is required. DC characteristics are guaranteed after the initialization.
• IDDPS, IDDP4, IDDP8 and IDDS1 might be higher for up to 200ms after POWER-UP or power down/standby mode entry. Parameter Symbol Test conditions Value Unit Min Max Input Leakage Current I LI VSS ≤ VIN ≤ VDD −1.0 +1.0 µA Output Leakage Current I LO 0 V ≤ VOUT ≤ VDD, Output Disable −1.0 +1.0 µA Output High Voltage Level V OH VDD = VDD Min, IOH = −0.5 mA 2.4 ⎯ V Output Low Voltage Level V OL IOL = 1 mA ⎯ 0.4 V VDD Power Down Current IDDPS VDD = VDD (26) Max, VIN = VIH or VIL, CE2 ≤ 0.2 V Sleep ⎯ 10 µA IDDP4 4 M-bit partial ⎯ 45 µA IDDP8 8 M-bit partial ⎯ 55 µA VDD Standby Current IDDS VDD = VDD (26) Max, VIN = VIH or VIL, CE1 = CE2 = VIH ⎯ 1.5 mA IDDS1 VDD = VDD (26) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V ⎯ 100 µA VDD Active Current IDDA1 VDD = VDD (26) Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC/tWC = Min ⎯ 30 mA IDDA2 tRC/tWC = 1 µs ⎯ 3m A VDD Page Read Current I DDA3 VDD = VDD (26) Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA, tPRC = Min ⎯ 10 mA

1. AC CHARACTERISTICS (1) READ OPERATION (At recommended operating conditions unless otherwise noted.) *1 : Maximum value is applicable if CE 1 is kept at Low without change of address input of A20 to A3. *2 : Address should not be changed within a minimum t RC. *3 : The output load 50 pF . *4 : The output load 5 pF . *5 : Applicable to A 20 to A3 when CE1 is kept at Low. *6 : Applicable only to A 2, A1 and A0 when CE1 is kept at Low for the page address access. *7 : In case Page Read Cycle is continued with keeping CE 1 stays Low, CE1 must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. *8 : Applicable when at least two of address inputs among applicable are switched from the previous state. *9 : t RC (Min) and tPRC (Min) must be satisfied. *10 : If the actual value of t WHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting the actual value from the specified minimum value. Parameter Symbol Value Unit Notes Min Max Read Cycle Time t RC 65 1000 ns *1, *2 CE1 Access Time t CE ⎯ 65 ns *3 OE Access Time t OE ⎯ 40 ns *3 Address Access Time t AA ⎯ 65 ns *3, *5 LB, UB Access Time t BA ⎯ 30 ns *3 Page Address Access Time t PAA ⎯ 20 ns *3, *6 Page Read Cycle Time t PRC 20 1000 ns *1, *6, *7 Output Data Hold Time t OH 5 ⎯ ns *3 CE1 Low to Output Low-Z t CLZ 5 ⎯ ns *4 OE Low to Output Low-Z t OLZ 10 ⎯ ns *4 LB, UB Low to Output Low-Z t BLZ 0 ⎯ ns *4 CE1 High to Output High-Z t CHZ ⎯ 12 ns *3 OE High to Output High-Z t OHZ ⎯ 12 ns *3 LB, UB High to Output High-Z t BHZ ⎯ 12 ns *3 Address Setup Time to CE1 Low t ASC −5 ⎯ ns Address Setup Time to OE Low t ASO 10 ⎯ ns Address Invalid Time t AX ⎯ 10 ns *5, *8 Address Hold Time from CE1 High t CHAH −6 ⎯ ns *9 Address Hold Time from OE High t OHAH −6 ⎯ ns WE High to OE Low Time for Read t WHOL 10 1000 ns *10 CE1 High Pulse Width t CP 10 ⎯ ns

(2) WRITE OPERATION (At recommended operating conditions unless otherwise noted.) *1 : Maximum value is applicable if CE 1 is kept at Low without any address change. *2 : Minimum value must be equal or gr eater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR). *3 : Write pulse is defined from High to Low transition of CE 1, WE, LB or UB, whichever occurs last. *4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE whichever occurs last. *5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *6 : Write recovery is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first. *7 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns after CE1 is brought to Low. *8 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before new address valid. Parameter Symbol Value Unit Notes Min Max Write Cycle Time t WC 65 1000 ns *1, *2 Address Setup Time t AS 0 ⎯ ns *3 CE1 Write Pulse Width t CW 40 ⎯ ns *3 WE Write Pulse Width t WP 40 ⎯ ns *3 LB, UB Write Pulse Width t BW 40 ⎯ ns *3 LB, UB Byte Mask Setup Time t BS − 5 ⎯ ns *4 LB, UB Byte Mask Hold Time t BH − 5 ⎯ ns *5 Write Recovery Time t WR 0 ⎯ ns *6 CE1 High Pulse Width t CP 10 ⎯ ns WE High Pulse Width t WHP 10 1000 ns LB, UB High Pulse Width t BHP 10 1000 ns Data Setup Time t DS 12 ⎯ ns Data Hold Time t DH 0 ⎯ ns OE High to CE1 Low Setup Time for Write t OHCL −5 ⎯ ns *7 OE High to Address Setup Time for Write t OES 0 ⎯ ns *8 LB and UB Write Pulse Overlap t BWO 40 ⎯ ns

(3) POWER DOWN PARAMETERS (At recommended operating conditions unless otherwise noted.) *1 : Applicable also to power-up. *2 : Applicable when 4M-bit and 8M-bit Partial mode is programmed. (4) OTHER TIMING PARAMETERS (At recommended operating conditions unless otherwise noted.) *1 : Some data might be writt en into any address location if tCHWX(Min) is not satisfied. *2 : The Input T ransition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. Parameter Symbol Value Unit Note Min Max CE2 Low Setup Time for Power Down Entry t CSP 10 ⎯ ns CE2 Low Hold Time after Power Down Entry t C2LP 65 ⎯ ns CE1 High Hold Time following CE2 High after Power Down Exit [Sleep mode only] tCHH 300 ⎯µ s* 1 CE1 High Hold Time following CE2 High after Power Down Exit [not in Sleep mode] tCHHP 65 ⎯ ns *2 CE1 High Setup Time following CE2 High after Power Down Exit tCHS 0 ⎯ ns *1 Parameter Symbol Value Unit Note Min Max CE1 High to OE Invalid Time for Standby Entry t CHOX 10 ⎯ ns CE1 High to WE Invalid Time for Standby Entry t CHWX 10 ⎯ ns *1 CE2 Low Hold Time after Power-up t C2LH 50 ⎯µ s CE1 High Hold Time following CE2 High after Power-up t CHH 300 ⎯µ s Input Transition Time t T 12 5 n s * 2

(5) AC TEST CONDITIONS (At recommended operating conditions unless otherwise noted.) Description Symbol Test Setup Value Unit Note Input High Level V IH ⎯ VDD × 0.8 V Input Low Level V IL ⎯ VDD × 0.2 V Input Timing Measurement Level V REF ⎯ VDD × 0.5 V Input Transition Time t T Between VIL and VIH 5n s VDD VSS 0.1 µF 50 pF OutputDevice under Test

• AC MEASUREMENT OUTPUT LOAD CIRCUIT

■ TIMING DIAGRAMS (1) READ Timing #1 (Basic Timing) tRC tCE tASC tCHAH tCP tCHZ tOHZ tOE tBA tBLZ tOLZ tCLZ tBHZ tOH tASC CE1 OE DQ LB, UB Note : This timing diagram assumes CE2 = H and WE = H. Valid Data Output (Output) Address Address Valid

(2) READ Timing #2 (OE & Address Access) Note : This timing diagram assumes CE2 = H and WE = H. CE1 OE DQ tRC tRC tASO tOE tOHZ tOLZ tOH tOH tOHAHtAA tAA tAX LB, UB Low Valid Data Output (Output) Address Valid Address ValidAddress Valid Data Output

(3) READ Timing #3 (LB , UB Byte Access) tRC tAXtAX tAA Low tBAtBA tBA tBLZ tOH tBLZ tOH tOHtBLZ tBHZ tBHZ tBHZ CE1, OE LB DQ7 to DQ0 DQ15 to DQ8 UB Note : This timing diagram assumes CE2 = H and WE = H. (Output) Address Valid Data Output Address Valid (Output) Valid Data Output Valid Data Output

(4) READ Timing #4 (Page Address Access after CE1 Control Access) tRC tRC tPRC tPRC tPRC tPAA tPAA tPAA tCHAH tOHtOHtOHtOH tCLZ tASC tCHZtCE CE1 OE (A2 to A0) (A20 to A3) DQ LB, UB Note : This timing diagram assumes CE2 = H and WE = H. Address Address Valid (Output) Valid Data Output (Normal Access) Address Valid Data Output (Page Access) Address Valid Address Valid Address Valid Address Valid

(5) READ Timing #5 (Random and Page Address Access) tRCtRC tRC tAA LOW tPAA tPRC (A20 to A3) tASO tOE tBA tOLZ tBLZ tOH tOH tOH tOH tAA tRC tPAA tPRC (A2 to A0) tAXtAX CE1 OE LB, UB DQ Notes : • This timing diagram assumes CE2 = H and WE = H.

• Either or both LB and UB must be Low when both CE1 and OE are Low. Address Address Valid (Output) Valid Data Output (Normal Access) Address Valid Data Output (Page Access) Address Valid Address ValidAddress Valid Address Valid Address Valid

(6) WRITE Timing #1 (Basic Timing) CE1 WE LB, UB OE DQ tWC tWR tWR tWR tAS tAS tAS tCW tWP tBW tAS tAS tOHCL tAS tDS tDH tCP tWHP tBHP Note : This timing diagram assumes CE2 = H. (Input) Address Address Valid Valid Data Input

(7) WRITE Timing #2 (WE Control) CE1 WE LB, UB OE DQ tWC tWC tWR tAStWP tWRtWPtAS tOHAH tOES tOHZ tDS tDH tDS tDH Low tWHP Note : This timing diagram assumes CE2 = H. (Input) Address Address Valid Valid Data Input Address Valid Valid Data Input

(8) WRITE Timing #3-1 (WE, LB, UB Byte Write Control) CE1 WE UB DQ7 to DQ0 DQ15 to DQ8 LB tWC tWC tAStWP tWR tWPtAS tDS tDH tDS tDH Low tWR tBS tBH tBH tBS tWHP Note : This timing diagram assumes CE2 = H and OE = H. (Input) Address Address Valid Valid Data Input Address Valid (Input) Valid Data Input

(9) WRITE Timing #3-2 (WE, LB, UB Byte Write Control) CE1 WE UB LB tWC tWC tWR tAS tBW tWR tBW tDS tDH tDS tDH Low tAS tBS tBH tBHtBS DQ7 to DQ0 DQ15 to DQ8 tWHP Note : This timing diagram assumes CE2 = H and OE = H. (Input) Address Address Valid Valid Data Input Address Valid (Input) Valid Data Input

(10) WRITE Timing #3-3 (WE, LB, UB Byte Write Control) CE1 WE UB LB tWC tWC tWR tAS tBW tWRtBW tAS tDS tDH tDS tDH Low tBStBS tBH tBS tBH DQ7 to DQ0 DQ15 to DQ8 tWHP Note : This timing diagram assumes CE2 = H and OE = H. (Input) Address Address Valid Valid Data Input Address Valid (Input) Valid Data Input

(11) WRITE Timing #3-4 (WE, LB, UB Byte Write Control) CE1 WE UB DQ7 to DQ0 DQ15 to DQ8 LB tWC tWC tWRtBW tBWO tBWO tAS tWRtBWtAS tWRtBWtAS tWRtBWtAS tDS tDH tDS tDH tDS tDH tDS tDH Low tBHP tBHP Note : This timing diagram assumes CE2 = H and OE = H. (Input) Address Address Valid Valid Data Input Address Valid (Input) Valid Data Input Valid Data InputValid Data Input

(12) READ / WRITE Timing #1-1 (CE1 Control) CE1 WE UB, LB OE DQ tCHAH tAS tCP tOHCL tCHZ tOH tWC tCW tWR tASC tCP tDS tDH tRC tCE tCHAH tCLZ tOH Address Write Address Write Data Input Read Address Read Data Output Notes : • This timing diagram assumes CE2 = H.

• Write address is valid from either CE1 or WE of last falling edge. Read Data Output

(13) READ / WRITE Timing #1-2 (CE1, WE, OE Control) CE1 WE UB, LB OE DQ tCHAH tAS tCP tOHCL tCHZ tOH tWC tWP tWR tASC tCP tOE tDS tDH tRC tCE tCHAH tOLZ tOH Address Write Address Write Data Input Read Address Read Data Output Read Data Output Notes : • This timing diagram assumes CE2 = H.

• OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence.

(14) READ / WRITE Timing #2 (OE, WE Control) CE1 WE UB, LB OE DQ tOHAH tWRtAS tOES tOHZ tOH tWC tWP tOE tOHZ tDS tDH tRC tAA tOHAH tOLZ tASO tOH Low tWHOL Address Write Address Write Data Input Read Address Read Data Output Read Data Output Notes : • This timing diagram assumes CE2 = H.

• CE1 can be tied to Low for WE and OE controlled operation.

(15) READ / WRITE Timing #3 (OE, WE, LB, UB Control) (16) POWER-UP Timing #1 CE1 WE UB, LB OE DQ tOHAH tAS tWRtOES tBHZ tOH tWC tBW tBA tBHZ tDS tDH tRC tAA tOHAH tBLZ tASO tOH Low tWHOL Address Read Address Write Data Input Write Address Read Data Output Read Data Output Notes : • This timing diagram assumes CE2 = H.

• CE1 can be tied to Low for WE and OE controlled operation. CE1 CE2 V DD 0 V VDD Min tCHH tCHS tC2LH Note : The tC2LH specifies after VDD reaches specified minimum level.

(17) POWER-UP Timing #2 (18) POWER DOWN Entry and Exit Timing CE1 CE2 V DD 0 V VDD Min tCHH Note : The tCHH specifies after VDD reaches specified minimum level and applicable both CE1 and CE2. If transition time of VDD (from 0 V to VDD Min) is longer than 50 ms, POWER-UP Timing #1 must be applied. tCHS tCHH (tCHHP)tC2LPtCSP Power Down Entry Power Down Mode Power Down Exit High-Z CE1 CE2 DQ Note : This Power Down mode can be also used as a reset timing if “POWER-UP timing” above could not be satisfied and Power Down program was not performed prior to this reset.

(19) Standby Entry Timing after Read or Write tCHOX tCHWX Active (Read) Standby Active (Write) Standby CE1 OE WE Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode.

(20) POWER DOWN PROGRAM Timing CE1 WE LB, UB*4 OE DQ*3 tRC tRCtWC tWC tWC tWC tCP tCP tCP tCP tCP tCP*3 RDa RDa RDa X X RDb MSB*1 MSB*1 MSB*1 MSB*1 MSB*1 Key*2Address Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confirm the format specified in “■ POWER DOWN”. If not, the operation and data are not guaranteed. *3 : After t CP following Cycle #6, the Power Down Program is completed and returned to the normal operation. *4 : Byte read or write is available in addition to Word read or write. At least one byte control signal (LB or UB) need to be Low.

■ PACKAGE FOR ENGINEERING SAMPLES

• Pin Assignment
• Pin Description Pin Name Description A20 to A0 Address Input CE1 Chip Enable (Low Active) CE2 Chip Enable (High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Control (Low Active) UB Upper Byte Control (Low Active) DQ7 to DQ0 Lower Byte Data Input/Output DQ15 to DQ8 Upper Byte Data Input/Output VDD Power Supply VSS Ground NC No Connection DU Don’t Use DJ HGFE A MLKCB NC A11NC NC NC NC NC NC NC NC NC NC NC NC NC NC A15 A12 NC A13 NC A14 A16 NC NC DQ15 VSS DQ7 A19 CE2 A20 DU UB DU A18 VSS A10 A17 DQ6 DQ1 DQ13 DQ4 DQ12 VDD DQ3 DQ9 VDD DQ10 NC DQ0 DQ14 DQ5 NC DQ11 DQ2 DQ8 WE DU LB A7 OE CE1 (TOP VIEW) (BGA-71P-M03)

• Package Capacitance (f = 1 MHz, TA = +25 °C)
• Package View
• Package Dimension Parameter Symbol Test conditions Value Unit Min Typ Max Address Input Capacitance C IN1 VIN = 0 V ⎯⎯ 5p F Control Input Capacitance C IN2 VIN = 0 V ⎯⎯ 5p F Data Input/Output Capacitance C I/O VIO = 0 V ⎯⎯ 8p F 71-ball plastic FBGA (BGA-71P-M03) 71-ball plastic FBGA (BGA-71P-M03) Dimensions in mm (inches). Note: The values in parentheses are reference values. C 2003 FUJITSU LIMITED B71003S-c-1-1 7.00±0.10 (.276±.004) INDEX-MARK AREA ABCDEFGHJKLM S 1.09 +0.11 –0.10 +.004 –.004.043 (.015±.004) 0.39±0.10 (Stand off) (Seated height) 0.20(.008) S B 0.10(.004) S 0.10(.004) S AS0.20(.008) REF 0.80(.031) B REF 0.40(.016) REF 0.80(.031) A REF 0.40(.016) ABSMø0.08(.003)71-ø0.45 +0.10 –0.05 +.004 –.00271-ø.018

■ BONDING PAD INFORMATION Please contact local FUJITSU representative for pad layout and pad coordinate information. ■ ORDERING INFORMATION Part Number Shipping Form Remarks MB82DP02183D-65LWT Wafer

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept.