MB82DBS02163D-70L

MB82DBS02163D-70L FUJITSU | Alldatasheet

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32 M Bit (2 M word×16 bit)

Mobile Phone Application Specific Memory MB82DBS02163D-70L ■ DESCRIPTION The FUJITSU MB82DBS02163D is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 33,554,432 storages accessible in a 16-bit format. MB82DBS02163D is utilized using a FUJITSU advanced FCRAM core technology and improved integration in comparison to regular SRAM. The MB82DBS02163D adopts the asynchronous page mode and the synchronous burst mode for fast memory access as user configurable options. This MB82DBS02163D is suited for mobile applications such as Cellular Handset and PDA. *: FCRAM is a trademark of Fujitsu Limited, Japan ■ FEATURES

Asynchronous SRAM Interface Fast Access Time : t CE = 70 ns Max 8 words Page Access Capability : t PAA = 20 ns Max Burst Read/Write Access Capability : t AC = 8 ns Max Low Voltage Operating Condition : V DD = 1.7 V to 1.95 V Operating Temperature : T A = − 10 °C to + 70 °C Byte Control by LB and UB Low-Power Consumption : I DDA1 = 30 mA Max IDDS1 = 100 µA Max Various Power Down mode : Sleep

4 M-bit Partial

8 M-bit Partial

■ PRODUCT LINEUP Parameter MB82DBS02163D-70L Access Time (Max) (tCE, tAA) 70 ns CLK Access Time (Max) (tAC) RL = 5, 6 8 ns Active Current (Max) (IDDA1) 30 mA Standby Current (Max) (IDDS1) 100 µA Power Down Current (Max) (IDDPS) 10 µA

■ PIN ASSIGNMENT ■ PIN DESCRIPTION Pin Name Description A20 to A0 Address Input CE1 Chip Enable 1 (Low Active) CE2 Chip Enable 2(High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Control (Low Active) UB Upper Byte Control (Low Active) CLK Clock Input ADV Address Valid Input (Low Active) WAIT Wait Output DQ7 to DQ0 Lower Byte Data Input/Output DQ15 to DQ8 Upper Byte Data Input/Output VDD Power Supply Voltage VSS Ground NC No Connection DJ HGFE A MLKCB NC A11NC NC NC NC NC NC NC NC NC NC NC NC NC NC A15 A12 NC A13 NC A14 A16 NC NC DQ15 VSS DQ7 A19 CE2 A20 ADV UB WAIT A18 VSS A10 A17 DQ6 DQ1 DQ13 DQ4 DQ12 VDD DQ3 DQ9 VDD DQ10 NC DQ0 DQ14 DQ5 NC DQ11 DQ2 DQ8 WE CLK LB A7 OE CE1 (TOP VIEW) (BGA-71P-M03)

■ BLOCK DIAGRAM VDD VSS A20 to A3 A2 to A0 CE2 CE1 ADV WE OE LB UB WAIT CLK DQ15 to DQ8 DQ7 to DQ0 MODE CONTROLLER COMMAND DECODER ADDRESS LATCH & BUFFER BURST ADDRESS COUNTER ADDRESS CONTROLLER MEMORY CORE CONTROLLER BUS CONTROLLER READ AMP WRITE AMP PARALLEL TO SERIAL CONVERSION SERIAL TO PARALLEL CONVERSION MEMORY CELL ARRAY 33,554,432 bits I/O BUFFER BURST CONTROLLER CONVERTER Y CONTROLLER X CONTROLLER

■ FUNCTION TRUTH TABLE 1. Asynchronous Operation (Page Mode) Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance *1: Should not be kept this logic condition longer than 1 µs. *2: Power Down mode can be entered from Standby state and all output are in High-Z state. Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in "■FUNCTIONAL DESCRIPTION" for the details. *3: "L" for address pass through and "H" for address latch on the rising edge of ADV. *4: OE can be VIL during write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. Refer to "(14) Asynchronous Read/Write Timing #1-1 (CE1 Control)" in "■TIMING DIAGRAMS". (2) OE stays VIL during Write cycle. *5: Can be either VIL or VIH but must be valid before Read or Write. *6: Output of upper and lower byte data is either Valid or High-Z depending on the level of LB and UB input. Mode CE2 CE 1C L KA D V WE OE LB UB A20 to A0 DQ7 to DQ0 DQ15 to DQ8 WAIT Standby (Deselect) H H X X X X X X X High-Z High-Z High-Z Output Disable*1 HL X *3 H H X X *5 High-Z High-Z High-Z Output Disable (No Read) X* 3 HL H H Valid High-Z High-Z High-Z Read (Upper Byte) X *3 H L Valid High-Z Output Valid High-Z Read (Lower Byte) X *3 L H Valid Output Valid High-Z High-Z Read (Word) X *3 L L Valid Output Valid Output Valid High-Z Page Read X *3 L/H L/H Valid *6 *6 High-Z No Write X *3 LH * H H Valid Invalid Invalid High-Z Write (Upper Byte) X *3 H L Valid Invalid Input Valid High-Z Write (Lower Byte) X *3 L H Valid Input Valid Invalid High-Z Write (Word) X *3 L L Valid Input Valid Input Valid High-Z Power Down*

2 L X X X X X X X X High-Z High-Z High-Z

Synchronous Operation (Burst Mode) Note : L = VIL, H = VIH, X can be either VIL or VIH, = valid edge, = rising edge of Low pulse, High-Z = High impedance *1: Should not be kept this logic condition longer than 8 µs. *2: Power Down mode can be entered from Standby state and all output are in High-Z state. Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details. *3: CLK must be started and stable prior to memory access. *4: Can be either VIL or VIH except for the case the both of OE and WE are VIL. It is prohibited to bring the both of OE and WE to VIL. *5: When device is operating in "WE Single Clock Pulse Control" mode, WE is a "don't care" once write operation is determined by WE Low Pulse at the beginning of write access together with address latching. Burst write suspend feature is not supported in "WE Single Clock Pulse Control" mode. *6: Can be either VIL or VIH but must be valid before Read or Write is determined. And once LB and UB input levels are determined, they must not be changed until the end of burst. *7: Once valid address is determined, input address must not be changed during ADV = L. *8: If OE = L, output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L, input is Invalid. If OE = WE = H, output is High-Z. *9: Outputs is either Valid or High-Z depending on the level of LB and UB input. *10: Input is either Valid or Invalid depending on the level of LB and UB input. *11: Output is either High-Z or Invalid depending on the level of OE and WE input. *12: Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in "■FUNCTIONAL DESCRIPTION" for the details. *13: WAIT output is driven in High level during burst write operation. Mode CE2 CE 1C L KA D V WE OE LB UB A20 to A0 DQ7 to DQ0 DQ15 to DQ8 WAIT Standby(Deselect) H H X X X X X X X High-Z High-Z High-Z Start Address Latch*1 L *3 X*4 X*4 X*6 X*6 Valid*7 High-Z*8 High-Z*8 High-Z*11 Advance Burst Read to Next Address*1 *3 H H L X Output Valid*9 Output Valid*9 Output Valid Burst Read Suspend* 1 *3 H High-Z High-Z High* 12 Advance Burst Write to Next Address* 1 *3 L*5 H Input Valid*10 Input Valid*10 High*13 Burst Write Suspend*1 *3 H*5 Input Invalid Input Invalid High*12 Terminate Burst Read X H X High-Z High-Z High-Z Terminate Burst Write X X H High-Z High-Z High-Z Power Down*

■ STATE DIAGRAM Note : Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the "■FUNCTIONAL DESCRIPTION", "2. AC Characteristics" in "■ELECTRICAL CHARACTERISTICS", and "■TIMING DIA- GRAMS" for details. CE2 = H CE2 = L @M = 1 @M = 0 CE2 = H CE2 = L @RP = 1CE2 Low Pulse @RP = 0 Power Down Power Up Pause Time Standby CR Set Standby Power Down Asynchronous Operation (Page Mode) Common State

Initial/Standby State Synchronous Operation (Burst Mode) CE2 = CE1 = H CE1 = L CE1 = H CE1 = L & OE = L CE1 = HCE1 = H CE1 = L & WE = L WE = H WE = L OE = H OE = L Asynchronous Operation Standby Write Read Output Disable Byte Control @OE = L Byte Control Address Change or Byte Control CE2 = CE1 = H CE1 = H CE1 = HCE1 = H WE = H WE = L OE = H OE = L CE1 = H CE1 = L, ADV Low Pulse, & WE = L CE1 = L, ADV Low Pulse, & OE = L Synchronous Operation Standby Write Suspend Read Suspend Write Read ADV Low Pulse (@BL = 8 or 16, and after burst operation is completed) ADV Low Pulse ADV Low Pulse

■ FUNCTIONAL DESCRIPTION This device supports asynchronous read, page read & normal write operations and synchronous burst read and burst write operations for faster memory access and features three kinds of power down modes for power saving as user configurable option.

Power-up It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing" in "■TIMING DIAGRAMS". After Power-up, the device defaults to the asynchronous page read & normal write operation mode with sleep power down feature.
Configuration Register The Configuration Register(CR) is used to configure the type of device function among optional features. Each selection of features is set through CR set sequence after power-up. If CR set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default con- figuration.
CR Set Sequence The CR set requires total 6 read/write operations wi th unique address. Between each read/write operation requires that device being in standby mode. The following table shows the detail sequence. The first cycle is to read from most significant address(MSB). The second and third cycles are to write to MSB. If the second or third cycle is written into the different address, the CR set is cancelled and the data written by the second or third cycle is valid as a normal write operation. It is recommended to write back the data(RDa) read by first cycle to MSB in order to secure the data. The fourth and fifth cycles are to write to MSB. The data of fourth and fifth cycle is a "don't-care". If the fourth or fifth cycle is written into different address, the CR set is also cancelled, but write data may not be written as normal write operation. The last cycle is to read from specific address key for mode selection. And read data(RDb) is invalid. Once this CR set sequence is performed from an initial CR set to the other new CR set, the written data stored in the memory cell array may be lost. So, CR set sequence should be performed prior to the regular read/write operation if necessary to change from the default configuration. Cycle # Operation Address Data #1 Read 1FFFFFh (MSB) Read Data (RDa) #2 Write 1FFFFFh RDa #3 Write 1FFFFFh RDa #4 Write 1FFFFFh X #5 Write 1FFFFFh X #6 Read Address Key Read Data (RDb)

Address Key The address key has the following format. *1 : Sleep and Partial power down mode are effective when RP = 1. (Continued) Address Pin Register Name Function Key Description Note A20, A19 PS Partial Size 00 8 M-bit Partial *1 01 4 M-bit Partial *1

10 Reserved for future use *2

11 Sleep [Default]

A18 to A16 BL Burst Length 000,

001 Reserved for future use *2

Reserved for future use *2

111 Continuous

15 MM o d e

0 Synchronous Mode (Burst Read / Write) *3

1 Asynchronous Mode [Default] (Page Read / Normal Write) *4

A 14 to A12 RL Read Latency

000 Reserved for future use *2

110,

111 Reserved for future use *2

A 11 ⎯⎯ 1 Unused bits must be 1 *5 A10 SW Single Write

0 Burst Read & Burst Write

1 Reserved for future use *2

0 Reserved for future use *2

1 Rising Clock Edge

0 Reset to Page mode *6

1 Remain the previous mode [Default] *1

0 WE Single Clock Pulse Control without Write Suspend

1W E Level Control with Write Suspend Function A6 DS Driver Size 0S t r o n g

1 Center [Default]

A 5 to A0 ⎯⎯ 1 Unused bits must be 1 *5

(Continued) *2 : It is prohibited to apply this key. *3 : If M = 0, all the registers must be set with appropriate Key inputs at the same time. *4 : If M = 1, PS and DS must be set with appropriate Key inputs at the same time. Except for PS and DS, all the other key inputs must be "1". *5 : A11 and A5 to A0 must be all "1" in any cases. *6 : In case of RP = 0, CE2 brought to Low reset the device to the asynchronous standby state regardless PS set value and so Sleep and Partial power down modes are not available.

Power Down The Power Down is a low power idle state controlled by CE2. CE2 Low drives the device in power down mode and maintains the low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down mode. This device has three power down modes, Sleep, 4 M-bit Partial, and 8 M-bit Partial. The selection of power down mode is set through CR set sequence. Each mode has following data retention features. The default state after power-up is Sleep and it is t he lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to perform CR set sequence to set to Sleep mode after power-up in case of the asynchronous operation. When RP = 0, CE2 brought to Low reset the device to the asynchronous standby state regardless PS set value.
Burst Read/Write Operation Synchronous burst read/write operation provides faster memory access that synchronized to the microcontroller or system bus frequency. Configuration Register(CR) Set is required to perform a burst read & write operation after power-up. Once CR set sequence is performed to select the synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through CR set sequence together with the operation mode. In order to perform a synchronous burst read & write operation, it is required to control new signals, CLK, ADV and WAIT that Low Power SRAMs do not have. (Continued) Mode Data Retention Size Retention Address Sleep [default] No N/A

4 M-bit Partial 4 M bits 000000h to 03FFFFh

8 M-bit Partial 8 M bits 000000h to 07FFFFh

Burst Read Operation Valid addressAddress

(Continued)

CLK Input Function The CLK is input signal to synchronize the memory to the microcontroller or system bus frequency during synchronous burst read & write operation. The CLK inpu t increments the device internal address counter and the valid edge of CLK is referred for latency counts from address latch, burst write data latch, and burst read data output. During synchronous oper ation mode, CLK input must be s upplied except for standby state and power down state. CLK is a “don't care” during asynchronous operation.
ADV Input Function The ADV is input signal to latch a valid address. It is applicable to synchronous operation as well as asynchronous operation. ADV input is active during CE1 = L and CE1 = H disables ADV input. All addresses are determined on the rising edge of ADV. During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to High after a valid address latch, it is inhibited to bring ADV Low until the end of burst or until the burst operation is terminated. ADV Low pulse is mandatory for the synchronous bu rst read/write operation mode to latch the valid address input. During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during asynchronous operation and it is not necessary to control ADV to High. RL-1 BL High High-Z High-Z CLK ADV CE1 OE WE WAIT DQ D1 D2 DBL
Burst Write Operation Valid addressAddress

WAIT Output Function The WAIT is output signal to indicate the data bus status when the device is operating in the synchronous burst mode. During burst read operation, WAIT output is enabled after specified time duration from OE = L or CE 1 = L whichever occurs last. WAIT output Low indicates data output at ne xt clock cycle is invalid, and WAIT output becomes High one clock cycle prior to a valid data output. During OE read suspend, WAIT output does not indicate the data bus status but carries the same level from previous clock cycle (kept High) except for read suspend on the final data output. If final read data output is suspended, WAIT output becomes high impedance after specified time duration from OE = H. During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L or CE1 = L whichever occurs last and kept Hi gh for entire write cycles including WE write suspend. The actual write data latching starts on the appropriate clock edge with respect to Valid Clock Edge, Read Latency, and Burst Length. During WE Write suspend, WAIT output does not indicate the data bus status but carries the same level from previous clock cycle (kept High) except for write suspend on the final data input. If final write data input is suspended, WAIT output becomes high impedance after specified time duration from WE = H. This device does not incur additional delay against crossing device-row boundary or internal refresh operation. Therefore, the burst operation is always started after the fixed latency with respect to Read Latency. And there is no waiting cycle asserted in the middle of burst operation except for burst suspend by OE brought to High or WE brought to High. Thus, once WAIT output is enabled and brought to High, WAIT output keep High level until the end of burst or until the burst operation is terminated. When the device is operating in the asynchronous mode, WAIT output is always in High Impedance.
Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through CR set sequence after power-up. Once specific RL is set through CR set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started after the fixed latency with respect to Read Latency set in CR.

RL = 3 RL = 4 RL = 5 12 34 5 6 CLK ADV CE1 WAIT DQ WAIT DQ WAIT DQ WAIT DQ WAIT DQ WAIT DQ Q1 Q2 Q3 Q4 Q5 D1 D3 D4 D5 D6 Q3 Q4 D1 D4 D5 Q2 Q3 D2D1 D3 D4 D3D2 Q1 Q2 High-Z High-Z High-Z High-Z High-Z High-Z WAIT DQ WAIT DQ Q1 Q2 D1 D2 D3 High-Z High-Z RL = 6 Valid address [Output] [Input] OE or WE Address [Output] [Input] [Output] [Input] [Output] [Input]

Address Latch by ADV The ADV latches valid address presence on address inputs. During synchr onous burst read/write operation mode, all the addresses are determined on the rising edge of ADV when CE1 = L. The specified minimum value of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied for appropriate RL counts. Valid address must be determined with specified setup time against either the falling edge of ADV or falling edge of CE1 whichever comes late. And the determined valid address must not be changed during ADV = L period.
Burst Length Burst Length is the number of word to be read or written during synchronous burst read/write operation as the result of a single address latch cycle. It can be set on 8,16 words boundary or co ntinuous for entire address through CR set sequence. The burst type is sequential that is incremental decoding scheme within a boundary address. Starting from the initial address being latched, the device internal address counter assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (= 0). After completing read data output or write data latch for the set burst length, operation automatically ended except for continuous burst length. When continuous burst length is set, read/write is endless unless it is termi- nated by the rising edge of CE1.
Write Control The device has two types of WE signal control method, "WE Level Control" and "WE Single Clock Pulse Control", for the synchronous burst write operation. It is configured through CR set sequence. 0 12 34 5 6 RL = 5 tWLD tCKWH tCLTH tWLTH High-Z High-Z CLK ADV CE1 WAIT DQ WAIT DQ WE WE D1 D2 D3 D4 D1 D2 tWSCK tWLTH D4D3 Valid addressAddress WE Level Control WE Single Clock Pulse Control [Input] [Input]

Burst Read Suspend Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High from Low suspends the burst read operation. Once OE is brought to High with the specified setup time against clock where the data being suspended, the device internal counter is suspended, and the data output becomes high impedance after specified time duration. It is inhibited to suspend the first data output at the beginning of burst read. OE brought to Low from High resumes the burst read operation. Once OE is brought to Low, data output becomes valid after specified time duration, and internal address counter is reactivated. The last data output being sus- pended as the result of OE = H and first data output as the result of OE = L are from the same address. In order to guarantee to output last data before suspension and first data after resumption, the specified minimum value of OE hold time and setup time against clock edge must be satisfied respectively.
Burst Write Suspend Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High from Low suspends the burst write operation. Once WE is brought to High with the specified setup time against clock where the data being suspended, the device intern al counter is suspended, dat a input is ignored. It is inhibited to suspend the first data input at the beginning of burst write. WE brought to Low from High resumes the burst write operation. Once WE is brought to Low, data input becomes valid after specified time duration, a nd internal address counter is reactiva ted. The write address of the cycle where data being suspended and the first write address as the result of WE = L are the same address. In order to guarantee to latch the last data input befor e suspension and first data input after resumption, the specified minimum value of WE hold time and setup time against clock edge must be satisfied respectively. Burst write suspend function is available when the device is operating in WE level controlled burst write only. CLK OE WAIT DQ tCKOH tOSCK tOSCKtCKOH tAC tAC tAC tOLZ tCKQX tCKQXtCKQXtCKTV tAC tOHZ Q1 Q2 Q3 Q4Q2 CLK WE WAIT DQ tCKWH tWSCK tWSCKtCKWH tDHCK tDSCK D1 D3 D4D2D2 tDSCK tDSCK tDSCK tDHCK tDHCK High

Burst Read Termination Burst read operation can be terminated by CE 1 brought to High. If BL is set on Continuous, the burst read operation is continued endlessly unless terminated by CE1 = H. It is inhibited to terminate the burst read before first data output is completed. In order to guarantee last data output, the specified minimum value of CE 1 = L hold time from the clock edge must be satisfied. After termination, the specified minimum recovery time is required to start a new access.
Burst Write Termination Burst write operation can be terminated by CE 1 brought to High. If BL is set on Continuous, the burst write operation is continued endlessly unless terminated by CE1 = H. It is inhibited to terminate the burst write before first data input is completed. In order to guarantee last data input being latched, the specified minimum values of CE1 = L hold time from the clock edge must be satisfied. After termination, the specified minimum recovery time is required to start a new access. tTRB CLK ADV CE1 WAIT DQ OE tCKCLH tCHZ tCKOH tOHZ tCHTZ tAC tCKQX High-Z Q2Q1 Address Valid address tTRB CLK ADV CE1 WAIT DQ WE tCKCLH tCHCK tCKWH tCHTZtDSCK High-Z D2D1 tDSCK tDHCK tDHCK Address Valid address

■ ABSOLUTE MAXIMUM RATINGS * : All voltages are referenced to VSS = 0 V. WARNING: Semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS *1 : All voltages are referenced to VSS = 0 V. *2 : Maximum DC voltage on input and I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to VDD + 1.0 V for periods of up to 5 ns. *3 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to -1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. ■ PACKAGE PIN CAPACITANCE (f = 1 MHz, TA = + 25 °C) Parameter Symbol Rating Unit Min Max Voltage of VDD Supply Relative to VSS *V DD − 0.5 + 2.6 V Voltage at Any Pin Relative to VSS *V IN, VOUT − 0.5 + 2.6 V Short Circuit Output Current * I OUT − 50 + 50 mA Storage Temperature T STG − 55 + 125 °C Parameter Symbol Value Unit Min Max Power Supply Voltage*1 VDD 1.7 1.95 V VSS 00 V High Level Input Voltage*1, *2 VIH VDD × 0.8 V DD + 0.2 V Low Level Input Voltage*1, *3 VIL − 0.3 V DD × 0.2 V Ambient Temperature T A − 10 + 70 °C Parameter Symbol Test conditions Value Unit Min Typ Max Address Input Capacitance C IN1 VIN = 0 V ⎯⎯ 5p F Control Input Capacitance C IN2 VIN = 0 V ⎯⎯ 5p F Data Input/Output Capacitance C I/O VIO = 0 V ⎯⎯ 8p F

■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (At recommended operating conditions unless otherwise noted) Notes : • All voltages are referenced to VSS = 0 V.

IDD depends on the output termination, load conditions, and AC characteristics.
After power on, initialization following Power-up timing is required. DC characteristics are guaranteed after the initialization.
IDDPS, IDDP4, IDDP8, IDDS1, and IDDS2çmight be higher for up to 200ms after Power-up or power down/standby mode entry. Parameter Symbol Test Conditions Value Unit Min Max Input Leakage Current I LI VSS ≤ VIN ≤ VDD − 1.0 + 1.0 µA Output Leakage Current I LO

0 V ≤ VOUT ≤ VDD,

Output Disable − 1.0 + 1.0 µA Output High Voltage Level V OH VDD = VDD (Min), IOH = − 0.5 mA 1.4 ⎯ V Output Low Voltage Level V OL IOL = 1 mA ⎯ 0.4 V VDD Power Down Current IDDPS VDD = VDD (Max), VIN = VIH or VIL, CE2 ≤ 0.2 V Sleep ⎯ 10 µA IDDP4 4 M-bit Partial ⎯ 45 µA IDDP8 8 M-bit Partial ⎯ 55 µA VDD Standby Current IDDS VDD = VDD (Max), VIN (including CLK) = VIH or VIL, CE1 = CE2 = VIH ⎯ 1.5 mA IDDS1 VDD = VDD (Max), VIN (including CLK) ≤ 0.2 V or VIN (including CLK) ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V ⎯ 100 µA IDDS2 VDD = VDD (Max), tCK = Min VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V RL = 6 ⎯ 600 µA RL = 3, 4, 5 ⎯ 200 µA VDD Active Current IDDA1 VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC/tWC = Min ⎯ 30 mA IDDA2 tRC/tWC = 1 µs ⎯ 3m A VDD Page Read Current I DDA3 VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA, tPRC = Min ⎯ 10 mA VDD Burst Access Current I DDA4 VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, tCK = tCK (Min), BL = Continuous, IOUT = 0 mA ⎯ 20 mA

AC Characteristics (1) Asynchronous Read Operation (Page Mode) (At recommended operating conditions unless otherwise noted) *1 : Maximum value is applicable if CE1 is kept at Low without change of address input of A20 to A3. *2 : Address should not be changed within minimum tRC. *3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *4 : The output load 5 pF without any other load. *5 : Applicable to A20 to A3 when CE1 is kept at Low. *6 : Applicable only to A2, A1 and A0 when CE1 is kept at Low for the page address access. (Continued) Parameter Symbol Value Unit Notes Min Max Read Cycle Time t RC 70 1000 ns *1, *2 CE1 Access Time t CE ⎯ 70 ns *3 OE Access Time t OE ⎯ 40 ns *3 Address Access Time t AA ⎯ 70 ns *3, *5 ADV Access Time t AV ⎯ 70 ns *3 LB, UB Access Time t BA ⎯ 30 ns *3 Page Address Access Time t PAA ⎯ 20 ns *3, *6 Page Read Cycle Time t PRC 20 1000 ns *1, *6, *7 Output Data Hold Time t OH 3 ⎯ ns *3 CE1 Low to Output Low-Z t CLZ 5 ⎯ ns *4 OE Low to Output Low-Z t OLZ 10 ⎯ ns *4 LB, UB Low to Output Low-Z t BLZ 0 ⎯ ns *4 CE1 High to Output High-Z t CHZ ⎯ 12 ns *3 OE High to Output High-Z t OHZ ⎯ 12 ns *3 LB, UB High to Output High-Z t BHZ ⎯ 12 ns *3 Address Setup Time to CE1 Low t ASC − 5 ⎯ ns Address Setup Time to OE Low t ASO 0 ⎯ ns ADV Low Pulse Width t VPL 10 ⎯ ns *8 ADV High Pulse Width t VPH 10 ⎯ ns *8 Address Setup Time to ADV High t ASV 10 ⎯ ns *9 Address Hold Time from ADV High t AHV 5 ⎯ ns *9 Address Invalid Time t AX ⎯ 10 ns *5, *10 Address Hold Time from CE1 High t CHAH − 5 ⎯ ns *11 Address Hold Time from OE High t OHAH − 5 ⎯ ns WE High to OE Low Time for Read t WHOL 10 1000 ns *12 CE1 High Pulse Width t CP 10 ⎯ ns

(Continued) *7 : In case Page Read Cycle is continued with keeping CE1 stays Low, CE1 must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. *8 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. *9 : The sum of actual tASV and tAHV must be equal or greater than 10 ns. *10 : Applicable to address access when at least two of address inputs are switched from previous state. *11 : tRC (Min) and tPRC (Min) must be satisfied. *12 : If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting actual value from specified minimum value.

(2) Asynchronous Write Operation (At recommended operating conditions unless otherwise noted) *1 : Maximum value is applicable if CE 1 is kept at Low without any address change. *2 : Minimum value must be equal or great er than the sum of write pulse width (tCW, tWP or tBW) and write recovery time (tWR). *3 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last. *4 : t VPL is specified from the falling edge of either CE1 or ADV whichever comes late. *5 : The sum of actual t ASV and tAHV must be equal or greater than 10 ns. *6 : Applicable for byte mask only. Byte mask setup time is defined from the High to Low transition of CE1 or WE whichever occurs last. *7 : Applicable for byte mask only. Byte mask hold ti me is defined from the Low to High transition of CE1 or WE whichever occurs first. *8 : Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first. *9 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns after CE1 is brought to Low. *10 : If OE is Low after a new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before the new address is valid. Parameter Symbol Value Unit Notes Min Max Write Cycle Time t WC 70 1000 ns *1, *2 Address Setup Time t AS 0 ⎯ ns *3 ADV Low Pulse Width t VPL 10 ⎯ ns *4 ADV High Pulse Width t VPH 10 ⎯ ns *4 Address Setup Time to ADV High t ASV 10 ⎯ ns *5 Address Hold Time from ADV High t AHV 5 ⎯ ns *5 CE1 Write Pulse Width t CW 45 ⎯ ns *3 WE Write Pulse Width t WP 45 ⎯ ns *3 LB, UB Write Pulse Width t BW 45 ⎯ ns *3 LB, UB Byte Mask Setup Time t BS −5 ⎯ ns *6 LB, UB Byte Mask Hold Time t BH −5 ⎯ ns *7 Write Recovery Time t WR 0 ⎯ ns *8 CE1 High Pulse Width t CP 10 ⎯ ns WE High Pulse Width t WHP 10 1000 ns LB, UB High Pulse Width t BHP 10 1000 ns Data Setup Time t DS 15 ⎯ ns Data Hold Time t DH 0 ⎯ ns OE High to CE1 Low Setup Time for Write t OHCL −5 ⎯ ns *9 OE High to Address Setup Time for Write t OES 0 ⎯ ns *10 LB and UB Write Pulse Overlap t BWO 40 ⎯ ns

(3) Synchronous Operation - Clock Input (Burst Mode) (At recommended operating conditions unless otherwise noted) *1: Clock period is defined between valid clock edges. *2: Clock transition time is defined between VIH (Min) and VIL (Max). (4) Synchronous Operation - Address Latch (Burst Mode) (At recommended operating conditions unless otherwise noted) *1: tASCL is applicable if CE1 is brought to Low after ADV is brought to Low. *2: tASVL is applicable if ADV is brought to Low after CE1 is brought to Low. *3: tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and tASVL (or tASCL) must be equal or greater than the specified minimum value of tVPL. *4: Applicable to the 1st valid clock edge. Parameter Symbol Value Unit Note Min Max Clock Period RL = 6 tCK 12 ⎯ ns *1 RL = 5 15 ⎯ ns *1 RL = 4 18 ⎯ ns *1 RL = 3 30 ⎯ ns *1 Clock High Pulse Width t CKH 3.5 ⎯ ns Clock Low Pulse Width t CKL 3.5 ⎯ ns Clock Transition Time t CKT ⎯ 1.5 ns *2 Parameter Symbol Value Unit Notes Min Max Address Setup Time to CE1 Low t ASCL − 3 ⎯ ns *1, *3 Address Setup Time to ADV Low t ASVL − 3 ⎯ ns *2, *3 Address Hold Time from ADV High t AHV 5 ⎯ ns ADV Low Pulse Width t VPL 8 ⎯ ns *3 ADV Low Setup Time to CLK RL = 6 tVSCK 4 ⎯ ns *4 RL = 3, 4, 5 5 ⎯ ns *4 CE1 Low Setup Time to CLK RL = 6 tCLCK 4 ⎯ ns *4 RL = 3, 4, 5 5 ⎯ ns *4 ADV Low Hold Time from CLK t CKVH 1 ⎯ ns *4

(5) Synchronous Read Operation (Burst Mode) (At recommended operating conditions unless otherwise noted) *1: The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *2: WAIT drives High at the beginning depending on OE falling edge timing. *3: tCKTV is guaranteed after tOLTL (Max) from OE falling edge and tOSCK must be satisfied. *4: The output load 5 pF without any other load. *5: Once LB and UB are determined, they must not be changed until the end of burst read. *6: Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever occurs late. Parameter Symbol Value Unit Notes Min Max Burst Read Cycle Time t RCB ⎯ 8000 ns CLK Access Time RL = 5, 6 tAC ⎯ 8n s * 1 RL = 3, 4 ⎯ 10 ns *1 Output Hold Time from CLK t CKQX 2 ⎯ ns *1 CE1 Low to WAIT Low t CLTL 51 5 n s * 1 OE Low to WAIT Low t OLTL 51 5 n s * 1 , * 2 CLK to WAIT Valid Time t CKTV ⎯ 8n s * 1 , * 3 WAIT Valid Hold Time from CLK t CKTX 2 ⎯ ns *1 CE1 Low to Output Low-Z t CLZ 5 ⎯ ns *4 OE Low to Output Low-Z t OLZ 10 ⎯ ns *4 LB, UB Low to Output Low-Z t BLZ 0 ⎯ ns *4 CE1 High to Output High-Z t CHZ ⎯ 12 ns *1 OE High to Output High-Z t OHZ ⎯ 12 ns *1 LB, UB High to Output High-Z t BHZ ⎯ 12 ns *1 CE1 High to WAIT High-Z t CHTZ ⎯ 12 ns *1 OE High to WAIT High-Z t OHTZ ⎯ 12 ns *1 OE Low Setup Time to 1st Data-output t OLQ 30 ⎯ ns LB, UB Setup Time to 1st Data-output t BLQ 30 ⎯ ns *5 OE Setup Time to CLK t OSCK 4 ⎯ ns OE Hold Time from CLK t CKOH 2 ⎯ ns Burst End CE1 Low Hold Time from CLK t CKCLH 2 ⎯ ns Burst End LB, UB Hold Time from CLK t CKBH 2 ⎯ ns Burst Terminate Recovery Time BL = 8, 16 tTRB 30 ⎯ ns *6 BL = Continuous 70 ⎯ ns *6

(6) Synchronous Write Operation (Burst Mode) (At recommended operating conditions unless otherwise noted) *1: Defined from the valid input edge to the High to Low transition of either ADV, CE1, or WE, whichever occurs last. And once LB, UB are determined, LB, UB must not be changed until the end of burst write. *2: The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *3: Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever occurs late for the next access. Parameter Symbol Value Unit Note Min Max Burst Write Cycle Time t WCB ⎯ 8000 ns Data Setup Time to CLK t DSCK 4 ⎯ ns Data Hold Time from CLK t DHCK 2 ⎯ ns WE Low Setup Time to 1st Data Input t WLD 30 ⎯ ns LB, UB Setup Time for Write t BS −5 ⎯ ns *1 WE Setup Time to CLK t WSCK 4 ⎯ ns WE Hold Time from CLK t CKWH 2 ⎯ ns CE1 Low to WAIT High t CLTH 51 5 n s * 2 WE Low to WAIT High t WLTH 51 5 n s * 2 CE1 High to WAIT High-Z t CHTZ ⎯ 12 ns *2 Burst End CE1 Low Hold Time from CLK t CKCLH 2 ⎯ ns Burst End CE1 High Setup Time to next CLK t CHCK 4 ⎯ ns Burst End LB, UB Hold Time from CLK t CKBH 2 ⎯ ns Burst Terminate Recovery Time BL = 8, 16 tTRB 30 ⎯ ns *3 BL = Continuous 70 ⎯ ns *3

(7) Power Down Parameters (At recommended operating conditions unless otherwise noted) *1 : Applicable when RP = 0 (Reset to Page mode) . *2 : Applicable also to power-up. *3 : Applicable when Partial mode is set. (8) Other Timing Parameters (At recommended operating conditions unless otherwise noted) *1 : Some data might be written into any address location if tCHWX (Min) is not satisfied. *2 : Except for clock input transition time. *3 : The Input Transition Time (tT) at AC testing is 5 ns for Asynchronous operation and 3 ns for Synchronous operation respectively. If actual tT is longer than 5 ns or 3 ns specified as AC test condition, it may violate AC specification of some timing parameters. Refer to " (9) AC Test Conditions". Parameter Symbol Value Unit Note Min Max CE2 Low Setup Time for Power Down Entry t CSP 10 ⎯ ns CE2 Low Hold Time after Power Down Entry t C2LP 70 ⎯ ns CE2 Low Hold Time for Reset to Asynchronous Mode t C2LPR 70 ⎯ ns *1 CE1 High Hold Time following CE2 High after Power Down Exit [Sleep mode only] tCHH 300 ⎯µ s* 2 CE1 High Hold Time following CE2 High after Power Down Exit [not in Sleep mode] tCHHP 70 ⎯ ns *3 CE1 High Setup Time following CE2 High after Power Down Exit tCHS 0 ⎯ ns *2 Parameter Symbol Value Unit Notes Min Max CE1 High to OE Invalid Time for Standby Entry t CHOX 10 ⎯ ns CE1 High to WE Invalid Time for Standby Entry t CHWX 10 ⎯ ns *1 CE2 Low Hold Time after Power-up t C2LH 50 ⎯µ s CE1 High Hold Time following CE2 High after Power-up t CHH 300 ⎯µ s Input Transition Time (except for CLK) t T 12 5 n s * 2 , * 3

(9) AC Test Conditions Description Symbol Test Setup Value Unit Note Input High Level V IH ⎯ VDD × 0.8 V Input Low Level V IL ⎯ VDD × 0.2 V Input Timing Measurement Level V REF ⎯ VDD × 0.5 V Input Transition Time Async. tT Between VIL and VIH 5n s Sync. 3 ns VDD VSS 0.1 µF 50 pF VDD 0.5 V OutputDevice under Test

AC MEASUREMENT OUTPUT LOAD CIRCUIT

■ TIMING DIAGRAMS (1) Asynchronous Read Timing #1-1 (Basic Timing) tRC tCE tASC tCHAH tCP tCHZ tOHZ tOE tBA tBLZ tOLZ tBHZ tOH tASC CE1 OE DQ LB, UB ADV Low Valid Data Output (Output) Address Address Valid Note : This timing diagram assumes CE2 = H and WE = H.

(2) Asynchronous Read Timing #1-2 (Basic Timing) tRC tCE tASC tCP tCHZ tOHZ tOE tBA tBLZ tOLZ tBHZ tOH tASC CE1 OE DQ LB, UB ADV tASV tVPH tVPL tAHV tAV Note : This timing diagram assumes CE2 = H and WE = H. Valid Data Output (Output) Address Address Valid

(3) Asynchronous Read Timing #2 (OE Control & Address Access) Note : This timing diagram assumes CE2 = H, ADV = L and WE = H. CE1 OE DQ tRC tRC tASO tOE tOHZ tOLZ tOH tOH tOHAHtAA tAA tAX LB, UB Low Valid Data Output(Output) Address Valid Address ValidAddress Valid Data Output

(4) Asynchronous Read Timing #3 (LB, UB Byte Control Access) tRC tAXtAX tAA Low tBAtBA tBA tBLZ tOH tBLZ tOH tOHtBLZ tBHZ tBHZ tBHZ CE1, OE LB UB Note : This timing diagram assumes CE2 = H, ADV = L and WE = H. Address Valid Data Output Address Valid Valid Data Output Valid Data Output DQ15 to DQ8 (Output) DQ7 to DQ0 (Output)

(5) Asynchronous Read Timing #4 (Page Address Access after CE1 Control Access) tRC tRC tPRC tPRC tPRC tPAA tPAA tPAA tCHAH tOHtOHtOHtOH tCLZ tASC tCHZtCE CE1 OE DQ LB, UB ADV Note : This timing diagram assumes CE2 = H and WE = H. Address Valid (Output) Valid Data Output (Normal Access) Valid Data Output (Page Access) Address Valid Address Vali d Address Valid Address Valid Address (A20 to A3) Address (A2 to A0)

(6) Asynchronous Read Timing #5 (Random and Page Address Access) tRCtRC tRC tAA LOW tPAA tPRC tASO tOE tBA tOLZ tBLZ tOH tOH tOH tOH tAA tRC tPAA tPRC tAXtAX CE1 OE LB, UB DQ Notes : • This timing diagram assumes CE2 = H, ADV = L and WE = H.

Either or both LB and UB must be Low when both CE1 and OE are Low. Address Valid (Output) Valid Data Output (Normal Access) Valid Data Output (Page Access) Address Valid Address ValidAddress Valid Address Valid Address Valid Address (A20 to A3) Address (A2 to A0)

(7) Asynchronous Write Timing #1-1 (Basic Timing) CE1 WE LB, UB OE DQ tWC tWR tWR tWR tAS tAS tAS tCW tWP tBW tAS tAS tOHCL tAS tDS tDH ADV Low tCP tWHP tBHP Note : This timing diagram assumes CE2 = H. (Input) Address Address Valid Valid Data Input

(8) Asynchronous Write Timing #1-2 (Basic Timing) CE1 WE LB, UB OE DQ tWC tWR tWR tWR tAS tAS tAS tCW tWP tBW tAS tAS tOHCL tAS tDS tDH ADV tCP tWHP tBHP tAHVtASV tVPH tVPL Note : This timing diagram assumes CE2 = H. (Input) Address Address Valid Valid Data Input

(9) Asynchronous Write Timing #2 (WE Control) CE1 WE LB, UB OE DQ tWC tWC tWR tAStWP tWRtWPtAS tOHAH tOES tOHZ tDS tDH tDS tDH Low tWHP Note : This timing diagram assumes CE2 = H and ADV = L. (Input) Address Address Valid Valid Data Input Address Valid Valid Data Input

(10) Asynchronous Write Timing #3-1 (WE, LB, UB Byte Write Control) CE1 WE UB LB tWC tWC tAStWP tWR tWPtAS tDS tDH tDS tDH Low tWR tBS tBH tBH tBS tWHP Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. DQ15 to DQ8 (Input) Address Address Valid Valid Data Input Address Valid DQ7 to DQ0 (Input) Valid Data Input

(11) Asynchronous Write Timing #3-2 (WE, LB, UB Byte Write Control) CE1 WE UB LB tWC tWC tWR tAS tBW tWR tBW tDS tDH tDS tDH Low tAS tBS tBH tBHtBS tWHP Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. Address Address Valid Valid Data Input Address Valid Valid Data Input DQ15 to DQ8 (Input) DQ7 to DQ0 (Input)

(12) Asynchronous Write Timing #3-3 (WE, LB, UB Byte Write Control) CE1 WE UB LB tWC tWC tWR tAS tBW tWRtBW tAS tDS tDH tDS tDH Low tBStBS tBH tBS tBH tWHP Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. Address Address Valid Valid Data Input Address Valid Valid Data Input DQ15 to DQ8 (Input) DQ7 to DQ0 (Input)

(13) Asynchronous Write Timing #3-4 (WE, LB, UB Byte Write Control) CE1 WE UB LB tWC tWC tWRtBW tBWO tBWO tAS tWRtBWtAS tWRtBWtAS tWRtBWtAS tDS tDH tDS tDH tDS tDH tDS tDH Low tBHP tBHP Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. Address Address Valid Valid Data Input Address Valid Valid Data Input Valid Data InputValid Data Input DQ7 to DQ0 (Input) DQ15 to DQ8 (Input)

(14) Asynchronous Read/Write Timing #1-1 (CE1 Control) CE1 WE LB, UB OE DQ tCHAH tAS tCP tOHCL tCHZ tOH tWC tCW tWR tASC tCP tDS tDH tRC tCE tCHAH tCLZ tOH Notes : • This timing diagram assumes CE2 = H and ADV = L

Write address is valid from either CE1 or WE of last falling edge. Address Write Address Write Data Input Read Address Read Data Output Read Data Output

(15) Asynchronous Read/Write Timing #1-2 (CE1, WE, OE Control) CE1 WE LB, UB OE DQ tCHAH tAS tCP tOHCL tCHZ tOH tWC tWP tWR tASC tCP tOE tDS tDH tRC tCE tCHAH tOLZ tOH Notes : • This timing diagram assumes CE2 = H and ADV = L.

OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. Write Address Write Data Input Read Address Read Data Output Read Data Output Address

(16) Asynchronous Read/Write Timing #2 (OE, WE Control) CE1 WE LB, UB OE DQ tOHAH tWRtAS tOES tOHZ tOH tWC tWP tOE tOHZ tDS tDH tRC tAA tOHAH tOLZ tASO tOH Low tWHOL Notes : • This timing diagram assumes CE2 = H and ADV = L.

CE1 can be tied to Low for WE and OE controlled operation. Address Write Address Write Data Input Read Address Read Data Output Read Data Output

(17) Asynchronous Read/Write Timing #3 (OE, WE, LB, UB Control) CE1 WE LB, UB OE DQ tOHAH tAS tWRtOES tBHZ tOH tWC tBW tBA tBHZ tDS tDH tRC tAA tOHAH tBLZ tASO tOH Low tWHOL Notes : • This timing diagram assumes CE2 = H and ADV = L.

CE1 can be tied to Low for WE and OE controlled operation. Address Read Address Write Data Input Write Address Read Data Output Read Data Output

(18) Clock Input Timing (19) Address Latch Timing (Synchronous Mode) CLK tCK tCK tCKH tCKL tCKT tCKT Notes : • Stable clock input must be required during CE1 = L.

tCK is defined between valid clock edges.
tCKT is defined between VIH (Min) and VIL (Max) Low CLK ADV CE1 tASCL tVSCK tCKVH tVPL tCLCK tAHV tASVL tVSCK tCKVH tAHV tVPL Notes : • Case #1 is the timing when CE1 is brought to Low after ADV is brought to Low. Case #2 is the timing when ADV is brought to Low after CE1 is brought to Low.
Address valid time must be equal or greater than the specified minimum value of tCK.
tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. At least one valid clock edge must be input during ADV = L.
tVSCK and tCLCK are applied to the 1st valid clock edge during ADV=L. Case #1 Case #2 Address Valid Valid

(20) Synchronous Read Timing #1 (OE Control) CLK ADV CE1 OE WE LB, UB WAIT DQ RL = 5 tASVL tAHV tCKVH tVPL tASCL tCLCK tVSCK tRCB High tOLQ tBLQ tOLTL tOLZ tCKTV tCKTX tAC tAC tAC tCKQX tCKQX tOHZ tOHTZ tCKBH tCKOH tCP tCLCK tASCL tVPL tCKVHtVSCK tASVL QBLQ1 High-Z High-Z Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. Address Address ValidAddress Valid

(21) Synchronous Read Timing #2 (CE1 Control) CLK ADV CE1 OE WE WAIT DQ RL = 5 tASVL tAHV tCKVH tVPL tASCL tCLCK tVSCK tRCB High tCLTL tCLZ tCKTV tCKTX tAC tAC tAC tCKQX tCKQX tCHZ tCLTL tCKBH tCP tCLCK tVPL QBL tCLZ tCHTZ tCKCLH tCKVH tASVL tVSCK tAHV tASCL LB, UB Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. Address Address ValidAddress Valid

(22) Synchronous Write Timing #1 (WE Level Control) CLK ADV CE1 OE WE WAIT DQ RL = 5 tASVL tAHV tCKVH tVPL tASCL tCLCK tVSCK tWCB tWLTH tDSCK tDHCK tCP tVPL tCKVH tASVL tAHV tASCL High tCLCK tCKWH tCKBH tDSCK tDSCK tDHCK tCHTZ tBS tBS tWLD tVSCK D1 D2 DBL High-Z LB, UB Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. Address Address Valid Address Valid

(23) Synchronous Write Timing #2 (WE Single Clock Pulse Timing) CLK ADV CE1 OE WE WAIT DQ RL = 5 tASVL tAHV tCKVH tVPL tASCL tCLCK tVSCK tWCB tWLTH tDSCK tDHCK tCP tVPL tCKVH tASVL tAHV tASCL High tCLCK tCKCLH tCKBH tDSCK tDSCK tDHCK tCHTZ tBS tVSCK tCKWHtWSCK tWLTH tCKWHtWSCK tBS D1 D2 DBL High-Z LB, UB Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. Address Address Valid Address Valid

(24) Synchronous Read to Write Timing #1 (CE1 Control) RL = 5 tAHV tCKVHtVSCK tASVL tVPL tCLCK tASCL tCP tDSCK tDHCK tDSCK tDHCK tDSCK tDHCK tDSCK tDHCK tBS tCHTZ tCLTHtCHZtAC tCKQXtCKQX tCKBH tCKCLH tCKCLH tCKBH D1 D2 D3 DBLQBL-1 QBL CLK ADV CE1 OE WE WAIT DQ LB,UB tWCB Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. Address Address Valid

(25) Synchronous Write to Read Timing #1(CE1 Control) tAHV tCKVH tASVL tVPL tDSCK tDHCK tDSCK tDHCK CLK ADV CE1 OE WE WAIT DQ LB,UB RL = 5 tCKCLH tCP tCHTZ tCLTL tAC tACtCKTX tCKTV tCKQX tCKQXtCLZ tCLCK High-Z DBL-1 DBL Q1 Q2 tCKBH tVSCK tASCL Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. Address Address Valid

(26) Power-up Timing #1 (27) Power-up Timing #2 CE1 CE2 V DD 0 V VDD (Min) tCHH tCHS tC2LH Note : The tC2LH specifies after VDD reaches specified minimum level. CE1 CE2 V DD 0 V VDD (Min) tCHH Note : The tCHH specifies after VDD reaches specified minimum level and applicable both CE1 and CE2. If transition time of VDD(from 0V to VDD Min) is longer than 50ms, Power-up Timing#1 must be applied.

(28) Power Down Entry and Exit Timing (29) Standby Entry Timing after Read or Write tCHS tCHH (tCHHP)tC2LP (tC2LPR)tCSP High-Z CE1 CE2 DQ Note : This Power Down mode can be also used as a reset timing if “Power-up timing” above could not be satisfied and Power Down program was not performed prior to this reset. Power Down Entry Power Down Mode Power Down Exit tCHOX tCHWX CE1 OE WE Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. Active (Read) Standby Active (Write) Standby

(30) Configuration Register Set Timing #1 (Asynchronous Operation) CE1 WE LB, UB*4 OE DQ*3 tRC tRCtWC tWC tWC tWC tCP tCP tCP tCP tCP tCP*3 (tRC) RDa RDa RDa X X RDb MSB*1 MSB*1 MSB*1 MSB*1 MSB*1Address Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confor m to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, the operation and data are not guaranteed. *3 : After t CP or tRC following Cycle #6, the CR Set is completed and returned to the normal operation. tCP and tRC are applicable to returning to asynchronous mode and to synchronous mode respectively. *4 : Byte read or write is available in addition to Word read or write. At least one byte control signal (LB or UB) need to be Low. Key*2

(31) Configuration Register Set Timing #2 (Synchronous Operation) MSB*1 MSB*1 MSB*1 MSB*1 MSB*1 RL RL-1 tTRB tTRB tTRB tTRB tTRB tTRB tRCB tWCB tWCB tWCB tWCB tRCB RDa RDa RDa X X RDb CLK ADV CE1 OE WE DQ LB,UB* RL-1 RL-1 RL-1 RL *1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confor m to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, the operation and data are not guaranteed. *3 : After t TRB following Cycle #6, the CR Set is completed and returned to the normal operation. *4 : Byte read or write is available in addition to Word read or write. At least one byte control signal (LB or UB) need to be Low. Address Key*2 Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6

■ ORDERING INFORMATION Part Number Package Remarks MB82DBS02163D-70LBGT 71-ball plastic FBGA (BGA-71P-M03)

■ PACKAGE DIMENSION Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 71-ball plastic FBGA Ball pitch 0.80 mm Package width × package length 7.00 × 11.00 mm Lead shape Soldering ball Sealing method Pla stic mold Ball size ∅0.45 mm Mounting height 1.20 mm Max. Weight 0.14 g 71-ball plastic FBGA (BGA-71P-M03) (BGA-71P-M03) C 2003 FUJITSU LIMITED B71003S-c-1-1 7.00±0.10 (.276±.004) INDEX-MARK AREA ABCDEFGHJKLM S 1.09 +0.11 –0.10 +.004 –.004.043 (.015±.004) 0.39±0.10 (Stand off) (Seated height) 0.20(.008) S B 0.10(.004) S 0.10(.004) S AS0.20(.008) REF 0.80(.031) B REF 0.40(.016) REF 0.80(.031) A REF 0.40(.016) ABSMø0.08(.003)71-ø0.45 +0.10 –0.05 +.004 –.00271-ø.018 Dimensions in mm (inches). Note: The values in parentheses are reference values.

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept.

Summary

32 M Bit (2 M word횞16 bit) Mobile Phone Application Specific Memory

Description

32 M Bit (2 M word횞16 bit) Mobile Phone Application Specific Memory

Source title MB82DBS02163D-70L Datasheet(PDF) - fujitsu semiconductor

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