MB82D01171A-85PBN

MB82D01171A FUJITSU | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 27

Technical content

DS05-11404-2EFUJITSU SEMICONDUCTOR DATA SHEET MEMORY Mobile FCRAM TM CMOS

16 Mbit (1 M word ···· 16 bit)

Mobile Phone Application Specific Memory MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL CMOS 1,048,576-WORD ···· 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface nnnn DESCRIPTION The Fujitsu MB82D01171A is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This MB82D01171A is suited for low power applications such as Cellular Handset and PDA. Note: FCRAM is a trademark of Fujitsu Limited, Japan. nnnn PRODUCT LINEUP nnnn PACKAGES Parameter MB82D01171A 80 80L 80LL 85 85L 85LL 90 90L 90LL Access Time (tAA Max, tCE Max) 80 ns 85 ns 90 ns Active Current (IDDA1 Max) 20 mA Standby Current (IDDS1 Max) 200 mA 100 mA7 0 mA 200 mA1 0 0 mA 70 mA 200 mA 100 mA 70 mA Power Down Current (IDDP Max) 10 mA 48-ball plastic FBGA 48-ball plastic FBGA (BGA-48P-M16) (BGA-48P-M18)

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn FEATURES

• Asynchronous SRAM Interface
• 1 M w o r d · 16 bit Organization
• Fast Random Cycle Time : tRC = 90 ns
• Fast Random Access Time : tAA = tCE = 80 ns, 85 ns, 90 ns
• Low Power Consumption : IDDS1 = 200 mA, 100 mA (L version) , 70 mA (LL version)
• Wide Operating Conditions : VDD = +2.3 V to +2.7 V +2.7 V to +3.1 V +3.1 V to +3.5 V TA = -30 °C to +85 °C
• Byte Write Control
• 4 words Address Access Capability
• Power Down Control by CE2

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn PIN ASSIGNMENTS nnnn PIN DESCRIPTION Pin Name Description A0 to A19 Address Input CE 1 Chip Enable (Low Active) CE2 Chip Enable (High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Write Control (Low Active) UB Upper Byte Write Control (Low Active) DQ 1 to DQ8 Lower Byte Data Input/Output DQ 9 to DQ16 Upper Byte Data Input/Output VDD Power Supply VSS Ground NC No Connection A B C D E F G H A CE1 OE VSS A17 DQ 1 DQ 9 DQ 10 DQ 2 UB LB A18 NC DQ 3 DQ 11 DQ 12 DQ 4 CE2 WE NC A19 DQ 6 DQ 13 VDD DQ 5 A10 A11 DQ 8 DQ 15 DQ 14 DQ 7 A12 A13 A14 A15 A16 NC DQ 16 VSS 16 5432 A B C D E F G H LB DQ DQ 10 VSS VDD DQ 15 DQ 16 A18 OE UB DQ 11 DQ 12 DQ 13 DQ 14 A19 A17 NC A14 A12 A16 A15 A13 A10 CE1 DQ 2 DQ 4 DQ 5 DQ 6 WE A11 CE2 DQ 1 DQ 3 VDD VSS DQ 7 DQ 8 NC 16 5432 (TOP VIEW) Flash Compatible FBGA (suffix PBT) SRAM Compatible FBGA (suffix PBN) (BGA-48P-M16) (BGA-48P-M18)

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn BLOCK DIAGRAM VDD VSS CE2 CE1 WE LB UB OE A0 to A19 DQ 1 to DQ8 DQ 9 to DQ16 Address Latch & Buffer Row Decoder Memory Cell Array 16,777,216 bit I/O Buffer Input Data Latch & Control Sense / Switch Output Data Control Column / Decoder Address Latch & Buffer Power Control Timing Control

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn FUNCTION TRUTH TABLE * 1 *1 : V = Valid, L = Logic Low, H = Logic High, X = either “L” or “H”, High-Z = High Impedance *2 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. *3 : Output Disable mode should not be kept longer than 1 ms. *4 : Byte control at Read mode is not supported. Mode CE 1C E 2 W E OE LB UB DQ 1 to DQ 8 DQ 9 to DQ 16 IDD Data Retention Power Down *2 XLXXXX H i g h - Z H i g h - Z I DDP No Standby (Deselect) H H XXXX H i g h - Z H i g h - Z I DDS Yes Output Disable*3 L H H X X High-Z High-Z IDDA Read*4 LXX Output Valid Output Valid Write LH LL Input Valid Input Valid Write (Lower Byte) L H Input Valid Invalid Write (Upper Byte) H L Invalid Input Valid

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn ABSOLUTE MAXIMUM RATINGS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. nnnn RECOMMENDED OPERATING CONDITIONS *1 : All voltages are referenced to VSS . *2 : Minimum DC voltage on input or I/O pins are -0.3 V . During voltage transitions, inputs may undershoot VSS to -1.0 V for periods of up to 5 ns. Maximum DC voltage on input and I/O pins are VDD + 0.3 V . During voltage transitions, inputs may positive overshoot to VDD + 1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min Max Voltage of V DD Supply Relative to VSS VDD -0.5 +3.6 V Voltage at Any Pin Relative to VSS VIN -0.5 +3.6 V VOUT -0.5 +3.6 V Short Circuit Output Current I OUT -50 +50 mA Storage Temperature T STG -55 +125 °C Parameter Symbol Value Unit Min Max Supply Voltage *1 VDD (31) 3.1 3.5 V VDD (27) 2.7 3.1 V VDD (23) 2.3 2.7 V VSS 00 V High Level Input Voltage *1, *2 VIH (31) 2.6 VDD + 0.3 and £ 3.6 V VIH (27) 2.2 V DD + 0.3 V VIH (23) 2.0 V DD + 0.3 V Low Level Input Voltage *1, *2 Ambient Temperature T A -30 85 °C

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn PIN CAPACITANCE (f = 1.0 MHz, TA = +25 °C) nnnn ELECTRICAL CHARACTERISTICS 1. DC Characteristics (Continued) Parameter Symbol Conditions Value Unit Min Typ Max Address Input Capacitance C IN1 VIN = 0 V ¾¾ 5p F Control Input Capacitance C IN2 VIN = 0 V ¾¾ 5p F Data Input/Output Capacitance C IO VIO = 0 V ¾¾ 8p F Parameter Symbol Conditions Value Unit Min Max Input Leakage Current I LI VSS £ VIN £ VDD -1.0 +1.0 mA Output Leakage Current I LO 0 V £ VOUT £ VDD , Output Disable -1.0 +1.0 mA Output High Voltage Level VOH(31) VDD = VDD(31), IOH = -0.5 mA 2.4 ¾ V VOH(27) VDD = VDD(27), IOH = -0.5 mA 2.25 ¾ V VOH(23) VDD = VDD(23), IOH = -0.5 mA 1.8 ¾ V Output Low Voltage Level V OL IOL = 1 mA ¾ 0.4 V VDD Power Down Current I DDP VDD = VDD(31) Max, VIN = VIH or VIL, CE2 £ 0.2 V ¾ 20 mA VDD = VDD(27, 23) Max, VIN = VIH or VIL, CE2 £ 0.2 V ¾ 10 mA VDD Standby Current IDDS VDD = VDD(31) Max, VIN = VIH or VIL CE 1 = CE2 = VIH, IOUT = 0 mA ¾ 5.5 mAL Version ¾ 2.0 LL Version ¾ 1.5 IDDS VDD = VDD(27, 23) Max, VIN = VIH or VIL CE 1 = CE2 = VIH, IOUT = 0 mA ¾ 5 mAL Version ¾ 1.5 LL Version ¾ 1 IDDS1 VDD = VDD(31) Max, VIN £ 0.2 V or VIN ‡ VDD - 0.2 V, CE 1 = CE2 ‡ VDD - 0.2 V, IOUT = 0 mA ¾ 250 mAL Version ¾ 150 LL Version ¾ 120 IDDS1 VDD = VDD(27, 23) Max, VIN £ 0.2 V or VIN ‡ VDD - 0.2 V, CE 1 = CE2 ‡ VDD - 0.2 V, IOUT = 0 mA ¾ 200 mAL Version ¾ 100 LL Version ¾ 70

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) Notes:• All voltages are referenced to Vss.

• DC Characteristics are measured after following POWER-UP timing.
• IOUT depends on the output load conditions. Parameter Symbol Conditions Value Unit Min Max VDD Active Current IDDA1 VDD(31) = VDD Max, VIN = VIH or VIL, CE 1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = Min ¾ mA VDD(27, 23) = VDD Max, VIN = VIH or VIL, CE 1 = VIL and CE2 = VIH, IOUT = 0 mA IDDA2 VDD(31) = VDD Max, VIN = VIH or VIL, CE 1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = 1 ms ¾ 4.0 mA VDD(27, 23) = VDD Max, VIN = VIH or VIL, CE 1 = VIL and CE2 = VIH, IOUT = 0 mA 3.0

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 2. AC Characteristics (1) Read Operation *1: The output load is 30 pF . *2: The output load is 5 pF . *3: The t CE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable only to A0 and A1 when both CE1 and OE are kept at Low for the address access. *5: Applicable if OE is brought to Low before CE1 goes Low. *6: The tASO , tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE . If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtraction actual value from specified minimum value. For example, if actual t ASO , tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1 stays Low) , the tOE become tOE (Max) + tASO (Min) - tASO (actual) . *7: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) - tCLOL (actual) or tRC (Min) - tOP (actual) . *9: Maximum value is applicable if CE1 is kept at Low. Parameter Symbol -80/-80L/ -80LL -85/-85L/ -85LL -90/-90L/ -90LL Unit Notes M i nM a xM i nM a xM i nM a x Read Cycle Time t RC 90 ¾ 90 ¾ 90 ¾ ns Chip Enable Access Time t CE ¾ 80 ¾ 85 ¾ 90 ns *1, *3 Output Enable Access Time t OE ¾ 45 ¾ 45 ¾ 45 ns *1 Address Access Time t AA ¾ 80 ¾ 85 ¾ 90 ns *1, *4 Output Data Hold Time t OH 5 ¾ 5 ¾ 5 ¾ ns *1 CE 1 Low to Output Low-Z t CLZ 5 ¾ 5 ¾ 5 ¾ ns *2 OE Low to Output Low-Z t OLZ 0 ¾ 0 ¾ 0 ¾ ns *2 CE 1 High to Output High-Z t CHZ ¾ 30 ¾ 30 ¾ 30 ns *2 OE High to Output High-Z t OHZ ¾ 25 ¾ 25 ¾ 25 ns *2 Address Setup Time to CE1 Low t ASC -5 ¾- 5 ¾- 5 ¾ ns *5 Address Setup Time to OE Low tASO 45 ¾ 45 ¾ 45 ¾ ns *3, *6 tASO[ABS] 10 ¾ 10 ¾ 10 ¾ ns *7 Address Invalid Time t AX ¾ 5 ¾ 5 ¾ 5n s * 4 CE 1 Low to Address Hold Time t CLAH 90 ¾ 90 ¾ 90 ¾ ns *4 OE Low to Address Hold Time t OLAH 45 ¾ 45 ¾ 45 ¾ ns *4, *8 CE 1 High to Address Hold Time t CHAH -5 ¾- 5 ¾- 5 ¾ ns OE High to Address Hold Time t OHAH -5 ¾- 5 ¾- 5 ¾ ns CE 1 Low to OE Low Delay Time t CLOL 45 1000 45 1000 45 1000 ns *3, *6, *8, *9 OE Low to CE1 High Delay Time t OLCH 45 ¾ 45 ¾ 45 ¾ ns *8 CE 1 High Pulse Width t CP 20 ¾ 20 ¾ 20 ¾ ns OE High Pulse Width tOP 45 1000 45 1000 45 1000 ns *6, *8, *9 tOP[ABS] 20 ¾ 20 ¾ 20 ¾ ns *7

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL (2) Write Operation *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP ) and tWRC (or tWR ) . *2: New write address is valid from either CE1 or WE is brought to High. *3: Maximum value is applicable if CE1 is kept at Low and both WE and OE are kept at High. *4: The tOEH is specified from end of tWC (Min) and is a reference value when access time is determined by tOE . If actual value is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low. *6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1 Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7: Applicable if CE1 stays Low after read operation. *8: tCW and tWP is applicable if write operation is initiated by CE1 and WE, respectively. *9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE, respectively. The tWR (Min) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the tCP (Min) must be satisfied. Parameter Symbol -80/-80L/ -80LL -85/-85L/ -85LL -90/-90L/ -90LL Unit Notes Min Max Min Max Min Max Write Cycle Time t WC 90 ¾ 90 ¾ 90 ¾ ns *1 Address Setup Time t AS 0 ¾ 0 ¾ 0 ¾ ns *2 Address Hold Time t AH 45 ¾ 45 ¾ 45 ¾ ns *2 CE 1 Write Setup Time t CS 0 1000 0 1000 0 1000 ns CE 1 Write Hold Time t CH 0 1000 0 1000 0 1000 ns WE Setup Time t WS 0 ¾ 0 ¾ 0 ¾ ns WE Hold Time t WH 0 ¾ 0 ¾ 0 ¾ ns LB and UB Setup Time t BS -5 ¾- 5 ¾- 5 ¾ ns LB and UB Hold Time t BH -5 ¾- 5 ¾- 5 ¾ ns OE Setup Time t OES 0 1000 0 1000 0 1000 ns *3 OE Hold Time tOEH 45 1000 45 1000 45 1000 ns *3, *4 tOEH[ABS] 20 ¾ 20 ¾ 20 ¾ ns *5 OE High to CE1 Low Setup Time t OHCL -3 ¾- 3 ¾- 3 ¾ ns *6 Address Hold Time to OE High t OHAH 0 ¾ 0 ¾ 0 ¾ ns *7 CE 1 Write Pulse Width t CW 60 ¾ 60 ¾ 60 ¾ ns *1, *8 WE Write Pulse Width t WP 60 ¾ 60 ¾ 60 ¾ ns *1, *8 CE 1 Write Recovery Time t WRC 15 ¾ 15 ¾ 15 ¾ ns *1, *9 WE Write Recovery Time t WR 15 1000 15 1000 15 1000 ns *1, *3, *9 Data Setup Time t DS 20 ¾ 20 ¾ 20 ¾ ns Data Hold Time t DH 0 ¾ 0 ¾ 0 ¾ ns CE 1 High Pulse Width t CP 20 ¾ 20 ¾ 20 ¾ ns *9

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL (3) Power Down Parameters (4) Other Timing Parameters *1: It may write some data into any address location if tCHWX is not satisfied. *2: Must satisfy tCHH (Min) after tC2LH (Min) . *3: Requires Power Down mode entry and exit after tC2HL . *4: The Input T ransition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate some timing parameters of AC specification. (5) AC Test Conditions Parameter Symbol Value Unit Note Min Max CE2 Low Setup Time for Power Down Entry t CSP 10 ¾ ns CE2 Low Hold Time after Power Down Entry t C2LP 100 ¾ ns CE 1 High Hold Time following CE2 High after Power Down Exit tCHH 350 ¾m s CE 1 High Setup Time following CE2 High after Power Down Exit tCHS 10 ¾ ns Parameter Symbol Value Unit Note Min Max CE 1 High to OE Invalid Time for Standby Entry tCHOX 20 ¾ ns CE 1 High to WE Invalid Time for Standby Entry tCHWX 20 ¾ ns *1 CE2 Low Hold Time after Power-up t C2LH 50 ¾m s* 2 CE2 High Hold Time after Power-up t C2HL 50 ¾m s* 3 CE 1 High Hold Time following CE2 High after Power-up tCHH 350 ¾m s* 2 Input Transition Time t T 12 5 n s * 4 Parameter Symbol Conditions Measured Value Unit Note Input High Level V IH VDD = 3.1 V to 3.5 V 2.6 V VDD = 2.7 V to 3.1 V 2.3 V VDD = 2.3 V to 2.7 V 2.0 V Input Low Level V IL VDD = 3.1 V to 3.5 V 0.5 V VDD = 2.7 V to 3.1 V 0.5 V VDD = 2.3 V to 2.7 V 0.4 V Input Timing Measurement Level V REF VDD = 3.1 V to 3.5 V 1.5 V VDD = 2.7 V to 3.1 V 1.3 V VDD = 2.3 V to 2.7 V 1.1 V Input Transition Time t T Between VIL and VIH 5n s

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn TIMING DIAGRAM 1. READ Timing #1 (OE Control Access) 2. READ Timing #2 (CE1 Control Access) CE1 Address OE DQ (Output) tRC tCE tOE tOP tOE tOLCH tOHZ tCLOL tASO tOLZ tOH tOHZ tOLZ tOH tRC tOHAH tASO tOHAH Address Valid A ddress Valid Valid Data OutputValid Data Output Note : CE2 and WE must be High for entire read cycle. CE1 Address OE DQ (Output) tRC tCEtASC tOE tOLCH tCP tCHZ tCE tCHZ tCLZ tOH tCLZ tOH tRC tCHAHtASCtCHAH Address Valid Address Valid Valid Data OutputValid Data Output Note : CE2 and WE must be High for entire read cycle.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 3. READ Timing #3 (Address Access after OE Control Access) 4. READ Timing #4 (Address Access after CE1 Control Access) CE1 Address (A19 - A2) Address (A1, A0) OE DQ (Output) tRC tRC tASO tOLAH tOE tOHZ tOLZ tOH tOH tOHAHtAA tAX Address Valid Address Valid Valid Data Output Valid Data Output Address Valid (No change) Address Valid Note : CE2 and WE must be High for entire read cycle. CE1 Address (A19-A2) Address (A1, A0) OE DQ (Output) tRC tRC tASC tCLAH tCE tCHZ tCLZ tOH tOH tCHAHtAA tAX Address Valid Address Valid Valid Data Output Valid Data Output Address Valid (No change) Address Valid Note : CE2 and WE must be High for entire read cycle.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 5. WRITE Timing #1 (CE1 Control) CE1 Address WE DQ (Input) UB , LB OE tWC tWS tAS tAH tAS tCW tWRC tWH tWS tBH tBStBS tOHCL tDS tDH Address Valid Valid Data Input Note : CE2 must be High for write cycle.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 6. WRITE Timing #2-1 (WE Control, Single Write Operation) CE1 Address WE DQ (Input) UB , LB OE tWC tCStOHCL tAStOHAH tAH tAS tCP tCH tWP tWR tBHtBS tOES tDStOHZ tDH Address Valid Valid Data Input Note : CE2 must be High for write cycle.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 7. WRITE Timing #2 (WE Control, Continuous Write Operation) CE1 Address WE DQ (Input) UB , LB OE tWC tCStOHCL tAStOHAH tAH tAS tWP tWR tBH tBStBS tOES tDStOHZ tDH Address Valid Valid Data Input

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 8. READ/WRITE Timing #1-1 (CE1 Control) CE1 Address WE DQ UB , LB OE tWC tWStWH tCP tAStCHAH tAH tASC tCW tWRC tWH tWS tBHtBS tOHCL tDS tCHZ tOH tDH tCLZ tOLZ tCLOL Read Data Output Write Data Input Write Address Read Address Note : Write address is valid from either CE1 or WE of last falling edge.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 9. READ/WRITE Timing #1-2 (CE1 Control) CE1 Address WE DQ UB , LB OE tRC tWStWH tWRC (Min) tASC tWRC tCHAH tAS tCP tWH tWS tBStBH tCE tOEH tDH tCLZ tOH tCHZ tOHCL Read Address Write Address Write Data Input Read Data Output Note : The tOEH is specified from the time satisfied both tWRC and tWR (Min) .

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 10. READ (OE Control) /WRITE (WE Control) Timing #2-1 CE1 Address Read Data Output Write Data Input WE DQ UB , LB OE tWC tWP tAS tAHtOHAH tASO tWR tBHtBS tOES tOH tOHZ tDS tDH tOLZ tOEH Low Write Address Read Address Note : CE1 can be tied to Low for WE and OE controlled operation. When CE 1 is tied to Low, output is exclusively controlled by OE.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 11. READ (OE Control) /WRITE (WE Control) Timing #2-2 CE1 Address Read Address Valid Read Data OutputWrite Data Input Write Address WE DQ UB , LB OE tRC tASO tAStOHAH tBStBH tWR tOEH tOE tOLZtDH tOHZ tOH tOES Low Note : CE1 can be tied to Low for WE and OE controlled operation. When CE 1 is tied to Low, output is exclusively controlled by OE.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 12. POWER DOWN Timing 13. Standby Entry Timing after Read or Write 14. POWER-UP Timing 1 tCHS tCHHtC2LPtCSP Power Down Entry Power Down Mode Power Down Exit High-Z CE1 CE2 DQ tCHOX tCHWX Active (Read ) Standby Active (Write) Standby CE1 OE WE Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period from either last address transition of A0 and A1, or CE1 Low to High transition. tCHHtC2LH tCHS VDD Min 0 V CE1 CE2 VDD Note : It is recommended to keep CE2 at Low during VDD power-up. The tC2LH specifies after VDD reaches specified minimum level.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 15. POWER-UP Timing 2 tCHHtC2HL tCSP VDD Min 0 V CE1 CE2 VDD tCHS tC2LP tC2HL Note : The tC2HL specifies from CE2 Low to High transition after VDD reaches specified minimum level. CE1 must be brought to High prior to or together with CE2 Low to High transition.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn DATA RETENTION 1. Low VDD Characteristics 2. Data Retention Timing Parameter Symbol Test Conditions Value Unit Min Max VDD Data Retention Supply Voltage VDR CE 1 = CE2 ‡ VDD - 0.2 V or, CE 1 = CE2 = VIH, 2.1 3.5 V VDD Data Retention Supply Current IDR VDD = VDD (23) , VIN = VIH (23) or VIL CE 1 = CE2 = VIH (23) , IOUT = 0 mA ¾ 5 mAL Version ¾ 1.5 LL Version ¾ 1 IDR1 VDD = VDD (23) , VIN £ 0.2 V or VIN ‡ VDD - 0.2 V, CE 1 = CE2 ‡ VDD - 0.2 V, IOUT = 0 mA ¾ 200 mAL Version ¾ 100 LL Version ¾ 70 Data Retention Setup Time t DRS VDD = VDD (27) at data retention entry 0 ¾ ns Data Retention Recovery Time t DRR VDD = VDD (27) after data retention 90 ¾ ns VDD Voltage Transition Time DV/Dt ¾ 0.5 ¾ V/ms 3.5 V VDD tDRS CE1 = CE2 ‡ VDD - 0.2 V or VIH (23) Min tDRR DV/Dt DV/Dt CE2 CE1 2.7 V 2.1 V 0.4 V VSS Data Retention Mode Data bus must be in High-Z at data retention entry.

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn ORDERING INFORMATION Part Number Package Remarks MB82D01171A-80PBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 80 ns Max, IDDS1 = 200 mA Max Flash Compatible Package MB82D01171A-80LPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 80 ns Max, IDDS1 = 100 mA Max Flash Compatible Package MB82D01171A-80LLPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 80 ns Max, IDDS1 = 70 mA Max Flash Compatible Package MB82D01171A-85PBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 85 ns Max, IDDS1 = 200 mA Max Flash Compatible Package MB82D01171A-85LPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 85 ns Max, IDDS1 = 100 mA Max Flash Compatible Package MB82D01171A-85LLPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 85 ns Max, IDDS1 = 70 mA Max Flash Compatible Package MB82D01171A-90PBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 90 ns Max, IDDS1 = 200 mA Max Flash Compatible Package MB82D01171A-90LPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 90 ns Max, IDDS1 = 100 mA Max Flash Compatible Package MB82D01171A-90LLPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 90 ns Max, IDDS1 = 70 mA Max Flash Compatible Package MB82D01171A-80PBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 80 ns Max, IDDS1 = 200 mA Max SRAM Compatible Package MB82D01171A-80LPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 80 ns Max, IDDS1 = 100 mA Max SRAM Compatible Package MB82D01171A-80LLPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 80 ns Max, IDDS1 = 70 mA Max SRAM Compatible Package MB82D01171A-85PBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 85 ns Max, IDDS1 = 200 mA Max SRAM Compatible Package MB82D01171A-85LPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 85 ns Max, IDDS1 = 100 mA Max SRAM Compatible Package MB82D01171A-85LLPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 85 ns Max, IDDS1 = 70 mA Max SRAM Compatible Package MB82D01171A-90PBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 90 ns Max, IDDS1 = 200 mA Max SRAM Compatible Package MB82D01171A-90LPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 90 ns Max, IDDS1 = 100 mA Max SRAM Compatible Package MB82D01171A-90LLPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 90 ns Max, IDDS1 = 70 mA Max SRAM Compatible Package

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL nnnn PACKAGE DIMENSIONS (Continued) 48-ball plastic FBGA (BGA-48P-M16) Dimensions in mm (inches) C 2000 FUJITSU LIMITED B48016S-1c-1 6.00±0.10 (.236±.004) 0.36±0.10 (.014±.004) .041–.004 +.006 –0.10 +0.15 1.05 INDEX AREA (Mounting height) (Stand off) 0.10(.004) 0.20(.008) S S (5.60(.220)) (4.00(.157)) 0.80(.031) TYP 0.80(.031) TYP HGFEDCBA 48-Ø0.45±0.10 (48-Ø.018±.004) M0.08(.003)

MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) 48-ball plastic FBGA (BGA-48P-M18) Dimensions in mm (inches) C 2001 FUJITSU LIMITED B48018S-c-1-1 6.00±0.10 (.236±.004) 0.25±0.10 (.010±.004) .041–.004 +.006 –0.10 +0.15 1.05 INDEX AREA (Mounting height) (Stand off) 0.10(.004) 0.20(.008)S S (5.25(.207)) (3.75(.148)) 0.75(.030) TYP 0.75(.030) TYP H G FEDCB 48-ø0.35±0.10 (48-ø.014±.004) M0.08(.003) S A INDEX MARK

MB 82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0112 ª FUJITSU LIMITED Printed in Japan