MB8264A-10

MB8264A FUJITSU | Alldatasheet

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65,536-BIT DYNAMIC RANDOM ACCESS MEMORY The Fujitsu MB 82644 is a fully decoded, dynamic random access memory organized as 65,536 one-bit words. The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory, 2 peripheral storage and environments where low power dissipation and com: At pact layout is required. a thy Multiplexed row and column address inputs permit the MB8264A to be Shy Aa LY housed in a standard 16 pin DIP and 18 pad LCC. Pin-outs conform to the eS N y je JEDEC approved pin out. The MB 8264A is fabricated using silicon gate NMOS and Fujitsu's advanced Double-Layer Polysilicon process. This process, coupled with single-transistor CERAM PAGE memory storage cells, permits maximum circuit density and minimal chip size. pipiec.coa Dynamic circuitry is employed in the design, including the sense amplifiers. Clock timing requirements are non-critical, and power supply tolerance is very wide. All inputs and output are TTL compatible, © 65,536 x 1 RAM, 16 pin DIP/18— @ ~-RAS-only and Hidden refresh pad LOC capability , © Silicon-gate, Double Poly NMOS, ® Read-Modify-Write and Page-Mode 9 single transistor cell capability KA © Row access time, © Common 1/0 capability using PLASC erMO 100 ns max (MB 8264A-10) Early Write operation 120 ns max (MB8264A-12) —@ Output unlatched at cycle end LOG 100-702: Bee Page 1-101 150 ns max (MB 8264A-15) allows extended page boundary © Cycle time, and two-dimensional chip select PIN ASSIGNMENT 190 ns min (MB 8264A-10) © On-chip latches for Addresses and 230 ns min (MB 8264A-12) Data-in 260 ns min (MB 8264A-15) “a woh vss © Single s5V Sepply, «10% tolerance 2 AR TwER. foun ate eliminated ont sos ingle ply, =10% tolerance» standard 16-pin Ceramic (Cerdip) wo 14Boour © Low power (active) DIP: Surfix-Z wes vor BD 275 mW max (MB 8264A-10) Standard 16-pin Plastic aoC]s VI TAs 248 mW max (MB 8264A-12) Dip. SurfixP nie sae 220 mW max (MB 8264-15) Standard 18-pad Ceramic wd? pan 22 mW Standby (max) LCC: ‘Surfix-TV vec(]® sp. @ = 2ms/128 refresh cycles TI Teer ABSOLUTE MAXIMUM RATINGS (See NOTE) Lt Voltage on any pin relative 10 Vss SEE ve Abs Voltage on Vcc supply relative to Vss oli as Short circuit ourput current ee NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM | [hE device containg ckcultyy te protees Se RATINGS are exceeded, Functional operation should be restricted to ogee ‘or electric fields. However, it is advised the conditions as detailed in the operational sections of this data 'at_normal precautions be taken to avoid Sheet, Exposure to absolute maximum rating conditions for extended | from vated ‘voltage: to this migh ‘enpeaanes periods may aftect device reliability circuit 1-176

Fig. 1 - MB 8264A BLOCK DIAGRAM Ras. ‘CLOCK GEN. GEN. i COLUMN DATA DECODER IN Din Ay SENSE AMPS J [see a 32 3 2 nde _ As DATA ar 8 65,536 BIT a STORAGE CELL SUBSTRATE - ~Vec CAPACITANCE «7; = 25°c) ee ap [omcnnineedowr tw 1177

MB 8264A-10 _TilifliLitiialiil MB 8264A-12 FUJITSU MB 8264A-15 _[itbllliifisl RECOMMENDED OPERATING CONDITIONS (Referenced to Vss) Operating [ream | Symbol | wm | ne [mm | vet Temperature Supply Vol Vee ¥ I} te ipply Voltage Ves v — “v pel fale Note * : The device can withstand undershoots to the ~2V level with a pulse width of 20 ns. (Recommended operating conditions unless otherwise noted.) OPERATING CURRENT * MB 8264A-10 [so | Average power supply current MB 8264A-12 leer [45 | om (RAS, CAS cycling: tac = min) MB 8264A-15 {| 40 | STANDBY CURRENT 1 Standby Power supply current [RAS = CAS = Vix) cee REFRESH CURRENT * MB 8264A-10 | se | | Aer power sot arent we ezeaai2| eco — (CAS = V4 ,RAS cycling: tae=min) MB 8264A-15 PAGE MODE CURRENT* MB 8264A-10 Average power supply current MB 8264-12} loca | 32 | mA (RAS = Vi., CAS cycling: tec = min} MB 8264A-15 INPUT LEAKAGE CURRENT Input leakage current, any input (OVSV iv $5.5V, Veo=5.5V, Veg=0V, all other pins not test=OV) OUTPUT LEAKAGE CURRENT low HA (Data out is disabled, OVSVourS5.5) OUTPUT LEVELS Output high voltage (lon, = -5MA) Vou v Output low voltage (Io. = 4.2m A) Vou v Note *: Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open. 1-178

(Mise MB 8264A-10 FUJITSU MB 8264A-12 ei MB 8264A-15 eee ee CS ernie oes) I _——o oe Time between Refresh [rer | [2 | fe? | [2 | me Random Read/Write Cycle Time [tac | 190 | | 290 | | 260 | | as Read-Write Cycle Time [tawe | 230 | | 265 | | 280 | | ns Page Mode Cyele Time [wc [1s [| a0 | [a5 [| ns Page Mode Read-Write Cycle Time [tence] 135 | | 15 | | 120 | | ns Access Time from RAS oo [100 | f10 [|_| os | ‘Access Time from CAS _ Cr) es Output Buffer Turn Off Delay [o fs fo [x | [40 | ns | Transition Time fe [3 [so [a |e [3 [60 | os | Cras teaming foe RAS Hold Time [rmsw [80 [| eo [| 7s || ss | Hesse Tx mama —es epee [cas Pie Tne Acerca Tens | [|| [as | 1m | rr [castoe tie ie ot ttt | Uistetxsbeortim WW fey | [po wpa ef | [aS onadPecing Tie Lew fo | pe] fe} [=| Row Address Set Up Time [tase [of fo | fo fs | Row Address Hold Time [tron | of fo ff Ts | Column Address Set Up Time ltsc | o | [|o | |[o | | as | Column Address Hold Time | tea | 15 | [fof ns | Read Command Set Up Time Tacs Ie opt Read Command Hold Time Referenced to CAS Ml | tac | as | Read Command Hold Time Referenced to RAS | tann [2] ae ns Write Command Set Up Time @ [is | o | |__| ns | [Wie conmind edi nTime fem ff | fe | [owinsuntine fe foe fe [extn ide fo af as [eas eW onay ene ao [wf [AS WE by Tine Dee ef [Ret nashosew ORR Tee Roar wen [we [=| t@ [lp @ |p» |— 1-178

MB 8264A-10 Iiilltfiillithai) MB 8264A-12 FUJITSU MB 8264A-15 _|ifhtilliiilititi) Notes: Bh An initial pause of 200 us is required after power-up reference point only; if taco is greater than the followed by any 8 RAS cycles before proper device specified taco (max) limit, then access time is operation is achieved. controlled exclusively by tcac- @ AC characteristics assume ty = 5ns. BI taco (min) = tran (min) + 2ty (ty=5ns) + tasc (min) Bi Vin (min) and Vi. (max) are reference levels for Bl twcs. tewo and tawo are not restrictive operating measuring timing of input signals. Also, transition parameters. They are included in the data sheet as times are measured between Vj), (min) and Vi, (max). electrical characteristics only. If twcs 2 twcs (min) Bi Assumes that taco $ taco (max). If taco is greater the cycle is an early write cycle and the data out pin ‘than the maximum recommended value shown in this will reman ‘open circuit (high impedance) throughout table, taac Will increase by the amount that taco entire cycle. ‘exceeds the value shown. Hf tewo2tcwo (min) and trwo 2 tawo (min), the cycle is a read-write cycle and data out will contain BI Assumes that taco > taco (max). data read from the selected cell. If neither of the above BB Measured with a load equivalent to 2 TTL loads and ‘sets of conditions is satisfied the condition of the data 100 pF. out is indeterminate. @ Operation within the taco (max) limit insures that HD Either tann or tach must be satisfied for a read trac (max) can be met. taco (max) is specified as a cycle. Read Cycle tt | AAS Vin | | RAS View i tere | ee tre | SH ie treo of = tas __ vin teas oS -tcpn— tasa i tRAN TASC) tcan A ee Vin RoW COLUMN | roonesses J" X aos KX Koos XT) | | le trane| tress —-ltace we Vin vu be teac ——4 tt torr Dour Vou= J ig.z {vad Vou - DATA (Don't Care 1-180

KCN! MB 8264A-10 FUJITSU MB 8264A-12 WO MB 8264A-15 Write Cycle (Early Write) tac tRAS: aw vw vie= “ tonp TCS tre: tRCO~ teas ty we ye LN fl) me tCPN: tasr | |tRaH ‘asc tan ADORESSES y,1— ADDRESS ADDRESS wes, Lo —_ Vine we we vn yor" Leal ee Via J VALID On Viw- DATA D, Vow GZ our Vou [J Don't care Read—Write/Read—Modify—Write Cycle tawe Vin tere Tes oe Ane: taco. tex _ Vin os vee KN ff tcpn—o4 tasr|| tran Asc toan ADORESSES yi" aooness)X DK _ADoness [a $j} towe tacs tewo taWe _ vin We vir~ tcac—— ‘we _ Torr VAUD Dout Vo.- DATA | tna toH Vin~ ¥ VALID Dw vie : X Gata

1 Don't care

MB 8264A-15 _|iliiilftliltl Page Mode Read Cycle teas +] — Yin- 1) RS 7 ve sone| =e ree tnar—| = vin JET 5 . * i a avpresses Vi" ROK SEEK | EK LEK tcac: tcac: tcac: tRac torr sorr te] [torr lr 7 Dour YOHT iz Wp Wp Vou tacs tRRH ‘RCS: 'RCH: “RCH we ye 7 ve we [pont core vos one Page Mode Write Cycle RAS Vin> ve one tes RSH TAP. _ tRCO tease tce- tCAS: tcas: v N as ve Pa hscon NN tran E4ICAH ace tcaH tase tcaw tase ob htase — = aooresses ¥'"” ¥ROSK XB 585) Bex ‘ce Two wen vin i['ss [ss we vice fo N " EP iwe- lt P we! If hwe- tosj--} L144 tos ton tos] ton Own vie {oat KX vara) earn Dour Voi ou- [loon't care 1-182

Page Mode Read-Write Cycle Sm RP. — Yin AK we tore a teste ' trsu| , poe tncoy=teas pawe __ - cas ia, | tran tase | teas | Tew. “se ann a gs gD ea | Vin ROW i) voonees ec Bs RS XT XT t iS = ote aa we we L/ [Ls fT) te | a Vou", VALID VALID Dour yg Hinz [bara pare {bars ‘es | tH vine es, VALID VALID VALID Om wie ae re © Grae. @ Gre. [1 von't care RAS-only Refresh Cycle Note: WE, Djy = Don't care, Az = Vix or Vit bot tRAS' — Vin ARS ve tan tre tase Vine ROW (Ao to.Ag) tore tae CAS toFF Vown (1 don't care 1-183

MB 8264A-15 _|/Hfi/Hisinilellt Hidden Refresh Cycle tac. ARC: tras: tre tRAS- tae. Vinm RAS Vie- tcrP a re N Yi tasR torr ADORESSES Yi SoHE KX adotiss K we Vin~ o ACT “| tw tore Dour yon ad ( > 1+—taws tewol— ay pte we Vin (Read-weite) Vit— tos, tDH: Vin VALID EX) pnt core Address Inputs: (taan) specification has been satisfied the Data In (Diy) register. In a write A total of sixteen binary input address and the address inputs have been cycle, if WE is brought low (write bits are required to decode any 1 of changed from row-addresses to column: mode) before CAS, Diy is strobed by 65536 storage cell locations within the addresses. CAS, and the set-up and hold times are MB 8264A. Eight row-address bits are referenced to CAS. In a read-write established on the input pins (Ag Write Enable: cycle, WE can be low after CAS has through A;) and latched with the Row The read mode or write mode is selected been low and CAS to WE Delay Time ‘Address Strobe (RAS). The eight with the WE input. A high on WE (tcwo) has been satisfied. Thus Din is column-address bits are established on selects read mode and low selects write strobed by WE, and set-up and hold the input pins and latched with the mode. Data input is disabled when read _ times are referenced to WE. Column Address Strobe (CAS). All mode is selected. input addresses must be stable on or Data Output: before the falling edge of RAS. CAS is Data Input: The output buffer is three-state TTL internally inhibited (or “gated”) by Data is written into the MB 8264A dur- compatible with a fan-out of two stand- RAS to permite triggering of CAS as ing a write or read-write cycle. The later ard TTL loads. Data-out is the same soon as the Row Address Hold Time falling edge of WE or CAS is a strobe for polarity as data-in. The output is in a 1-184

‘NUNN MB 8264-15 hhigh impedance state until GAS is ations in which the row addresses don’t because the output buffer is in a high brought low. In a read cycle, or read- change. Thus the power dissipated by impedance state unless CAS is brought write cycle, the output is valid after the falling edge of RAS is saved. Fur- low. Strobing each of 128 row-addresses trac from the falling edge of RAS ther, access and cycle times are de- with RAS will cause all bits in each row when taco (max) is satisfied, or after creased because the time normally re- to be refreshed. Further RAS-only re- tcac from the falling edge of CAS when quired to strobe a new row addresses are fresh results in a substantial reduction in the transition occurs after taco (max). eliminated. power dissipation. Data remains valid until CAS is returned to a high. Ina write cycle the indentical RAS-only Refresh Hidden Refresh: sequence occurs, but data is not valid. Refresh of the dynamic memory cells is RAS-only refresh cycle may take place accomplished by performing a memory while maintaining valid output data. Page Mode: cycle at each of the 128 row-addresses This feature is referred to as Hidden Page-mode operation permits strobing (Ag ~ Ag) at least every two milli- Refresh. the row-address into the MB8264A seconds. During refresh, either Vix or Hidden Refresh is performed by holding while maintaining RAS at a low Vi is permitted for Ay. RAS-only re- CAS as Vi. from a previous memory throughout all successive memory oper- fresh avoids any output during refresh read cycle. Fig. 2— CURRENT WAVE FORM (Vcc *5.5V, Ta = 25°C) a SE SEE OO a ee ee el SSF EGERETigurari saa : ‘ \\ H iL Y a eee eee te at Ah | N abo Co EA 1-185,

MB 8264A-12, FUJITSU MB 8264A-15 Wisi tilt Fig. 3— NORMALIZED ACCESS TIME Fig. 4 — NORMALIZED ACCESS TIME vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE w w % 12h theo * 2005 4 ‘taco = 200s y 3 Qo g g | Ps 3 2 yo 8 109} ra z Fa fe 3° 3 g =, 08 08 zl | mT TTT = z . 4 45 s 55 6 -20° «0 20 40 «+60 80 100 Vee, SUPPLY VOLTAGE (V) Tq, AMBIENT TEMPERATURE (°C) Fig. 5 — OPERATING CURRENT Fig. 6 — OPERATING CURRENT vs CYCLE RATE vs SUPPLY VOLTAGE i 3 Ta= 25°C i soL- Ta 25°C E 80f-—trac * 200ns © a0 | 4 Ea 5 4 S a0 _ 8 4 8 2 30 we 2 = = = 2 L € 30) Fa 4 Fe aT TT tT ne ~ 0 oO 1 2 3 4 5 6 4 45 5 55 6 1 /te. CYCLE RATE (MHz) Voce. SUPPLY VOLTAGE (V) Fig. 7 — OPERATING CURRENT Fig. 8 - STANDBY CURRENT vs AMBIENT TEMPERATURE vs SUPPLY VOLTAGE = 50} tras = 100ns £ 4 com 5 Fd w E Fa ~ ae c

8 Ty 8 J Do

8 tr = 2500s z Fs 0 tac = 300ns a 2 & % 3 g | is a eS 2002040 60-80 F00 4 a5 5 55 6 Ta, AMBIENT TEMPERATURE (°C) Voc. SUPPLY VOLTAGE (v) 1-186

WH ~ MB 8264A-10 FUJITSU MB 8264A-12 eI ~MB 8264A-15 Fig. 9— STANDBY CURRENT Fig. 10— REFRESH CURRENT vs AMBIENT TEMPERATURE vs CYCLE RATE q z Vee = 854 £4 = sol —ta= 26°C 5 5 tras = 100ns 3 = 40 2 2 | 7iinnee Pe 2 —— @ 2 2 = ol Z| 3 3 10} 2 4 2 [| |] | 2020 406080700 ° 2 4 6 Ta, AMBIENT TEMPERATURE (°C) tac, CYCLE RATE (MHz) Fig, 11 — REFRESH CURRENT Fig. 12 — REFRESH CURRENT vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE E40} —-Ta¢ = 200ns E 40}—tpas = 100ns. 5 fs Fa Fe

3 Laan i == imi

z FA | Fe a Fd £ 20} £2) a > $ tro = 300ns Fr c c | 2 10) 10) {__ ee ee ee [| a ase 3 -2 020406080 T00 Vec, SUPPLY VOLTAGE(V) Ta, AMBIENT TEMPERATURE (°C) Fig. 13 - PAGE MODE CURRENT Fig. 14 — PAGE MODE CURRENT vs CYCLE RATE vs SUPPLY VOLTAGE € ~ = gl YS Set | || = gl Tan 28'e [| | - : “4 z tong 50ns faq ‘re oe Fe Fe c c i} 3 3 So A a is a a | oO 2 4 6 8 10 4 45 6 6.5 6 ‘Vtg, CYCLE RATE (MHz) Vee, SUPPLY VOLTAGE(v) 1-187

MB 8264A-10 _SIBILIBINEEIA MB 8264A-12 FUJITSU MB 8264A-15 _[sRNH/NAIUE Fig. 15 — PAGE MODE CURRENT Fig. 16 — ADDRESS AND DATA INPUT VOLTAGE vs AMBIENT TEMPERATURE vs SUPPLY VOLTAGE = 40}—tcas = 50ns 25 5 4 30 2 | #8 = od | i g5 3 89 M om tec = 1058 <3 29 _ g 25 + 2 20 [ T tec = 150ns, 2 g | = 8 a A 2 < 19) r | 3 + | ie a ao | 3 10 3

2 ME Ql

Ta, AMBIENT TEMPERATURE (°C) Voc, SUPPLY VOLTAGE (V) Fig. 17 — ADDRESS AND DATA INPUT VOLTAGE Fig. 18 — RAS, CAS AND WE INPUT VOLTAGE vs AMBIENT TEMPERATURE vs SUPPLY VOLTAGE 40 40 2 53.0) : 25 3.0} . | = 88 Bs rad we Vin (Min) 3 —_—— = ct =2 Vin (Max) >2 ~ < < z > ol G0 30 a0 60 8000 a Tq, AMBIENT TEMPERATURE (°C) Voc. SUPPLY VOLTAGE (V) Fig. 19 — RAS, CAS AND WE VOLTAGE vs AMBIENT TEMPERATURE 4.05 A 2530 8 @ 320 ee = S = | Fe 33,4 1 1 1 Tt > ol °30 02040608100 ‘Tq, ANBIENT TEMPERATURE (°C) 1-188

SEM) ~MB 8264A-15 Fig. 20 — CURRENT WAVE FORM DURING POWER UP >s >s zy 5 zy ¥ ag 32 rE ol AE ol #8 |_| 38 Td $8 28 20-—Ta = 25°C. . 2 3 ae é | FE z < RAS = CAS = Vv, ad = TAS = XE 10 > © rol —] FAS - CHS - Vos. & Pa a en a (A | Ty

3 ZZ RAS = CAS = Veo 3 = RAS = CAS = Vee]

A - Vt TTT) 0 0 104s/Division 100u8/Division Fig. 21 — CURRENT WAVE FORM DURING POWER uP (ON MEMORY BOARD) _ >s xs ag Ld a An az 38 ou 83 83

28 Taeaee SS raha

80} es - _ 5 iA tre 270s 5 tac = 270ns | £ sof > = 60 —- > E 40} £ 40) z= y MB 864A + Decoupling Fa (MB 8264A + Decoupling & capocttor (0.1K) g Z\\iseastorigut ® 20) = e 20} +

3 Decoupling capacitor 8 ja Decoupling capacitor

FL \\ilointiony eA einet ony ry by 20us/Division 100us/0ivision Fig. 22 — SUBSTRATE VOLTATE vs SUPPLY VOLTAGE (DURING POWER UP) za 4 ou 88 of a | Ta* 2c #4 RAS = CAS = Veo: as Eo go -2 Yl an a N 3 — LTT ‘50us/Division 1-189

MB 8264A-10__ Tifillliflizitth MB 8264A-12 FUJITSU MB 8264A-15 _|Wiiifiliittiit Standard 16-pin Ceramic DIP (Surfix : -2) 16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE (CASE No. : DiP-16C-C04) NM an casio fer geaiyan 3130798) 3021767) 2518.26) “T “788(20.02) 00810 201 —- = — 05011. 27)MAX Ellalead | 201s csinax ean 090(2.29) 03210813) if “| 0007 78iREF ° seu 13033) bimentionatn ae bo aig10.20) aera Nimetes Standard 16-pin Plastic DIP (Surfix : -P) 16-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-16P-M03) \\ oe ~15" INDEX asotgas) 2001730 Boies) otra) 7ieti8 oosto24) ora 38) a fe osots aa On 205 | 118{3.0)MIN- 1000258) 0401 WF : SHOT _o70\\0 50MIN “smantunein 947(1.20) inches (enilimeters) Seatts0t 1-190

EO, «MB 8264A-15 PACKAGE DIMENSIONS Standard 18-pad Ceramic LCC (Surfix : -TV) j 8PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER (CASE No Loo 180 F02) ° | 125,381 Ree 1 = A oT | H= c4 | | 3H, | foes 1-191