MB81F161622B-10

MB81F161622B-75 FUJITSU | Alldatasheet

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SS SUATASHIERT. | CC (0 805-11039-1E | _ MB81F161622B-75/-102/-100 0 CMOS 2 Banks of 524,288 x 16 Bit Synchronous Dynamic Random Access Memory DESCRIPTION ro ‘ed The Fujitsu MB81F161622B is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing 16,777,216 memory cells accessible in an 16-bit format. The MB81F161622B features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The: MB81F161622B SDRAM is designed to reduce the complexity of using a standard dynamic RAM (ORAM):which requires many control signal timing constraints, and may improve data bandwidth of memory.as much as 5 times more than a standard DRAM. The MB81F161622B is ideally suited for laser printers, high resolution graphic adapters, accelerators and other applications where an extremely large memory:and bandwidth are required and where a simple interface is ™@ PRODUCT LINE & FEATURES = [| _____—Parameter = =———_.|-: MB81F161622B-75 | MB81F161622B-102 | MB81F161622B-10 Access Time From Clock (CL= 3) “| 6insmax. | 6 ns max. (CL = 2) * Single +3.3 V Supply +0.3 V tolerance + Byte control by DQMU/DQML + LVTTL compatible I/O interface + Programmable burst type, burst length, + 4K refresh cycles every 64 ms and CAS latency + Dual banks operation + Auto-and Self-refresh (every 15.6 |1s) + Burst read/write operation and burst + CKE power down mode read/single write operation capability + Output Enable and Input Data Mask

@ PACKAGE 50-pin plastic TSOP (II) Marking side (FPT-50P-M05) (Normal Bend) Package and Ordering Information —50-pin plastic (400 mil) TSOP-II with normal bend leads,order as MB81F161622B-xxxFN

@ PIN ASSIGNMENTS AND DESCRIPTIONS 50-Pin TSOP (II) (TOP VIEW) <Normal Bend: FPT-50P-MO5> Veo of 30 a vee oa: Ey 2 49 Pos oa: OO s 43 FO 0a. Vooo EY 4 47 Woe oa C5 46 FOI00» oa oy 6 2s Poco. Veco EY 7 44 Veco ons: 4 43 Popa. oa oy o 42 Poaoa. Voeo EY 10 44 Vee ba: Ef 11 40 Poca. Da Ee 12 30 Pepa. Veco EE 13 38 Fo Veco came oxy 14 37 Peau WE Eo ts 36 fo bau CAS CO is 35 POICLK RAS of 17 34 Poacke TS oy to 33 Peou Aw Eq io 2 POA AWAP EX 20 31 Pow Ae Ee 21 20 Foa. a: Ed 2 2 Pow A: Ef 23 22 Fow A ed 24 27 fom Veo BEY 25 26 FO Ves, (Marking side) 1,7, 13, 25, 38, 44 Supply Voltage 43, 45, 46, 48, 49 DQ to DQis Data I/O + Row: = Aocto Ato 20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32 Ao to Ato Address Input | Column: Acto Ar * : These pins are connected internally in the chip.

@ BLOCK DIAGRAM Fig. 1 - MB81F161622B BLOCK DIAGRAM CLK To each block cLock BUFFER CKE ——| BANK-O [as Ras cs CONTROL |. SIGNAL |[ ST cas LATCH ons | Lt we WE DRAM CORE MODE (2,048 x 256 x 16) REGISTER oto Ari, BUFFER/ ROW AP REGISTER ian ADDR. en COL. | [| abbr. DOML COLUMN ADDRESS COUNTER vo DQMU VO DATA BUFFER/ REGISTER t Vic DQo <i Veco to Dis A Vss/Vss0

@ FUNCTIONAL TRUTHAL TABLE (Note 1) COMMAND TRUTH TABLE Notes 2,3,4 An | Ato Arto reton Nowe Symel Poi hid ied ada (BA) (AP) Ae aust Sop vest fH [x|efw[H[t[x|x| x |x| Precharge SngleBark | PRE | Hx |t{e[Hie|vie| x | x | Notes: “1. V = Valid, L = Logic Low, H = Logic High, X = either L or H *2. Allcommands assume no CSUS command on previous rising edge of clock. *3. Allcommands are assumed to be valid state transitions. *4. Allinputs are latched on the rising edge of clock. *5. NOP and DESL commands have the same effect on the part. *6. READ, READA, WRIT, and WRITA commands should only be issued after the corresponding bank has been activated (ACTV command). Refer to STATE DIAGRAM. *7. ACTV command should only be asserted after corresponding bank has been precharged (PRE or PALL command). *8. Required after power up. *9. MRS command should only be issued after all banks have been precharged (PRE or PALL command). Refer to STATE DIAGRAM.

Data Write/Output Enable for Lower Byte ENBL L Data Write/Output Enable for Upper Byte ENBL U Data Mask/Output Disable for Lower Byte MASK L pF oH | x [| H | x | Data Mask/Output Disable for Upper Byte MASK U CKE TRUTH TABLE Current Function Notes | CKE | An | Ato | Ao State [na] on | (BA) | (AP)| to Ao Bank Active | Clock Suspend Mode Entry*1,*5 | CSUS Any Except to Clock Suspend Continue 4 L/L] xX x x x x x x Idle Clock Self-refresh | Self-refresh Exit SELFX | H | | # | [4 Power Down Entry 3 LH | LH | i Power Down | Power Down Exit Notes: *1. The CSUS command requires that at least one bank is active. Refer to STATE DIAGRAM. *2. REF and SELF commands should only be issued after all banks have been precharged (PRE or PAL command). Refer to STATE DIAGRAM. *3. Self and PD commands should only be issued after the last data have been appeared on DQ. *4. Once it enters the auto-refresh mode, Asynchronous Self-Refresh Entry exceuted when CKE is brought Low together with DSEL or NOP command(ASE command) within tase. *5. NOP or DSEL commands should only be issued after CSUS and PRE(or PALL) commands asserted at same time.

OPERATION COMMAND TABLE (Applicable to single bank) a [eee come [rn = [she CS Sof ef me por cope [por SOLED D | exe [pe acest SUED ear [mera por Sop ef [ne for Soper SLED ene [pe fg SCTE [| ear [mera [res serve esa oe (Continued)

Read NOP (Continue Burst to End — ost Bank Active) L H x NOP (Continue Burst to End > Bank Active) Hope eC) | ear leon sta Terminate Burst, New Read; Sonat BA, CA, AP | READ/READA Determine AP Terminate Burst, Start Write; * BA, CA, AP | WRIT/WRITA Determine AP ‘4 SOG Cee : Terminate Burst, Precharge; — Idle Pefe fale BA, AP PRE/PALL Determine Precharge Type Write NOP (Continue Burst to End > ogo ost Bank Active) L x NOP (Continue Burst to End > Bank Active) SOC Terminate Burst, Start Read; Sonn BA, CA, AP | READ/READA Determine AP Terminate Burst, New Write; BA, CA, AP | WRIT/WRITA Determine AP SCOR soe : Terminate Burst, Precharge; pefe fale BA, AP PRE/PALL Determine Precharge Type Coe | er fo (Continued)

Read with NOP (Continue Burst to End — precharge L H x NOP (Continue Burst to End > Precharge — Idle) pefafel al BA, CA, AP | READ/READA | Illegal *2 BA, CA, AP | WRIT/WRITA | Illegal *2 pepe la |W] ears ACTV _ |lllegal 2 cece adel BA, AP PRE/PALL _ | Illegal *2 Pope) peri Write with NOP (Continue Burst to End Auto- ost Precharge ~ Idle) precharge L H x NOP (Continue Burst to End > Precharge — Idle) cepa} ela) BA, CA, AP | READ/READA | Illegal *2 BA, CA, AP | WRIT/WRITA | Illegal *2 pete l ala) BA, RA ACTV [Illegal 2 pefelalel BA, AP PRE/PALL | Illegal *2 SCLC | rer in (Continued)

(Continued) Refreshing DESL NOP (Idle after tac) *8 NOPST [NOP (eater 3 READ/READA/ WRITAWRITA man ACTV/PRE/ REF/SELF/ COG eee Register Sas’ eT pw enor ar eats pele e tet xe | est (mot READ/READA/ WRITAWRITA Mesa ACTV/PRE/ L L x x x PALL/REF/ SELF/MRS ABBREVIATIONS: RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge

COMMAND TRUTH TABLE FOR CKE liso refresh SOGoOme er SO00G0 eas (Self-refresh Recovery — Idle after tac) a Pee [ie PT [i refresh Peete Dee Pee Dee [ie Pee [ie COCR COS Es (Continued)

(Continued) Bank Aeve Reterto te Operation Command Table Bank Read/Write Suspend Any State Refer to the Operation Command Table Other Than Notes: “1. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means don’t used command. If used, power up sequence be asserted after power shut down. *2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. *3. Illegal if any bank is not idle. *4. Must satisfy bus contention, bus turn around, and/or write recovery requirements. *5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP). *6. SELF command should only be issued after the last read data have been appeared on DQ. *7. MRS command should only be issued on condition that all DQ are in Hi-Z. *8. Asynchronous Self-Refresh Entry executed when CKE is brought Low together with DSEL or NOP command(ASE command) within tase.

@ FUNCTIONAL DESCRIPTION SDRAM BASIC FUNCTION Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. An SDRAM uses a Clock input for the synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined by commands and all operations are referenced to a positive clock edge. Fig.2 shows the basic timing diagram differences between SDRAMs and DRAMs. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to justify the SDRAM operation and function into desired system conditions. MODE REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming. CLOCK (CLK) AND CLOCK ENABLE (CKE) All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a positive edge of CLK. Alll outputs are validated by the CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode(standby) is entered with CKE = Low and this will make extremely low standby current. CHIP SELECT (CS) TS enables all commands inputs, RAS, CAS, and WE, and address input. When TS is High , command signals are negated but internal operation such as burst cycle will not be suspended. If such a control isn't needed, TS can be tied to ground level. COMMAND INPUTS (RAS, CAS AND WE) Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address strobe by RAS. Instead, each combination of RAS, TAS, and WE input in conjunction with TS input at a rising edge of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5. ADDRESS INPUTS (Ac to Aio) Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of nineteen address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to reduce the pin count of the address line. Ata Bank Active command (ACTV), eleven Row addresses are initially latched and the remainder of nine Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or Write command (WRIT or WRITA). BANK SELECT (A:1) This SDRAM has two banks and each bank is organized as 512 K words by 16-bit. Bank selection by A1: occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT or WRITA), and precharge command (PRE).

DATA INPUTS AND OUTPUTS (DQc to DQis) Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input: trac; from the bank active command when treo (min) is satisfied. (This parameter is reference only.) teac : from the read command when trco is greater than taco (min).(This parameter is reference only.) tac : from the clock edge after trac and teac. The polarity of the output data is identical to that of the input. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tox). DATA I/O MASK (DQML/DQMU) DQML and DQMU are active high enable inputs and have an output disable and input mask function. During burst cycle and when DQML/DQMU = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. DQML controls lower byte (DQo to DQ7) and DQMU controls upper byte (DQs to DQis). BURST MODE OPERATION AND BURST TYPE The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tac and tcx, respectively. The internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1,2,4 or 8 bits of boundary. In order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: Current Stage Next Stage Method (Assert the following command) Burst Read Burst Read Read Command 1st Step Mask Command (Normally 3 clock cycles) Burst Read Burst Write 2nd Step | Write Command after lowo Burst Write Burst Write Write Command Burst Write Burst Read Read Command Burst Read Precharge Command Burst Write Precharge Command The burst type can be selected either sequential or interleave mode if burst length is 2,4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address(=0). The interleave mode is a scrambled decoding scheme for Ao and Az. If the first access of column address is even (0), the next address will be odd (1), or vice-versa. (Continued)

(Continued) When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write operation. The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address(=0). Burst Stating Column - ress equential Mode erleave eh Add Sequential Mod Inter! s Ac Ar Ao Se ed fe FULL COLUMN BURST AND BURST STOP COMMAND (BST) The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps round to first column address (=0) and continues to count until interrupted by the news Read (READ) /Write (WRIT) , Precharge (PRE) , or Burst Stop (BST) command. The selection of Auto-precharge option is illegal during the full column burst operation except write command at BURST READ & SINGLE WRITE mode. The BST command is applicable to terminated burst operation. If the BST command is asserted burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When read mode is interrupted by BST command, the output will be in High-Z. For the detail rule, please refer to TIMING DIAGRAM-8. When write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored. BURST READ & SINGLE WRITE The burst read and single write mode provides single word write operation regardless of its burst length. In this mode, burst read operation does not affected by this mode.

PRECHARGE AND PRECHARGE OPTION (PRE, PALL) SDRAM memory core is the same as conventional DRAMs'’, requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE). With the Precharge command, SDRAM will automatically be in standby state after precharge time (tae) The precharged bank is selected by combination of AP and A11 when Precharge command is asserted. If AP = High, both banks are precharged regardless of A:: (PALL). If AP = Low, a bank to be selected by A is precharged (PRE). The Auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command assertion. This Auto-precharge is entered by AP = High when a read or write command is asserted. Refer to FUNCTION TRUTH TABLE. AUTO-REFRESH (REF) Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 15.6 1s or a total 4096 refresh commands within a 64 ms period. SELF-REFRESH ENTRY (SELF) Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once SDRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level state) and outputs will be in a High-Z state. During a Self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ. ASYNCHRONOUS SELF-REFRESH ENTRY(ASE) The SELF command requires high speed control to the CKE as well as other command inputs. The MB81F161622B supports Asynchronous Self-refresh entry and it executed when CKE is brought Low together with DSEL or NOP command(ASE command) within tase(min). Once it enters the self-refresh mode, CKE=Low should be maintained as the same manner as regular Self-refresh mode. ASE command should only be effective if not of access command is issued after the last REF command has been issued. SELF-REFRESH EXIT (SELFX) To Exit SElf-Refresh mode, apply minimum tcxsr before CKE brought high, and then the NOP command (NOP) or the Deselect command (DESL) should be asserted within minimum tRC. Refer to Timing Diagram for the detail. It is recommended to assert an Auto-refresh command just after the tac period to avoid the violation of refresh period. MODE REGISTER SET (MRS) The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE in page 33. The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of SDRAM. Refer to POWER-UP INITIALIZATION below.

The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 200 ps. 3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL). 4. Assert minimum of 8 Auto-refresh command(REF). 5. Program the mode register by Mode Register Set command(MRS). In addition, it is recommended DQML/DQMU and CKE to track Vcc to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 8 Auto-refresh command (REF).

Fig. 2— BASIC TIMING FOR CONVENTIONAL DRAM vs. SYNCHRONOUS DYNAMIC RAM <SDRAM> Active ReadWrite Precharge eo FLEPU FLUUULUL Ue Ho p= CKE : : : : : : tr ty te : : : : : : ‘ : H:Read : : : WC y ‘ \\Y WN p CBC’ FPCP>E—.°»p» UKriWwws x WY “BA(An) ” BA(An) : : BA (An) RA . ’ CAS Latency =2 » AP (Aro) : : ‘ : BurstLength=4 | : <Conventional DRAM> + ‘ : ! t : ! Row Address Select ' : * Precharge RAS \\ : Column Address Select {

CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION Second command > é bE < 4 uo (same Qa E a a ank) By} < £ fa z i < iv Ss a on — tase trsc eee 222 2 =| trsc tase tasc fm | ACV FL em | treo treo | treo LL READA BL+ | Ble | fF Bl | Ble tee bel tee — na 1 1 be ee tac te || fit tre tre Notes: *1. Assume no I/O conflict. *2. If tae < tex, minimum latency is a sum of BL + CL. *3. Assume Output is in High-Z state. *4. Assume tras is satisfied. -—_|_ Illegal Command

CLOCK LATENCY OR DELAY TIME FOR 2 BANK OPERATION Second commani (opposite 6 = 4 u bank) é iva = Ww < vd = a 7) mms [me | me || - - ia bee treo aso tre | te tre wat | 1 1 eo 4 2 2 2 4 1 1 1 1 tre PALL | , =| | the tre Notes: “1. Assume opposite bank is in idle state. *2. Assume opposite bank is in active state. *3. Assume no I/O conflict. *4. If tre < tox, minimum latency is a sum of BL + CL. *5. Assume PALL command dose not affect any operation on opposite bank. *6. Assume Output is in High-Z state. *7. Assume tas of opposite bank is satisfied. *8. Assume tras(ACTV to PALL) is satisfied. *9. If opposite bank should be interrupted, tRAS of own bank is satisfied... Illegal Command

Fig. 3— STATE DIAGRAM (Simplitied for Single Bank Operation State Diagram) MRS SELF REGISTER SELFX SET CKE ASE ckA\\Pp) POWER AUTO DOWN REFRESH CKE\\ BANK ACTIVE Cre SUSPEND ACTIVE (wr) ; READA’ ° 7 CKE read CEL (READ USPEN Lg || war\\_ Lg oxe | </ \\— WRITA r\\/ . Wea ve READA Ke . /walre with B34 Crono wiTH\\ CKE\\ READ AUTO we ‘AUTO SUSPEND cKe\\ | PRECHARGE ae PRECHARGE gg CKE | PRE or PRE or PALL PALL PRE or PALL POWER or PRECHARGE POWER APPLIED DEFINITION OF ALLOWS Manual Automatic ——> input — FP Sequence

@ ABSOLUTE MAXIMUM RATINGS (See WARNING) Voltage of Vcc Supply Relative to Vss 0.5 to +4.6 Voltage at Any Pin Relative to Vss 0.5 to +4.6 Short Circuit Output Current —50 to +50 WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. @ RECOMMENDED OPERATING CONDITIONS (Referenced to Vss) uo Von u age Notes: *1. Overshoot limit: Vix (max) = TBD. *2. Undershoot limit: Vi (min) = —1.5 V with a pulsewidth < 5 ns WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. @ CAPACITANCE (Ta = 25°C, f = 1 MHz) Symbol] win] Tye | Mex [Unt]

@ DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 1, 2 7" Value . Ouipat High Votiage Output Low Voltage [ Vowoo [lne2mA | (| OV < Vis Voc; Input Leakage Current (Any Input) lu All other pins not under +5 5 pA test=0V OV < Vis Veo; Burst: Length = 4, MB81F16422B-75 tro= min for BL = 4, 100 tex = min, One bank active, MB81F16422B-102 | °° | Outputs open, 100 mA Addresses changed up to Operating Current | MB81F161622B-10 ous, uring trc(min), 80 (Average Power Burst Length 4 (each bank) = 4 (each bank), Supply Current) | #581F164208-75 tho= min fOr BL = 4,eon.aro, 150 tex = min, All banks active, MB81F16422B-102 Output open, 140 mA Addresses changed up to MB81F161622B-10 3-times during tso(min), 120 OV<Vws Veo CKE = Vi, All banks idle, Iccee | tex = min, 400 Power down mode, OV< Vis Voc yA CKE=Vi, All banks idle, Iccers |CLK=HorL, 400 Power down mode, OV < Vins Veco Precharge Standby CKE = Vix, Current MB81F16422B-75 All banks idle, 27 (Power Supply tex = min, Current) NOP commands only, MB81F16422B-102 Iccan | Input signals(except to 20 CMD) are changed one times during 3 clock mA MB81F161622B-10 cycles, 20

0 V< Vins Voc

CKE = Vin, All banks idle, lccans |CLK = HorL, 15 Input signals are stable, OV <Vin< Veo (Continued)

(Continued) | Parameter _[Srmbat| cantons twa UE CKE = Vi, Any bank active, loos? tox = min, 5 mA Active Standby Current 0V<Vws Veo (Power Supply Current) CKE=Vi, Any bank active, CLK=HorL, 3 mA OV< Vins Veo CKE = Vix, MB81F16422B-75 Any bank active, 54 mA " tex = min, Aetive Standby NOP commands only, (Power Supply MB81F16422B-75 Iccan Cea) eer to mA are changed one Current) times during 3 clock MB81F161622B-10 cycles, 40 mA OV <Viw< Veo CKE = Vin, lcoans | Oy Dani active, 25 | mA OV< Vis Veo MB81F16422B-75 tex = min, Burst mode Burst Length = 4, Current Outputs open, (Average Power MB81F16422B-102 Veo Multiple-banks active, ma Supply Current) Gapless data, MB81F16422B-10 OV < Vins Veo Refresh Current #1 Autorefresh; (Average Power MB81F16422B-102 loos | tec= min, mA Supply Current) 0V< Vine Veo MB81F16422B-10 8 Self-refresh; Refresh Current #2 loos | tox = min, 400 WA (Average Power Supply Current) CKE <0.2V, 0V< Vins Veo Asynchronous Self- Refresh Current #2 ee (oy ck stop); WA (Average Power Supply Current) CLK =ViL , OV < Vins Veo

@ AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 2, 3, 4 Parameter Notes 775 “102 710 clock Pore OnStar 2, we [S| — | | — | 6) — | Cocco Tine | tm fe | | 8 | = | 8 | = fe [Coactowtime tm es | 8 | fe | [oe | lmpuSeuptime | we | | 2 || 2 | [os fmouttiod time tw | 1 | | 1 |=] 1 | | oo | Jounintow2 tw | | | | | 0 | [oe aStateney=3[ ta | 2 | 6 | 8 | 6 | 8 | 6 | ns | r2[=[s/[=[s ||| [Time between Auto-refresh command interval | teen | — | 186 | — | 156 | — | 15.6 | us | franstontime | OS | 2 | OS | 2 | OS | 2 | ws [CKe Soup timeorPowerBonm Bat jt | 9 | — | 8] — | 3 |— ||

BASE VALUES FOR CLOCK COUNT/LATENCY MB81F161622B | MB81F161622B | MB81F161622B Parameter Notes 75 “102 710 RAS Active Time | tas | 45 | 100000] 50 | 100000 100000] ns | CLOCK COUNT FORMULA Note10 Base Value Clock Period (Round off a whole number)

(The latency values on these parameters are fixed regardless of clock period.) Parameter Notes | Symbot |MB81F161622B | MB81F 1616228 | MB81F161622B -75 -102 -10 KE to Clack Disable a DQM to Input Data Delay [bo | ooo PT cto | Last Output to Write Command Delay ee ee Write Command to Input Precharge to Outputin [CL=2 | how | 2 | 2 | cycle Burst Stop Command to Notes: *1. Ico depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; the specified values are obtained with the output open and no termination register. *2. Aninitial pause (DESL or NOP) of 200 us is required after power-up followed by a minimum of eight Auto-refresh cycles. *3. AC characteristics assume tr = 1 ns and 50 pF of capacitive load. *4. 1.4V is the reference level for measuring timing of input signals. Transition times are measured between Vi (min) and Vi. (max). *5. Assumes tron is satisfied. *6. tcalso specifies the access time at burst mode. *7. Specified where output buffer is no longer driven. *8. Actual clock count of tac (Inc) will be sum of clock count of tras (Inxs) and tae (InP). *9. Operation within the taco (min) ensures that access time is determined by taco(min) + tac(max); if taco is greater than the specified taco (min), access time is determined by tr. “10. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number).

Fig. 4— EXAMPLE OF AC TEST LOAD CIRCUIT Ri=50Q Output Tw 14V T C.=50 pF LVTTL Note: AC characteristics are measured in this condition. This load circuits are not applicable for Vou and Vou.

Fig. 5 - TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME tex _ r— YX 1.4V cLK 08V tsi ti Addr. & Data) 08V tac tuz 24V | ey 0.4V Note: Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL. Fig. 6 — TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT CLK Don't Care ) / \\ toxse (min) as CKE Command Don't Care ACTV ») A L\\ L\\ L\\

Fig. 7— TIMING DIAGRAM, PULSE WIDTH CLK thc, tar tras, trop, twa, Input trem tort, toaL, tasc, taro, toxse WAVAV/ YVY VYY YY (Control) (x) Command (X) (x) Command () D/V/\\ DAV/\\ D//A\\ D/\\ Note: These parameter are a limit value of the rising edge of the clock from one command input to next input. tcxse is the latency value from the rising edge of CKE. Measurement reference voltage is 1.4 V. Fig. 8— TIMING DIAGRAM, ACCESS TIME RAS trop teac TAS (CAS Latency — 1) x tex WWW Q(Valid) ray Movie) Note: trac, teac are a reference value. Data can be obtained after both toac = (CL — 1) x tex and tac are satisfied.

@ MODE REGISTER TABLE MODE REGISTER SET [Teta [= [a= [e[e[e [a [a] ® [ooness Op- MODE [ope fae]efef~ oa fet om [rain CAS Latency Burst Length Ae A Ao ° ° ' Reserved 0 0 0 1 Reserved ° 1 ° 2 ) oO 1 2 2 ° 1 ' 3 0 1 oO 4 4 1 te) 0 Reserved 0 1 1 8 8 1 0 1 Reserved 1 0 0 Reserved Reserved 1 1 0 Reserved 1 0 1 Reserved Reserved 1 1 1 Reserved 1 1 0 Reserved Reserved 1 1 1 Full Column Reserved Burst Read & Burst Write Sequential (Wrap round, Binary-up) Burst Read & Single Write Interleave (Wrap round, Binary-up) Notes: 1. When As = 1, burst length at Write is always one regardless of BL value. 2. BL=1 and Full Column are not applicable to the interleave mode.

TIMING DIAGRAM - 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4) CLK al CLK po. (Internal) ‘ DQ V “2V “2V (Read) Qi h Q2 (No Change) h Q3 (No Change) h De V V V V V Notes: “1. The latency of CKE (Icxe) is one clock. *2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output remain the same data. *3. During the write mode, data at the next clock of CSUS command is ignored. TIMING DIAGRAM - 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT CLK texse ———— en CKE Command Y NOP TY PD(NOP ) Don't Care X nop ¥ nor’ Y ACTV Y i I L\\ a) A \\ L\\ [\\ trer (max) Notes: “1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2, Precharge command can be posted in conjunction with CKE when burst mode is ended at this clock. *3. The ACTV command can be latched after tcxse (min) + 1clock (min). It is should be asserted NOP command in conjunction with CKE.

TIMING DIAGRAM - 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY RAS Icon (1 clock) leco loo loco Address Y ,Row Y VY Column Y Column Yo Column Yo Column Y Column Y [\\__Address_/\\ (Address | Address \\ Address Address (| Address f\\ I i 1 I ! 1 Note: TAS to TAS address delay can be one or more clock period. TIMING DIAGRAM - 4 : DIFFERENT BANK ADDRESS INPUT DELAY leap loso ‘Add Vo Rw Y VY Row Y Column Y Column Y Column Y Column Y ress. Address A Address \\ Address Address Address Address An(BA) \\ Bank 0 | ] Bank 1 \\ Banko / Banki \\ Banko [Bank 1 \\

TIMING DIAGRAM - 5 : DQM-INPUT MASK AND OUTPUT DISABLE (@ BL = 4) CLK DQML-DQMU , (@ Read) DQ V . (oes (ot Ye wee) ae DQML-DQMU (@ Write) Iban (same clock) wr fo J wesc fos fof (@ Write) A | Masked \\ \\ \\___End of burst TIMING DIAGRAM - 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK) oS UW —~ i\\ AN A L\\

TIMING DIAGRAM - 7 : READ INTERRUPTED BY PRECHARGE (Example @ CL = 2, BL = 4) V V pA L\\ — | | V V Command Precharge L\\ L\\ Inon (2 clocks) | L L\\ Ion (2 clocks) L\\ L\\ L\\ A No effect (end of burst) L L\\ A Note: Incase of CL = 2, the Inox is 2 clock. In case of CL = 3, the Inox is 3 clock.

TIMING DIAGRAM - 8 : READ INTERRUPTED BY BURST STOP (Example @ BL = Full Column) (CL =2) A AN lash (2 clocks) AY A\\ A\\ A (CL =3) A A Issh (3 clocks) fo» fo Xo J on fo DQ Ins + fo» fo Xo J on fo Note: The selection of Auto precharge option is ilegal during the full column burst operation except Write command at BURST READ & SINGLE WRITE mode. TIMING DIAGRAM - 9 : WRITE INTERRUPT BY BURST STOP (Example @ CL = 2) X_est_J conmans X Command \\ BST \\ Command \\ Last \\ "Masked" ~~.

TIMING DIAGRAM - 10 : WRITE INTERUPTED BY PRECHARGE (Example @ CL = 3) AY AN At A Ay tot(min) tap(min) ba Yous Vadose /\\_Data-In /. byPRE - Note: The precharge command (PRE) should only be issued after the tor: of final data input, is satisfied. TIMING DIAGRAM - 11 : READ INTERRUPTED BY WRITE (Example @ CL = 3, BL = 4) A\\ AN f A\\ AN DQM | (DQML/DQMU) Note 1 Note 2 Note 3 loaz (2 clocks) , lowo (same clock) V V DQ Data Out Data In Data In Masked pA pA Notes: 1. First DQM makes high-impedance state High-Z between last output and first input data. 2. Second DQM makes internal output data mask to avoid bus contention. 3. Third DON in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.

TIMING DIAGRAM - 12 : WRITE TO READ TIMING (Example @ CL = 3, BL = 4) ou me V A A A A Dam (DQML/DQMU) (CL=1) x tex tac (max) D3 V pa or \\ { at \\ ae /\\ Masked \\ by Read Note: Read command should be issued after twr of final data input is satisfied if read command is applied to the same bank.

TIMING DIAGRAM - 13 : READ WITH AUTO-PRECHARGE (Example @ CL = 2, BL = 2 Applied to same bank) CLK tras (min) I Command ACTV READA NOP or DESL ACTV 2 clocks | (same Value as BL) BL + tae(min) 2 DQM (DQMLDOMU) \\ v Notes: *1. Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length (BL) after READA command is asserted. *2. Next ACTV command should be issued after BL + tae(min) from READA command. TIMING DIAGRAM - 14 : WRITE WITH AUTO-PRECHARGE (Example @ CL = 2, BL = 2 Applied to same bank) tras (min) - pif WOOL BL + ter (min)’® Command ACTV WRITA NOP or DESL ACTV ——_ l DQM (DQ@vLUDAMU) I Notes: *1. Precharge at write with Auto-precharge is started after the tor: from the end of burst. *2.Even if the final data is masked by DQM, the precharge does not start the clock of final data input. *3.Once auto precharge command is asserted, no new command within the same bank can be issued. *4.Auto-precharge command doesn't affect at full column burst operation except Burst Read & Single Write mode. *5.Next command should be issued after BL + tae(min) at CL = 2, BL + 1+ tar(min) at CL = 3 from WRITEA command.

TIMING DIAGRAM - 15 : AUTO-REFRESH TIMING “VY * 7, 5 A L\\ AY A l\\ A AN AY tre (min) tac (min) V V rien) J oorrcwef Jverrcwef — foomrcwef Km I Notes: “1. All banks should be precharged prior to the first Auto-refresh command (REF). *2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. *3. Either NOP or DESL command should be asserted during taro and tac period while Auto-refresh mode. *4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tac from the last REF command. TIMING DIAGRAM - 16 : SELF-REFRESH ENTRY AND EXIT TIMING CLK y ) texse (min) tec(min)"4 CKE ) * V V V ) *3V V command Y noPtY seur Y ) dontoare }nor’?} serFx } nop’s A\\ A AY L\\ L\\ L\\ ) L\\ i Notes: “1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF). *2. The Self-refresh Exit command (SELFX) is latched after tcxsp (min). It is recommended to apply NOP command in conjunction with CKE. It is also recommended to apply minimum of 4 clocks to stabilize external clock prior to SELFX command. *3. Either NOP or DESL command can be used during tac period. *4. CKE should be held High within tac(min) period after toxse

TIMING DIAGRAM - 17 : SELF-REFRESH TIMING (Asynchronous Self-refresh) ' 1 CLK ) I 1 tase texse (min) tac (min) I ! ) ore | | i} 5) | | U 1 y “Vy 72 3 ) V V Command h AREF h NOP or DESL NOP or DESL Hoommand} wh. ‘Any new command cancels Self-refresh Entry the entry of Self-refresh. Entry Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Auto-refresh command (AREF). *2. Either NOP or DESL command can be used during tac period. Applying any command before CKE is brought Low cancenls the entry of Asynchronous Self-refresh. *3. Either NOP or DESL command can be used during tase period. TIMING DIAGRAM - 18 : SELF-REFRESH TIMING (Async. Self-refresh) 1 tase? ouK \\\\= ) ; ! CLKeLow fixed tro (min) I CKE ) | | | | ' 1 V V WV Py ] )y V Command X nop ¥ AREF h NOP or DESL NOP or DESL oommanc\\ Auto-refresh Self-refresh Entry Entry Notes: “1. Precharge command (PRE or PALL) should be issued if any bank is active prior to Auto-refresh command (AREF). *2. Either NOP or DESL command must be maintained. *3. CLK must stop and be kept at Low in order to enter Asynchronous Self-refresh. *4. Either NOP or DESL command can be used during trc period.

TIMING DIAGRAM - 19 : SELF-REFRESH TIMING (Async. Self-refresh Cancellation) ' ' | I teKsP(min) | | ) CKE | | I | tase t 1 ) VVV * V V A A NVA ‘\\ I ) ‘\\ \\ ‘Auto-refresh Entry Notes: “1. Simply by turn CKE = High before tase(min). *2. Next commnad can be issued form 1 clock later when toxsp is satisfied. *3. Either NOP or DESL command can be used. *4. The cancellation of Asynchronous Self-refresh entry can be done if CKE is brought to High prior to tase(min). TIMING DIAGRAM - 20 : MODE REGISTER SET TIMING Command {wns NOP or DESL Y ACTV V A A A ih V V V row VV “ress [= Moores A A A i Note: The Mode Register Set command (MRS) should be only asserted after all banks have been precharged.

@ PACKAGE DIMENSIONS 50-pin plastic TSOP (II) (FPT-50P-MO05) * Resin protrusion. (Each side: 0.15 (.006) Max) @ © ouasarapan HAAARAAAAAARAAA AR AAA RA ! ! 1 i H 0.15(.006) i i f 1 I I i 1 1 \\ 0.25(.010) | 5 ! o.to.004 ! INDEX 4 i MAX 1 PHUUUUORE BOO BUDO BUBOOHEE ! 0.40.016 ' ee 1 MAX ' * 20.95+0.10 1.15+0.05 (Mounting height) {.463+.008) 0.30+0.10 S 0.12510.05 [[eot28008) igfosg.009 8) Cc a (005,002) CTT | rt i} 0.50+0.10 10.7640.20 ‘REF. (STAND OFF) © 1995 FUITSU UMITED FS005S-2041 Dimensions in mm (inches)

Summary

SYNCHRONOUS DYNAMIC RAM

Description

SYNCHRONOUS DYNAMIC RAM

Source title MB81F161622B-10 Datasheet(PDF) - fujitsu semiconductor

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