MB81ES173225-15WFKT-X

MB81ES171625 FUJITSU | Alldatasheet

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DS05-11408-3EFUJITSU SEMICONDUCTOR DATA SHEET MEMORY CMOS SINGLE DATA RATE I/F FCRAM TM (Extended Temp. Version) Consumer/Embedded Application Specific Memory for SiP MB81ES171625/173225-15-X n DESCRIPTION The Fujitsu MB81ES171625/173225 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216 bit memory cells accessible in a 2·512K·16 bit / 2·256K·32 bit format. The MB81ES171625/173225 features a fully synchronous operation referenced to a positive edge clock same as that of SDRAM operation, whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexist- ence. The MB81ES171625/173225 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power consumption and low voltage operation than regular synchronous DRAM (SDRAM). The MB81ES171625/173225 is dedicated for SiP (System in a Package), and ideally suited for various embedded/ consumer applications including digital AVs, and image processing where a large band width and low power consumption memory is needed. * : FCRAM is a trademark of Fujitsu Limited, Japan. n PRODUCT LINEUP Parameter MB81ES171625/173225-15-X Clock Frequency (Max) 66.7 MHz Burst Mode Cycle Time (Min) CL = 13 0 n s CL = 21 5 n s Access Time From Clock (Max) CL = 1 27 ns CL = 2 12 ns XRAS Cycle Time (Min) 75 ns Operating Current (Max) (IDD1 ) 30 mA Power Down Mode Current (Max) (IDD2P ) 1 mA Self-refresh Current (Max) (IDD6 ) 5 mA

FCRAM core with Single Data Rate SDRAM interface
512 K word · 16 bit · 2 bank or 256 K word · 32 bit
2 bank organization
Single +1.8 V Supply –0.15 V tolerance
C M O S I / O i n t e r f a c e
Programmable burst type, burst length, and CAS latency Burst type : Sequential Mode, Interleave Mode Burst length : 1, 2, 4, 8, full column (64 : ·16 bit, 32 : ·32 bit) CAS latency MB81ES171625/173225-15-X CL = 1 (Min tCK = 30 ns, Max 33.3 MHz) CL = 2 (Min tCK = 15 ns, Max 66.7 MHz)
2 K refresh cycles every 4 ms
Auto- and Self-refresh
CKE power down mode
Output Enable and Input Data Mask
Burst Stop command at full column burst
Burst read/write
66.7 MHz Clock frequency

••• MB81ES171625 PA D DSE BME TBST DQC V SS VDD VSS VDD DQ8 DQ9 DQ10 DQ11 VDDQ VSSQ DQ12 DQ13 DQ14 DQ15 DQM A12 A11 BA A 10/AP CLK CKE V SSQ S16 V DDQ XCS XRAS XCAS XWE A DQM0 DQ DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 VDD VSS VDD VSS P AD No.84 PA D N o. 1

••• MB81ES173225 PA D DSE BME TBST DQC DQ DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 VSS VDD VSS VDD DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 DQM2 DQM3 A12 A11 BA A 10/AP CLK CKE VSSQ S32 VDDQ XCS XRAS XCAS XWE A DQM1 DQM0 DQ15 DQ14 DQ13 DQ12 VSSQ VDDQ DQ11 DQ10 DQ9 DQ8 VDD VSS VDD VSS DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 P AD No.84 PA D N o. 1

MB81ES171625
••• MB81ES173225 Symbol Function VDD, VDDQ Supply Voltage VSS, VSSQ Ground DQ 15 to DQ0 Data I/O DQM 1 to DQM0 DQ MASK XWE Write Enable XCAS Column Address Strobe XRAS Row Address Strobe XCS Chip Select BA Bank Select AP Auto Precharge Enable A 12 to A0 Address Input • Row : A12 to A0 • Column : A5 to A0 CKE Clock Enable CLK Clock Input TBST BIST Control BME Burn In Enable DSE Disable DQC BIST Output S16 · 16 Select Symbol Function VDD, VDDQ Supply Voltage VSS, VSSQ Ground DQ 31 to DQ0 Data I/O DQM 3 to DQM0 DQ MASK XWE Write Enable XCAS Column Address Strobe XRAS Row Address Strobe XCS Chip Select BA Bank Select AP Auto Precharge Enable A 12 to A0 Address Input • Row : A12 to A0 • Column : A4 to A0 CKE Clock Enable CLK Clock Input TBST BIST Control BME Burn In Enable DSE Disable DQC BIST Output S32 · 32 Select

••• MB81ES171625 XRAS XCAS XWE A12,A11,A9 to A0, A10/AP I/O VDD VSS/VSSQ VDDQ XRAS XCAS DQM 1 to DQM0 DQ 15 to DQ0 BA XWE CLK BME XCS S16 DSE CKE TBST DQC BANK-1 COMMAND DECODER CLOCK BUFFER ADDRESS BUFFER/ REGISTER BANK SELECT I/O DATA BUFFER/ REGISTER MODE REGISTER FCRAM CORE (8,192 · 64 · 16) COL. ADDR. BANK-0 ROW ADDR. To each block CONTROL SIGNAL LATCH BIST COLUMN ADDRESS COUNTER

••• MB81ES173225 XRAS XCAS XWE A12,A11,A9 to A0, A10/AP I/O VDD VSS/VSSQ VDDQ CLK BME XCS XRAS XCAS S32 XWE DSE CKE DQM 3 to DQM0 DQ 31 to DQ0 BA TBST DQC BANK-1 COMMAND DECODER CLOCK BUFFER ADDRESS BUFFER/ REGISTER BANK SELECT I/O DATA BUFFER/ REGISTER MODE REGISTER FCRAM CORE (8,192 · 32 · 32) COL. ADDR. BANK-0 ROW ADDR. To each block CONTROL SIGNAL LATCH BIST COLUMN ADDRESS COUNTER

Command Truth Table V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n-1 = state at 1 clock cycle before n. *1: NOP and DESL commands have the same effect on the part. At DESL command (XCS = “H”) , all input signal are ignored, but hold the internal state. NOP command (XCS = “L”, XRAS = XCAS = XWE = “H”) is no effect on device operation and the internal state continue. *2: BST command is effective on every Burst Length. (BL = 1, 2, 4, 8, full column) *3: READ, READA, WRIT and WRIT A commands should be issued only after the corresponding bank has been activated (ACTV command) . Refer to “n ST A TE DIAGRAM”. *4: ACTV command should be issued only after the corresponding bank has been precharged (PRE or P ALL command) . *5: Required after power up. Refer to “17. Power-Up- Initialization” in “n FUNCTIONAL DESCRIPTION.” *6: MRS command should be issued only after all banks have been precharged (PRE or P ALL command) and DQ is in High-Z. Refer to “n ST A TE DIAGRAM”. Notes:• All commands assumes no CSUS command on previous rising edge of clock.

All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of the clock.
TBST ,BME and DSE should be held Low.
S16 should be held VIH, and S32 should be held VIL. Function Com- mand CKE XCS XRAS XCAS XWE BA A 10/ AP A 12 to A 6 A5 A 4 to A 0n-1 n Device Deselect *1 DESL H X H X X X X X X X X No Operation *1 NOP H X L H H H X X X X X Burst Stop*2 BST H X L H H L X X X X X Read *3 X16 READ HX L H L H V L X V V X32 H X L H L H V L X X V Read with Auto-precharge *3 X16 READA HX L H L H V H X V V X32 H X L H L H V H X X V Write *3 X16 WRIT HX L H L L V L X V V X32 H X L H L L V L X X V Write with Auto-precharge *3 X16 WRITA HX L H L L V H X V V X32 H X L H L L V H X X V Bank Active *4 ACTV H X L L H H V V V V V Precharge Single Bank *5 PRE H X L L H L V L X X X Precharge All Banks *5 PALL H X L L H L X H X X X Mode Register Set *5, *6 MRS H X L L L L L L V V V

DQM Truth Table V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n-1 = state at 1 clock cycle before n. Notes : • MB81ES171625; DQM 0 and DQM1 control DQ7 to DQ0 and DQ15 to DQ8, respectively.

MB81ES173225; DQM 0, DQM1, DQM2 and DQM3 control DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, and DQ 31 to DQ24, respectively.
All commands assume no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transition.
All inputs are latched on the rising edge of clock.
TBST , BME and DSE should be held Low.
S16 should be held VIH, and S32 should be held VIL. 3. CKE Truth Table V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n-1 = state at 1 clock cycle before n. *1 : CSUS command requires that at least one bank is active. Refer to “n ST A TE DIAGRAM”. *2 : REF and SELF commands should be issued only after all banks have been precharged (PRE or P ALL command). Refer to “n ST A TE DIAGRAM”. *3 : SELF and PD commands should be issued only after the last read data have been appeared on DQ. *4 : CKE should be held High during tREFC . Notes:• TBST ,BME and DSE should be held Low.
S16 should be held VIH, and S32 should be held VIL.
All commands assume no CSUS command on previous rising edge of clock.
All commands assumed to be valid state transition.
All inputs are latched on the rising edge of clock. Function Command CKE DQMn-1 n Data Input/Output Enable ENBL H X L Data Input/Output Disable MASK H X H Current State Function Com- mand CKE XCS XRAS XCAS XWE BA A 10/ AP A 12, A11, A 9 to A0n-1 n Bank Active Clock Suspend Mode Entry *1 CSUS H L X X X X X X X Any (Except Idle) Clock Suspend Continue *1 ¾ LL X X X X X X X Clock Suspend Clock Suspend Mode Exit ¾ LH X X X X X X X Idle Auto-refresh Command * 2 REF H H L L L H X X X Idle Self-refresh Entry * 2, *3 SELF H L L L L H X X X Self Refresh Self-refresh Exit *4 SELFX LH L H H H X X X LH H X X X X X X Idle Power Down Entry * 3 PD HL L H H H X X X HL H X X X X X X Power Down Power Down Exit ¾ LH L H H H X X X LH H X X X X X X

Operation Command Table (Applicable to single bank) (Continued) Current State XCS XRAS XCAS XWE Addr Command Function Idle H X X X X DESL NOP LH HH X N O P L H H L X BST NOP * 1 L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA L L H H BA, RA ACTV Bank Active after t RCD L L H L BA, AP PRE NOP L L H L AP PALL NOP * 1 L L L H X REF/SELF Auto-refresh or Self-refresh * 3, *5 L L L L MODE MRS Mode Register Set (Idle after tRSC ) *3, *6 Bank Active H X X X X DESL NOPLH HH X N O P L H H L X BST L H L H BA, CA, AP READ/READA Begin Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP L L H H BA, RA ACTV Illegal * L L H L BA, AP PRE Precharge L L H L AP PALL Precharge * 1 L L L H X REF/SELF Illegal L L L L MODE MRS Read H X X X X DESL Continue Burst to End ﬁ Bank Active LH HH X N O P L H H L X BST Burst Stop ﬁ Bank Active L H L H BA, CA, AP READ/READA Terminate Burst, New Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Terminate Burst, Start Write; Determine AP *4 L L H H BA, RA ACTV Illegal * 2 L L H L BA, AP PRE Terminate Burst, Precharge ﬁ Idle L L H L AP PALL Terminate Burst, Precharge ﬁ Idle *1 L L L H X REF/SELF Illegal L L L L MODE MRS

(Continued) Current State XCS XRAS XCAS XWE Addr Command Function Write H XXX X D E S L Continue Burst to End ﬁ Bank Active LH H H X N O P L H H L X BST Burst Stop ﬁ Bank Active L H L H BA, CA, AP READ/READA Terminate Burst, Start Read; Determine AP *4 L H L L BA, CA, AP WRIT/WRITA Terminate Burst, New Write; Determine AP L L H H BA, RA ACTV Illegal * 2 L L H L BA, AP PRE Terminate Burst, Precharge ﬁ Idle L L H L AP PALL Terminate Burst, Precharge ﬁ Idle *1 L L L H X REF/SELF Illegal L LLL M O D E M R S Read with Auto- precharge H XXX X D E S L Continue Burst to End ﬁ Precharge ﬁ IdleLH H H X N O P L H H L X BST Illegal L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA L L H H BA, RA ACTV L L H L BA, AP PRE L L H L AP PALL IllegalL L L H X REF/SELF L LLL M O D E M R S Write with Auto- precharge H XXX X D E S L Continue Burst to End ﬁ Precharge ﬁ IdleLH H H X N O P L H H L X BST Illegal L H L H BA, CA, AP READ/READA Illegal * L H L L BA, CA, AP WRIT/WRITA L L H H BA, RA ACTV L L H L BA, AP PRE L L H L AP PALL IllegalL L L H X REF/SELF L LLL M O D E M R S

(Continued) Current State XCS XRAS XCAS XWE Addr Command Function Precharging H X X X X DESL Idle after tRPLH H H X N O P LH H L X B S T L H L H BA, CA, AP READ/READA Illegal * 2L H L L BA, CA, AP WRIT/WRITA LL HHB A , R A A C T V L L H L BA, AP PRE NOP * L L H L AP PALL NOP * 1 LL L H X R E F / S E L F Illegal LL L L M O D E M R S Bank Activating H X X X X DESL Bank Active after tRCD LH H H X N O P L H H L X BST Bank Active after t RCD *1 L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA LL HHB A , R A A C T V L L H L BA, AP PRE L L H L AP PALL IllegalLL L H X R E F / S E L F LL L L M O D E M R S Refreshing H X X X X DESL Idle after t REFC LH H H X N O P LH H L X B S T Illegal LH L X X READ/READA/ WRIT/WRITA LL H X X ACTV/ PRE/PALL LL L X X REF/SELF/ MRS

(Continued) ABBREVIATIONS L = Logic Low, H = Logic High, X = either L or H RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge *1: Entry may affect other bank. *2: Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of that bank. *3: Illegal if any bank is not idle. *4: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to “11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)” and “12. WRITE to READ Timing (Example @ CL = 1, BL = 4)” in “n TIMING DIAGRAMS.” *5: SELF command should be issued only after the last read data has been appeared on DQ. *6: MRS command should be issued only when all DQ are in High-Z. *7: NOP in precharging or idle state. PRE may affect to the bank specified BA and AP . Notes:•TBST ,BME and DSE should be held Low.

S16 should be held V IH, and S32 should be held VIL.
All entries in “4. Operation Command T able” assume that CKE was High during the proceeding clock cycle and the current clock cycle.
Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence will be asserted after power shut down.
All commands assume no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of the clock. Current State XCS XRAS XCAS XWE Addr Command Function Mode Register Setting HXXX X D E S L Idle after t RSC LHH H X N O P L H H L X BST Illegal LHLX X READ/READA/ WRIT/WRITA LLX X X ACTV/PRE/ PALL/REF/SELF/ MRS

Command Truth Table for CKE (Continued) Current State CKE XCS XRAS XCAS XWE Addr Function (n-1) (n) Self- refresh H X X X X X X Invalid LHHX X X X Exit Self-refresh (Self-refresh Recovery ﬁ Idle after tREFC ) LHLH H H X LHLH H L X IllegalLHLH L X X LHL L X X X L L X X X X X Maintain Self-refresh Self- refresh Recovery L X X X X X X Invalid HHHX X X X Idle after t REFC HHL H H H X HHL H H L X IllegalHHL H L X X HHL L X X X H L X X X X X Illegal * 1 Power Down H X X X X X X Invalid LHHX X X X Exit Power Down Mode ﬁ Idle LHLH H H X L L X X X X X Maintain Power Down Mode LHL L X X X IllegalLHLH L X X LHLH H L X All Banks Idle HHHX X X V Refer to “4. Operation Command Table”.HHL H X X V HHL L H X V H H L L L H X Auto-refresh H H L L L L V Refer to “4. Operation Command Table”. HLHX X X X Power Down HLLH H H X HLLH H L X IllegalHLLH L X X HLL L H X X H L L L L H X Self-refresh * H L L L L L X Illegal L X X X X X X Invalid

(Continued) V = Valid, L = Logic Low, H = Logic High, X = either L or H *1: CKE should be held High for tREFC period. *2: SELF command should be issued only after the last data has been appeared on DQ. Notes:• TBST ,BME and DSE should be held Low.

S16 should be held VIH, and S32 should be held VIL.
All entries in “COMMAND TRUTH T ABLE FOR CKE” are specified at CKE (n) state and CKE input from CKE (n-1) to CKE (n) state must satisfy the corresponding setup and hold time for CKE. Current State CKE XCS XRAS XCAS XWE Addr Function (n-1) (n) Bank Active Bank Activating Read/Write H H X X X X X Refer to “4. Operation Command Table”. H L X X X X X Begin Clock Suspend next cycle LXX X X X X Invalid Clock Suspend HXX X X X X L H X X X X X Exit Clock Suspend next cycle L L X X X X X Maintain Clock Suspend Any State Other Than Listed Above L X X X X X X Invalid H H X X X X X Refer to “4. Operation Command Table”. H L X X X X X Illegal

SDR I/F FCRAM Basic Function Three major differences between SDR I/F FCRAMs and conventional DRAMs are : synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. SDR I/F FCRAM uses a clock input for synchroni- zation, while DRAM is basically asynchronous memory although it has been using two clocks, XRAS and XCAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDR I/F FCRAM is determined by commands and all operations are referenced to a rising edge of a clock. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to configure SDR I/F FCRAM operation and function into desired system conditions. “n MODE REGISTER T ABLE” shows how SDR I/F FCRAM can be configured for system requirements by mode register programming. The program to the mode resister should be excuted after all banks are precharged. 2. FCRAM TM MB81ES171625/173225 utilizes FCRAM core technology. FCRAM is an acronym for Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs. 3. Clock (CLK) and Clock Enable (CKE) All input and output signals of SDR I/F FCRAM use register type buffers. CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a rising edge of CLK. All outputs are validated by a rising edge of CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged) , the Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current. 4. Chip Select (XCS) XCS enables all command inputs, XRAS, XCAS, XWE and address inputs. When XCS is High, command signals are negated but internal operations such as a burst cycle will not be suspended. If such a control isn’t needed, XCS can be tied to ground level. 5. Command Input (XRAS , XCAS and XWE) Unlike a conventional DRAM, XRAS, XCAS and XWE do not directly imply SDR I/F FCRAM operations, such as Row address strobe by XRAS. Instead, each combination of XRAS, XCAS, and XWE input in conjunction with XCS input at the rising edge of the CLK determines SDR I/F FCRAM operations. Refer to “n FUNCTIONAL TRUTH T ABLE.” 6. Address Input (A12 to A0) Address input selects an arbitrary location of each memory cell matrix, 524,288 (·16 bit) or 262,144 (·32 bit) . A total of 19 ( · 16 bit) or 18 ( · 32 bit) address input signals are required to decode 13 bit Row addresses and 6 bit (·16 bit) or 5 bit (·32 bit) column addresses matrix. SDR I/F FCRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV) , 13 bit Row addresses are initially latched and the remainder of 6 bit ( · 16 bit) or 5 bit ( · 32 bit) Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or a Write command (WRIT or WRIT A) . A 10 selects READ or READA, WRIT or WRITA and PRE or PALL.

Bank Select (BA) This SDR I/F FCRAM has two banks. Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT or WRIT A) , and precharge commands (PRE or P ALL) . 8. Data Inputs and Outputs (DQ15 to DQ0/DQ31 to DQ0) Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input : t RAC ; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.) tCAC ; from the read command when tRCD is greater than tRCD (Min) at CL = 1. tAC ; from the rising edge of clock after tRAC and tCAC . The polarity of the output data is identical to that of input data. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH ) . Refer to “n AC CHARACTERISTICS”. 9. Data I/O Mask (DQM1 to DQM0/DQM 3 to DQM0) DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when DQM = High is latched by a clock, input is masked at the same clock and output will be masked at CL later while internal burst counter will increment by one or will go to the next stage depending on the burst type. 10. Burst Mode Operation The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatically strobing column address. Access time and cycle time of Burst mode is specified as t CAC /tAC and tCK , respectively. The internal column address counter operation is determined by a mode register which defines burst type and the burst count length of 1, 2, 4, 8 bits of boundary or full column. In order to terminate or move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required : (1) Burst Type The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the least significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A 0 through A2. If the first access of column address is even (0) , the next address will be odd (1) , or vice-versa. (2) Burst Mode Termination and Method of Next Stage Set Current Stage Next Stage Method (Assert the following command) Burst Read Burst Read Read Command Burst Read Burst Write 1st Step Mask Command (Normally 3 clock cycles) 2nd Step Write Command after lOWD Burst Write Burst Write Write Command Burst Write Burst Read Read Command Burst Read Precharge Precharge Command Burst Write Precharge Precharge Command

(3) Counter Operation of Sequential Mode and lnterleave Mode 11. Full Column Burst and Burst Stop Command (BST) The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address, then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read (READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge option is illegal during the full column burst operation. BST command is applicable to terminate the burst operation. If BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When a read mode is interrupted by BST command, the output will be in High-Z. For the detailed rule, please refer to “8. Read Interrupted by Burst Stop (Example @ BL = Full Column)” in “n TIMING DIAGRAMS.” When a write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored. 12. Precharge and Precharge Option (PRE, PALL) SDR I/F FCRAM memory core is the same as a conventional DRAM’s, requiring precharge and refresh opera- tions. Precharge rewrites the bit line and reset the internal Row address line and is executed by the Precharge command (PRE) . With the Precharge command, SDR I/F FCRAM will automatically be in standby state after precharge time (t RP ) . The precharged bank is selected by combination of AP and BA when the Precharge command is asserted. If AP = High, all banks are precharged regardless of BA (P ALL) . If AP = Low, a bank to be selected by BA is precharged (PRE) . The auto-precharge enters precharge mode at the end of burst mode of read or write without the Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to “n FUNCTIONAL TRUTH T ABLE.” Burst Length Starting Column Address Sequential Mode Interleave Mode A

2 A 1 A 0

X00 0 - 1 - 2 - 30 - 1 - 2 - 3 X01 1 - 2 - 3 - 01 - 0 - 3 - 2 X10 2 - 3 - 0 - 12 - 3 - 0 - 1 X11 3 - 0 - 1 - 23 - 2 - 1 - 0 000 0 - 1 - 2 - 3 - 4 - 5 - 6 - 70 - 1 - 2 - 3 - 4 - 5 - 6 - 7 001 1 - 2 - 3 - 4 - 5 - 6 - 7 - 01 - 0 - 3 - 2 - 5 - 4 - 7 - 6 010 2 - 3 - 4 - 5 - 6 - 7 - 0 - 12 - 3 - 0 - 1 - 6 - 7 - 4 - 5 011 3 - 4 - 5 - 6 - 7 - 0 - 1 - 23 - 2 - 1 - 0 - 7 - 6 - 5 - 4 100 4 - 5 - 6 - 7 - 0 - 1 - 2 - 34 - 5 - 6 - 7 - 0 - 1 - 2 - 3 101 5 - 6 - 7 - 0 - 1 - 2 - 3 - 45 - 4 - 7 - 6 - 1 - 0 - 3 - 2 110 6 - 7 - 0 - 1 - 2 - 3 - 4 - 56 - 7 - 4 - 5 - 2 - 3 - 0 - 1 111 7 - 0 - 1 - 2 - 3 - 4 - 5 - 67 - 6 - 5 - 4 - 3 - 2 - 1 - 0

Auto-Refresh (REF) Auto-refresh uses the internal refresh address counter. SDR I/F FCRAM Auto-refresh command (REF) generates the Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 1.95 ms or a total 2048 refresh commands within a 4 ms period. 14. Self-Refresh Entry (SELF) Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh function until cancelled by SELFX. Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF) . Once SDR I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level state) and outputs will be in High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF command should be issued only after the last read data has been appeared on DQ. Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1 ms prior to the self-refresh mode entry. 15. Self-Refresh Exit (SELFX) T o exit the Self-refresh mode, apply minimum tSI after CKE brought high, and then the No operation command (NOP) or the Deselect command (DESL) should be asserted within one tREFC period. CKE should be held High within one tREFC period after tSI. Refer to “16. Self-Refresh Entry and Exit Timing” in “n TIMING DIAGRAMS” for the detail. It is recommended to assert an Auto-refresh command just after the tREFC period to avoid the violation of refresh period. Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1 ms after the Self-refresh exit. 16. Mode Register Set (MRS) The mode register of SDR I/F FCRAM provides a variety of operations. The register consists of 3 operation fields; Burst Length, Burst T ype, and CAS latency. Refer to “n MODE REGISTER T ABLE.” The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power) . MRS command should be issued only when DQ is in High-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of SDR I/F FCRAM. Refer to “17. Power-Up Initialization”. 17. Power-Up Initialization SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply the power and start the clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 500 ms. 3. Precharge all banks by Precharge (PRE) or Precharge All command (P ALL) . 4. Assert minimum of 2 Auto-refresh commands (REF) . 5. Program the mode register by Mode Register Set command (MRS) . In addition, it is recommended that DQM and CKE track V DD to insure that output is in High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh commands (REF) . It is possible to excute 5 before 4.

n STATE DIAGRAM (Simplified for Single BANK Operation State Diagram) MODE REGISTER SET SELF REFRESHIDLE READ SUSPEND BANK ACTIVE AUTO REFRESH POWER DOWN BANK ACTIVE SUSPEND WRITEWRITE SUSPEND POWER ON PRECHARGE READ WRITE WITH AUTO PRECHARGE READ WITH AUTO PRECHARGE WRIT READ READWRIT BST BST MRS SELF SELFX REF ACTV CKE CKE\\(CSUS) CKE READ WRIT READA WRIT A READA CKE WRIT A PRE or P ALL PRE or PA L L POWER APPLIED DEFINITION OF ALLOWS Manual Input Automatic Sequence WRIT A READA PRE or PA L L PRE or PA L L CKE\\(PD) READ SUSPENDCKE WRITE SUSPEND CKE CKE\\(CSUS) CKE\\(CSUS) CKE\\(CSUS) CKE\\(CSUS) Note: CKE\\ means CKE goes Low-level from High-level. CKE

n BANK OPERATION COMMAND TABLE

••• Minimum Clock Latency or Delay Time for Single Bank Operation *1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: Assume t RAS (Min) is satisfied. *4: Assume no I/O conflict. *5: Assume the last data has been appeared on DQ. Second command (same bank) MRS ACTV READ READA WRIT WRITA PRE PALL REF SELF BST First command MRS tRSC tRSC tRSC tRSC tRSC tRSC tRSC ACTV tRCD tRCD tRCD tRCD tRAS tRAS 1 READ 11 1 1 READA *1, *2 BL + tRP BL + tRP BL + tRP BL + tRP BL + tRP BL + tRP BL + tRP WRIT tWR tWR 11 tDPL tDPL 1 WRITA *1, *2 BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL PRE *1, *2 tRP tRP 1 tRP *1, *5 tRP 1 PALL tRP tRP 11 t RP tRP 1 REF tREFC tREFC tREFC tREFC tREFC tREFC tREFC SELFX tREFC tREFC tREFC tREFC tREFC tREFC tREFC Illegal Command.

••• Minimum Clock Latency or Delay Time for Multi Bank Operation *1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: tRRD (Min) of other bank (the second command will be asserted) is satisfied. *4: Assume other bank is in active, read or write state. *5: Assume tRAS (Min) is satisfied. *6: Assume other banks are not in READA/WRIT A state. *7: Assume the last data has been appeared on DQ. *8: Assume no I/O conflict. Second command (other bank) MRS ACTV READ READA WRIT WRITA PRE PALL REF SELF BST First command MRS tRSC tRSC tRSC tRSC tRSC tRSC tRSC ACTV *1 tRRD *5, *6 tRAS READ *1, *3 1 11 *8 1 1 READA *1, *2 BL + tRP *1, *3 *5, *8 *5, *8 BL + tRP BL + tRP BL + tRP BL + tRP WRIT *1, *3 1 1111 *5 tDPL WRITA *1, *2 BL-1 + tDAL *1, *3 BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL BL-1 + tDAL PRE *1, *2 tRP *1, *3 *5, *6 tRP *1, *7 tRP PALL *2 tRP tRP 11 t RP tRP REF tREFC tREFC tREFC tREFC tREFC tREFC tREFC SELFX tREFC tREFC tREFC tREFC tREFC tREFC tREFC Illegal Command.

BA A 12 A 11 A 10 A 9 A 8*2 A 7*2 A 6 A 5 A 4 A 3 A 2 A 1 A 0 ADDRESS 0 or 1 0 0 CL BT BL MODE REGISTER *1: BL = 1 and Full Column are not applicable to the interleave mode. *2: A7 and A8 = 1 are reserved for vender test. A 6 A 5 A 4 CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved A 2 A 1 A 0 Burst Length Reserved Reserved Reserved Full Column Reserved Reserved Reserved Reserved Reserved A 3 Burst Type Sequential Interleave

n ABSOLUTE MAXIMUM RATINGS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. n RECOMMENDED OPERATING CONDITIONS (Referenced to Vss) *1 : All voltages are referenced to VSS . *4 : The maximum junction temperature of FCRAM (Tj) should not be more than +125 °C. Tj is represented by the power consumption of FCRAM (PFCRAM ) and Logic LSI(PD ),the thermal resistance of the package(qja),and the maximum ambient temperature of the SiP(TAMax). TjM ax[ °C] = TAMax[ °C] + qja[ °C/W] · S PMax[W] S PM ax[W] = PFCRA M + PD WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min Max Voltage of VCC Supply Relative to VSS VDD , VDDQ -0.5 +3.0 V Voltage at Any Pin Relative to VSS VIN, VOUT -0.5 +3.0 V Short Circuit Output Current I OUT -13 +13 mA Storage Temperature T STG -55 +125 °C Parameter Symbol Value Unit Min Typ Max Supply Voltage*1 VDD , VDDQ 1.65 1.8 1.95 V VSS , VSSQ 000V Input High Voltage *2 VIH VDDQ -0.4 ¾ VDDQ + 0.3 V Input Low Voltage *3 VIL -0.3 ¾ 0.4 V Ambient Temperature T A -40 ¾+ 85 °C Junction Temperature*4 Tj -40 ¾+ 125 °C 3.0 V VIH VIL VIH (Min) -1.5 V VIL VIH VIL (Max)50% of pulse amplitude Pulse width £ 5 ns 50% of pulse amplitude Pulse width £ 5 ns *3 : Undershoot limit: VIL (Min) = VSS –1.5 V for pulse width £ 5 ns acceptable, pulse width measured at 50% of pulse amplitude. *2 : Overshoot limit: VIH (Max) =

3.0 V for pulse width £ 5 ns acceptable,

pulse width measured at 50% of pulse amplitude.

(f = 1 MHz, TA = + 25 °C) Parameter Symbol Value Unit Min Typ Max Input Capacitance, Except for CLK C IN1 2.0 ¾ 5.0 pF Input Capacitance for CLK C IN2 2.0 ¾ 5.0 pF I/O Capacitance C I/O 2.0 ¾ 5.0 pF

(At recommended operating conditions unless otherwise noted.) (Continued) Parameter Symbol Condition Value Unit Min Max Output High Voltage V OH(DC) IOH = -2 mA V DDQ -0.2 ¾ V Output Low Voltage V OL(DC) IOL = 2 mA ¾ 0.2 V Input Leakage Current (Any Input) I LI

0 V £ VIN £ VDDQ ;

test = 0 V -55 mA Output Leakage Current I LO (Average Power Supply Current) IDD1 Burst Length = 1, tRC = Min for BL = 1, tCK = Min, One bank active, Output pin open, Addresses changed up to one time during t CK (Min),

0 V £ VIN £ VIL Max,

VIH Min £ VIN £ VDDQ ¾ 30 mA Power Supply Current (Precharge Standby Current) IDD2P CKE = 0 V, All banks idle, tCK = Min, Power down mode, V IL = 0 V, VIH = VDDQ ¾ 1m A IDD2PS CKE = 0 V, All banks idle, CLK = VDDQ or 0 V, Power down mode, V IL = 0 V, VIH = VDDQ ¾ 1m A IDD2N CKE = VDDQ , All banks idle, tCK = Min, NOP command only, Input signals (except to CMD) are changed one time during 30 ns, V IL= 0 V, VIH = VDDQ ¾ 4m A IDD2NS CKE = VDDQ , All banks idle, CLK = V DDQ or 0 V, Input signal are stable, V IL= 0 V, VIH = VDDQ ¾ 1m A

(Continued) Notes:• All voltages are referenced to VSS and VSSQ.

DC characteristics are measured after following “17. Power-Up Initialization” procedure in “n FUNCTIONAL DESCRIPTION”.
IDD depends on output termination, load conditions, clock rate, number of address and/or command change within certain period. The specified values are obtained with the output open. Parameter Symbol Condition Value Unit Min Max Power Supply Current (Active Standby Current) IDD3P CKE = 0 V, Any bank active, tCK = Min, VIL = 0 V, VIH = VDDQ ¾ 1m A IDD3PS CKE = 0 V, Any bank active, CLK = V DDQ or 0 V, VIL = 0 V, VIH = VDDQ ¾ 1m A IDD3N CKE = VDDQ , Any bank active, t CK = Min, NOP command only, Input signals (except to CMD) are changed one time during 30 ns, V IL = 0 V, VIH = VDDQ ¾ 10 mA IDD3NS CKE = VDDQ , Any bank active, CLK = V DDQ or 0 V, Input signals are stable, V IL = 0 V, VIH = VDDQ ¾ 1m A Average Power Supply Current (Burst mode Current) IDD4 tCK = Min, Burst Length = 4, Output pin open, All-banks active, Gapless data,

0 V £ V

IN £ VIL Max, VIH Min £ VIN £ VDDQ ¾ 40 mA Average Power Supply Current (Refresh Current #1) IDD5 Auto-refresh; tCK = Min, tREFC = Min, VIH Min £ VIN £ VDDQ ¾ 73 mA Average Power Supply Current (Refresh Current #2) IDD6 Self-refresh; CLK = VDDQ or 0 V, CKE= 0 V, IN £ VIL Max, VIH Min £ VIN £ VDDQ ¾ 5m A

(1) Basic AC Characteristics (At recommended operating conditions unless otherwise noted.) *1: If input signal transition time (tT) is longer than 1 ns; [ (tT / 2) - 0.5] ns should be added to tCAC (Max) , tAC (Max) , tHZ (Max) and tSI (Min) spec values, [ (tT / 2) - 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) and tOH (Min) spec values, and (tT - 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values. *2: This value is for reference only. *3: Measured under AC test load circuit shown in “ (5) Measurement Condition of AC Characteristics (Load Circuit) ”. *4: t AC also specifies the access time at burst mode except for first access at CL = 1. *5: Specified where output buffer is no longer driven. Notes:• AC characteristics are measured after following “17. Power-Up Initialization” procedure in “n FUNCTIONAL DESCRIPTION”.

AC characteristics assume tT = 1 ns ,10 pF of capacitive and 50 W of terminated load. Refer to “ (5) Measurement Condition of AC Characteristics (Load Circuit) ”
0.9 V is the reference level for measuring timing of input/output signals.
T ransition times are measured between VIH (Min) and VIL (Max) . Refer to “(6) Setup, Hold and Delay Time”. Parameter Symbol Value Unit Min Max Clock Period CL = 1t CK1 30 1000 ns CL = 2t CK2 15 ns Clock High Time *1 tCH 6 ¾ ns Clock Low Time *1 tCL 6 ¾ ns Input Setup Time *1 tSI 3 ¾ ns Input Hold Time except for CKE *1 tHI 2 ¾ ns XRAS Access Time *2 tRAC ¾ 57 ns XCAS Access Time *1, *3 tCAC ¾ 27 ns Access Time from Clock (tCK = Min) *1, *3, *4 CL = 1t AC1 ¾ 27 ns CL = 2t AC2 ¾ 12 ns Output in Low-Z *1 tLZ 0 ¾ ns Output in High-Z *1, *5 CL = 1t HZ1 2.5 10 ns CL = 2t HZ2 2.5 10 ns Output Hold Time *1, *3 tOH 2.5 ¾ ns Time between Auto-Refresh command interval *2 tREFI ¾ 1.95 ms Time between Refresh t REF ¾ 4m s Transition Time t T 0.5 5 ns

(2) Base Values for Clock Count/Latency *: tRC (Min) is not sum of tRAS (Min) and tRP (Min) . Actual clock count of tRC (lRC ) must satisfy tRC (Min) , tRAS (Min) and tRP (Min) . (3) Clock Count Formula Note: All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula : clock count equals base value divided by clock period (round up to a whole number) . Parameter Symbol Value Unit Min Max XRAS Cycle Time * t RC 75 ¾ ns XRAS Precharge Time t RP 30 ¾ ns XRAS Active Time t RAS 45 110000 ns XRAS to XCAS Delay Time t RCD 30 ¾ ns Write Recovery Time t WR 15 ¾ ns XRAS to XRAS Bank Active Delay Time t RRD 15 ¾ ns Data-in to Precharge Lead Time t DPL 15 ¾ ns Data-in to Active/ Refresh Command Period t DAL 1cyc+ tRP ¾ ns Refresh Cycle Time t REFC 75 ¾ ns Mode Resister Set Cycle Time t RSC 45 ¾ ns Clock ‡ Base Value Clock Period (Round up to a whole number)

(4) Latency - Fixed Values (The latency values on these parameters are fixed regardless of clock period.) (5) Measurement Condition of AC Characteristics (Load Circuit) Parameter Symbol Value Unit CKE to Clock Disable CKE 1 cycle DQM to Output in High-Z CL = 1 DQZ1 1 cycle CL = 2 DQZ2 2 cycle DQM to Input Data Delay DQD 0 cycle Last Output to Write Command Delay OWD 2 cycle Write Command to Input Data Delay DWD 0 cycle Precharge to Output in High-Z Delay CL = 1 ROH1 1 cycle CL = 2 ROH2 2 cycle Burst Stop Command to Output in High-Z Delay CL = 1 BSH1 1 cycle CL = 2 BSH2 2 cycle XCAS to XCAS Delay (Min) CCD 1 cycle XCAS Bank Delay (Min) CBD 1 cycle R 1 = 50 W 0.9 V C L = 10 pF Output

(6) Setup, Hold and Delay Time (7) Delay Time for Power Down Exit VOH VOL 0.9 V 0.9 V 1.4 V 1.4 V 0.4 V 0.4 V 0.9 V tCK tCH tSI tHI tCAC , tAC1 or tAC2 tLZ tHZ1 or tHZ2 tOH tCL CLK Output Input (Control, Addr. & Data) VALID VALID Notes:• Reference level of input/output signal is 0.9 V .

Access time is measured at 0.9 V .
AC characteristics are also measured in this condition. CLK CKE Command tSI 1 clock (Min) NOP ACTV H or L H or L

(8) Pulse Width (9) Access Time tRC , tRP , tRAS , tRCD , tWR , tREFI, tREFC , tDPL , tDAL , tRSC , tRRD CLK Input (Control) COMMAND COMMAND Notes : • These parameters are a limit value of the rising edge of the clock from one command input to the next input.

Measurement reference voltage is 0.9 V . : INVALID CLK XRAS XCAS DQ (Output) tAC tRCD tRAC tAC tAC 1 clock at CL = 2 Q (Valid) Q (Valid) Q (Valid) tCAC

Clock Enable - READ and WRITE Suspend (@ BL = 4) 2. Clock Enable - Power Down Entry and Exit CKE (1 clock) CKE (1 clock) CLK CKE CLK (Internal) DQ (Read) DQ (Write) D1 D2 NOT WRITTEN NOT WRITTEN D3 D4 Q1 Q2 (NO CHANGE) (NO CHANGE) Q3 Q4 *1 *1 *2 *2 *3*3 tSI tHI tSI tHI tSI tHI *1: The latency of CKE (CKE ) is one clock. *2: During the read mode, burst counter will not be increased/decreased at the next clock of CSUS command. Output data remains the same data. *3: During the write mode, data at the next clock of CSUS command is ignored. CSUS command CSUS command CLK CKE Command tSI 1 clock (Min) tREF (Max) NOP PD (NOP) H or L NOP ACTV *3*2*1 *1: The Precharge command (PRE or P ALL) should be asserted if any bank is active and in the burst mode. *2: The NOP command should be asserted in conjunction with CKE. *3: The ACTV command can be latched after tSI + 1 clock (Min) .

Column Address to Column Address Input Delay 4. Different Bank Address Input Delay CLK XRAS XCAS Address tRCD (Min) CCDCCD CCD (1 clock) ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS CCD Note : XCAS to XCAS delay (CCD ) can be one or more clock period. Address CLK XRAS XCAS BA tRCD (Min) or more tRCD (Min) tRRD (Min) CBD (1 clock) CBD Bank 1Bank 0Bank 1Bank 1 Bank 0Bank 0 ROW ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS Note : XCAS Bank delay (CBD ) can be one or more clock period.

DQM - Input Mask and Output Disable (@ CL ==== 2, BL ==== 4) 6. Precharge Timing (Applied to the Same Bank) CLK DQM (@ Read) DQ (@ Read) DQM (@ Write) DQ (@ Write) D1 Q1 Q2 DQZ2 D4D3MASKED High-Z End of burst End of burst DQD (same clock) CLK Command ACTV PRE tRAS (Min) Note : PRE means ‘PRE’ or ‘P ALL ’.

READ Interrupted by Precharge (Example @ CL ==== 2, BL ==== 4) High-Z CLK Command Command Command Command DQ DQ DQ DQ PRE ROH2 (2 clocks) No effect (end of burst) Q1 Q2 Q3 Q4 High-Z High-Z PRE PRE PRE ROH2 (2 clocks) Q1 Q2 ROH2 (2 clocks) Q2 Q3Q1 Note : In case of CL = 1, the ROH is 1 clock. In case of CL = 2, the ROH is 2 clocks. PRE means ‘PRE’ or ‘P ALL ’.

READ Interrupted by Burst Stop (Example @ BL ==== Full Column) 9. WRITE Interrupted by Burst Stop (Example @ BL = 2) BST Q nQ n - 2 Q n - 1 BST Q nQ n - 2 Q n - 1 Q n + 1 BSH2 (2 clocks) BSH1 (1 clock) CLK Command (CL = 1) Command (CL = 2) DQ DQ High-Z High-Z BST Command CLK Command DQ LAST D n Masked by BST

WRITE Interrupted by Precharge 11. READ Interrupted by WRITE (Example @ CL ==== 2, BL ==== 4) CLK Command DQ PRE ACTV tDPL (Min) D n - 1 LAST D n MASKED by Precharge tRP (Min) Note : The precharge command (PRE) should be issued only after the tDPL of final data input is satisfied. PRE means ‘PRE’ or ‘P ALL ’. CLK Command DQM DQ READ WRIT DQZ2 (2 clocks) OWD (2 clocks) DWD (same clock) Q 1 Masked D 1 D 2 *1 *2 *3 *1: The First DQM makes high-impedance state (High-Z) between the last output and the first input data. *2: The Second DQM makes internal output data mask to avoid bus contention. *3: The Third DQM in illustrated above also makes internal output data mask. If burst read ends (the final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.

WRITE to READ Timing (Example @ CL ==== 1, BL ==== 4) 13. READ with Auto-Precharge (Example @ CL ==== 2, BL ==== 2 Applied to same bank) CLK Command DQM DQ WRIT READ D1 D2 Masked by READ Q3Q2Q1 tWR (Min) tAC1tAC1tCAC (Max) tAC1 Notes:• READ command should be issued after tWR of the final data input is satisfied.

The write data after READ command is masked by READ command. ACTV CLK Command DQ DQM BL + tRP * ACTVREADA Q1 Q2 NOP or DESL *: The Next ACTV command should be issued after BL + tRP from READA command.

WRITE with Auto-Precharge (Example @ CL ==== 2, BL ==== 2 Applied to same bank) 15. Auto-Refresh Timing ACTV CLK Command DQ DQM tDAL (Min) (BL - 1) + tDAL * ACTVWRITA D1 D2 NOP or DESL *: The Next command should be issued after (BL - 1) + tDAL from WRIT A command. Notes:• If the final data is masked by DQM, the precharge does not start at the clock of the final data input.

Once the auto precharge command is asserted, no new command within the same bank can be issued.
The Auto-precharge command can not be invoked at full column burst operation. REF *1 REFNOP *2 NOP *2 tREFC (Min) t REFC (Min) NOP *2 NOP *2 Command * 3 CLK Command BA H or L BAH or L *1: All banks should be precharged prior to the first Auto-refresh command (REF) . *2: Either NOP or DESL command should be asserted within tREFC period while Auto-refresh mode. *3: Any activation command such as ACTV or MRS commands other than REF command should be asserted after tREFC from the last REF command. Note: Bank select is ignored at the REF command. The refresh address and bank select are selected by the internal refresh counter.

Self-Refresh Entry and Exit Timing 17. Mode Register Set Timing NOP *1 SELF SELFX * 2H or L NOP * 3 Command tSI (Min) tSI tREFC (Min) *4 CLK CKE Command *1: The Precharge command (PRE or P ALL) should be asserted if any bank is active prior to the Self-refresh Entry command (SELF) . *2: The Self-refresh Exit command (SELFX) is latched after tSI. *3: Either NOP or DESL command can be used during tREFC period. *4: CKE should be held high for at least one tREFC period after tSI. Entry Exit ACTVMRS NOP or DESL ROW ADDRESSMODE tRSC (Min) CLK Command Address Note : The Mode Register Set command (MRS) should be asserted only after all banks have been precharged and DQ is in High-Z.

Part number Configuration Shipping form Remarks MB81ES171625-15WFKT -X 512 K word · 16 bit · 2 bank wafer MB81ES173225-15WFKT -X 256 K word · 32 bit · 2 bank wafer

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Summary

SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP

Description