MB81C81A FUJITSU | Alldatasheet

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ao s_aT DATA SHEET —— EE _DATA SHEET > ee 256K Words x 1 Bit High-Speed CMOS Static Random Access Memory 1 ‘The Fujitsu MB81CB1A is a 262,144 words x 1 bi static random access memory fabricated with a CMOS technology. The MB81C81A uses NMOS calls and CMOS RNY peripherals and has 300 mil plastic DIP and SOJ packages. I uses fully static circuitry SS throughout and, therefore, requires no clocks or retrashes to operate, gs ‘The MB81C81A is designed for memory applications where high performance, low RN) cost, large bit storage, and simple interfacing are required. it is compatible with TTL gd logic and requires a single +5 V supply. , * Organization: 262,144 words x 1 bit | * Static operation: no clocks or refresh required PLASTIC PACKAGE ‘© Accosstime: 251s max, (MB81C81A-25) DIP-24P-M03 35 ns max. (MB81C81A-35) ‘Single +5 V power supply +10% tolerance with low current drain: 100 mA max. (Active operation) Kee 55mAmax. (Standby, CMOS level) Ss a 30 mA max. (Standby, TTL level) a ‘* Separate data inputs and outputs ‘© TTL compatible inputs and outputs * Chip selected for simplified memory expansion, automatic power down eerste ‘Electrostatic protection for all inputs and outputs © Standard 24-pin Plastic Packages: Skinny DIP (300 mil) MBB1C81A-xPSK PIN ASSIGNMENT SOU (300 mil) —- MBB1CB1AxPJ TOP VIEW Absolute Maximum Ratings (see Note) ‘ = ; 3 = ye a Cs Ean on = PS =o | 5 Output Voltage on any pin with as C17 185 ai7 respecte GRD any pie Vour 05 1047 |v | a Ce 75 aw r= CO =P [Power Dissipation [Po | to Tw cad a rr Serge Toners Rage Note: Permanent device damage may occur it absolute maximum ratings are exceeded. pus be Functional peraton shoud be restriced i he conditons as detaled inthe operation | may teat emeveag ea te oer ‘sections of this data sheet. Exposure to absolute maximum rating conditions for ex- sd ht rere pecatora be ah ea ecaien tended periods may affect device reliability. erowlaen ace an miu rated voRages hi igh Copyright © 1900 by FUJITSU LIMITED and Fuyesu Microelectronics, Inc. 1-107

Fig. 1 - MB81C81A BLOCK DIAGRAM Ao a a vec 1] Ae SI GND CELL a—_Q J —7.fon, ARRAY M St 256 ROWS $ 1024 COLUMNS a PT As > | a | eur SS reyes cs DoT) AB AQ AlO Att Al2 At3 At4 AIS Al6 AIT DOWN CIRCUIT ‘TRUTH TABLE [es [we [Mode | output_[ Power _] a ad Lu [ow [Read [pour [Active X= Don't Care CAPACITANCE cra-25°0, 1 = 1 mz [Parameter samt Te ex |e Ips Capactaes (VN = OV) [ow fs Te | eecwpatonnves-om | es fT Te [| owwncapacancewour-o [cour [|e Tr 1-108

[Symbol [PinName Symbol PinName id | _AotoAiz [Address input WET SCWito Enable =i [ow [ata pot ve | Power Suppiy avin | [dour [Data Output GND Ground Sd Les Chip Select RECOMMENDED OPERATING CONDITIONS Lt Referenced to GND} a [seers ee [ef ses | * The operating ambient temperature range is guaranteed with transverse airflow exceed 2m/sec. DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) [Parameter [cancion symbot [in [tye [ax [uot | ee oe [ewe [eer [= [P= P| ome [| | p= f= | VIN2VCC-0.2V or VINSO.2V ‘Standby Supply Current Pemonnes [ef | f= f=] [perme eee! [P= P| a ee emer fem fete fT | eume fem f= [ [| "1 A pull-up resistor to Vee on the GS input is required to keep the device deselected; otherwise, power-on current approaches Icc active. *2 -2.0 V Min. for pulse width less than 10 ns. 1-109

  • Input Pulse Levels: 06 VI024V * Input Pulse Rise and Fall Times: 2ns (0.8Vt02.2V) Timing Reterence Levels: Input, VI = 08, VI 22 * Output Load: Fip2 Ri Dour “T Re “Including Scope and Jig capacitance [Jar] Re [ct Parameters Measured _| [soc | 250 | 30 | [Keeani 200 [asa | Sor | AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) ee lee ee [_feoscretm 22 [we [= | [= | | = | A Ces ff = [= fe | [ownistonssnstiowe [em fa | fs | | = | [Lawsecowomaniez [a ts | |= | [= | | Siedeeacrecaornnez | we [eo | * { o | a |» | [cipseosonrowruptne | wv e | {eo ||» | ee *1 WE is high for Read cycle. *2 All Read cycles are determined from the last address transition to the first address: transition of next cycle. "3 Device is continuously selected, CS=VIL, *4 Address valid prior to or coincident with CS transition low. *5 Transition is measured at the point of £500mV from steady state voltage with specified Load Il in Fig. 2. 1-110

READ CYCLE: ADDRESS CONTROLLED *1 3 tro g Ve 1 tAA 10H Previous Data ‘ DATAOUT = Yny Data Valid READ CYCLE:CS CONTROLLED "1 “4 tRC ADDRESS ZZ 4 4 y cS \\ACS- 5 *5 uz tHZ- L\\ZN {PU L tPD- kc --f---- 2 -- 50% 50% isB BX :undotines EZ : dont care "1 WE is high for Read cycle. £2.All Road cycles aro determined from the last address transition to the first address transition of next cycle. *3 Device is continuously selected, CS=ViL_ "4 Address valid prior to or coincident with CS transition low. “5 Transition is measured at the point of +500mV from steady state voltage with specified Load Il in Fig. 2. 1-111

AC CHARACTERISTICS (continues) (Recommended operating conditions unless otherwise noted.) ee de [_Wiecyontme dT wo] = [| = [| » | a [ cipsonaenwewawne | ew [= | |» || = | [ous vanswensarwne [ow | [| * | = | | datatowting Pe Te ee |_wetePuise wean Pwr Pe Pe |_witeRecoveryting Of we Ps A [ ompanciwtonewawie | ow [oe | [|e {| » | [_wietnaiewoupainninz [we [eo | @ | 0 | | = | WRITE CYCLE TIMING DIAGRAM WRITE CYCLE: WE CONTROLLED “1 *2 “3 two tow wR 3s \\\\WN A/LLLL Ewa Aw } 1AS 1we We KN tow 10H wz rows KKKKKKEKK) High-Z XX DATA OUT EX : Undetines Don't Care bal Ser WE must be high during address transitions. a *2. CS goes high simuttanoously with WE high, the output remains in high impedance state. *3 All Write cycles are determined from the last address transition to the first address transition of next cycle. *4 Transition is measured at the point of +500mV from steady state voltage with specified Load Il in Fig. 2. 1-112

$$ SSS WRITE CYCLE TIMING DIAGRAM WRITE CYCLE: CS CONTROLLED "1 *2 we ae woes ZX vs \\ aw 1wR tAS CW. cs twP we AQAA ALLLLLL tow 10H jb owc* igh-Z DATA OUT Hs EX : underines :Don't Care *1 CS or WE must be high during address transitions, "2H CS goes high simultaneously with WE high, the output remains in high impedance state. “3 All Write cycles are determined from the last address transition to the first address transition of next cycle. “4 Transition is measured at the point of +500mV from steady state voltage with specified Load It in Fig. 2. 1-113

24-LEAD PLASTIC SKINNY DUAL IN-LINE PACKAGE (CASE No.: DIP-24P-M03) psx AAAAAAAA AA baswax INDEX i 1 b) 260:,010 300(7.621 >) (680:6.25) ia woex2-FO |_| joy Pur ya aa ea ey ty oS neg | (0.252005) (28.72°938) 24720562 °°) 17214.36)Max 5011.27) MAX 11812,00)M1N -10012.84) osoty? || orss.003 zoids ener tntirnaters) ©1988 FUsITSU LIMITED 0240178.3¢ 1-114

PACKAGE DIMENSIONS (Continued 24-LEAD PLASTIC LEADED CHIP CARRIER (CASE No.: LCC-24P-M02) | | = ‘woe © | Re | asgees, SSS Qt T2720.131 cons min "S603. 97REF “NOM” 14413.66) ax etait ot" part fmm ee OPUAY APD APRERPRAPRY AE wot ~“ A fetes — | L017: 004 +: This dimension includes resin protrusion, (Each side’ 006(0.15IMAX.) (0432010) Perper mutimeters) aes FUsTSU LuTeD coumes.te 1-115