MB81464-12

MB81464-12 FUJITSU | Alldatasheet

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PHO AGT) FUJITSU MICROELECTRONICS 4Y?7E D MM 37497?be 0019311 7 MFNI October 1990 sai FUJITSU le DATA SHEET MB81464-12/-15 MOS 262,144 BIT DYNAMIC RANDOM ACCESS MEMORY Se ee 65,536 x 4 Bits Dynamic Random Access Memory The Fujitsu MB81464 Is a fully decoded, dynamic random access memory organized as 65,536 words by 4 bits. The design Is optimized for high speed, high performance applications such as mainframe memory, buffer memory, peripheral storage, and system memory for microprocessor units where low powar dissipation and a compact layout is required. ‘The mutiplexed row and column address inputs permit the MB81464 to be PLASTIC PACKAGE housed in standard 18-pin DIP and PLCC, or 20-pin ZIP packages. Additionally, the DIP-18P-m03 1 MB81464 offers new functional enhancements that make it more versatile than previous dynamic RAMs. The CAS-before-RAS refresh cycle provides an on-chip Teftesh capability, The MB81464 also features page mode which allows high speed random access of up to 256 bits within the same row. Kee The MB81464 uses silicon gato NMOS and Fujitsu's advanced Triple-layer na Polysilicon process technology. This process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamic PLASTIC PACKAGE circuity is used in the design, including the sense ampifiers, Clock timing Meee moe requirements are non critical, and power supply tolerance is very wide. All inputs are . TTL compatible. © 65,596 x 4 DRAM organization . eh sutrat bias generator © Silicon-gato, Tr NMOS, {for high performance Smeg ets Poly NMOS, singio Allinputs/outputs are TTL compatible . Rag Acoase Tie (ae) © 4 ms/256 refresh cycles 120 ns ma NE eet © Easly write of OE controlled write 150.8 max. (MB 8146416) capacity PLASTIC PACKAGE + Oe Tine (oe) ° epee rs woe ZIP-20P-M01 360s mn. (MB 81468-10) * Road wo capabiiy DIFC -AO': See Poon 22 © On-chip latches for addresses and * ae ax (MS 464-12) . ony ith LPD41254, HME0464, Jasne max, (MB 31ase18) ood Tuas " " PIN ASSIGNMENT ‘© Standard 18-Pin Plastic Packages: ag Se = had © Single +5 V Supply, £10% tolerance Bip (uaa isd eotf> Boos PLCC (MBB1464-XXxi cart] > Dee © Low Power ‘Standard 20-Pin Plastic Package: we soos Sebi moe ug ace 12 and OBESE) mde gg, Be ae eee Bip Be test XC), Nol Seal “Ge vfs Absolute Maximum Ratings po: Ae = [ParamelerTSymbot [Vatu [voit] soe [Votageatary pinroiatwo Ves | VaNour| 16.7 |v | 3 Shon Circuit Output Current ee ee ee Pr rugnment for 2s Seepage 21 Nowe: Permanent davice damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operation Thi device containe circultry 10 protect he Inputs againat fectone of fis data shoot E \\sure to absolute maximum rating conditions for ex- G0 to tigh tate voLageR or Sc ele en Wrath ay see dolce ay pepetesimimrienn caste ‘eorex © 10000 FUITBU UNITED and Fu Mtrouconc, ne. 1-93

FUJITSU MICROELECTRONICS 4?E D MM 3749762 0019312 9 MFMI [ft B23V7 MB81464-12 MB81464-15 Fig. 1 — MB 81464 BLOCK DIAGRAM No | clock we | P | | JF tJ Qt ar~pas * =! TT | oa —_ | ge i or B 262,144 BIT Aa 93 8 STORAGE CELL — As: . —— Vee * ss [ susstRATe CAPACITANCE 17, =28°c) Parameter Symbol Unit Input Capacitance Ao t Ay [oem | = | 7 | oF | |_tpurcassstaner as. caswe oe | Gwe | = | | Data 1/0 Capacitance (DA1 to 004) Cpa f - [| 7 [| » | 1-94

FUJITSU MICROELECTRONICS 4Y7E D MM 3749762 0019313 0 MFMI 7-¥e-2372 MB81464-12 MB81464-15 (Referenced to Vss) Parameter ‘Symbol atin | vec [as | suvnly Voge | so | ss | va [|e [eo fe |v * The device will withstand undershoots to the ~2.0 V level with a maximum pulse width of 20 ns at the ~1.5 V level. DC CHARACTERISTICS {At recommended operating conditions unless otherwise noted.) ; — arameter im [win [tye [max _| OPERATING CURRENT* Me 81464-12 | | Average Power Supply Current STANDBY CURRENT Power Supply Current (RAS = CAS = Vin) REFRESH CURRENT 1° Me 81464-12 Average Power Supply Current (CAS = Vi. RAS cycling; tac = min) MB 8146415 [| |» | ‘Average Power Supply Current loca mA REFRESH CURRENT 2° me 1464-12 | [| ow | Average Power Supply Current tees (CAS-before- RAS; tac = min} MB 81464-15 [fs | INPUT LEAKAGE CURRENT any input (OV < Vy S5.5V, 4.5V < Voc < 5.5V, Ves = OV, ie) all other pins not under test = OV) OUTPUT LEAKAGE CURRENT j nA {Data out 1s disabled, 0 V £ Vour $5.5 V) paw) OUTPUT LEVEL v. Vv Output High Voltage (loys = -5 mA) on OUTPUT LEVEL \\ v ‘Output Low Voltage (Lo. = 4.2 mA) ou * + lee is dependent on output loading and cycle rates. Specified values are obtained with the output open. gc is dependent on input low voltage level Vio, Vio > -0.5 V. 1-95

FUJITSU MICROELECTRONICS 47E D MM 3749?b2 0019314 2 @mrni 7-Ye-2377 MB81464-12 meses AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) SIOIEESS Time between Refresh ee ee Ce [Reon ris enw wee | 2a] Pf [ney ne Cee [trae [05 [ae PrerieircyeeTnw ve ews [Fiminte nema ene ee Tome | oe | [as || | a [asses tow 8S ag tee [fw P| [enon te tenor [to [0] | 0 foe] a [Rasher we w]e | pases Pina [fo = Ls] [ext racogT fermoan te [so [pe] CAS Precharge Time a re betemsore — te t= te ee [row Aten eine van 9 fp Py brow Aten twee Pe [eos atewan Tine [we Pe [Pf [coum arin ae Drewes oy [Reseonmd se ptem [wr fo] TP Read Command Hold Time [RocsmweeT™ alm fe [fe | | o| Wirtommmsriotie wwe [= [sp] [i mance [wer 0 py [wis omnearinewetn [wwe [90 ep [Wis Gmncie Bin Taw WW www [ofp ef 1-96

FUJITSU MICROELECTRONICS 4W?E D MM 3749762 0019315 4 T-¥6-2307 MB81464-12 MB81464-15 o AC CHARACTERISTICS (cont'd) (At recommended operating conditions unless otherwise noted.) i oymbot |_Meeuee2 me eiaesis | arameter mbol nit win [tex [iin Tax | CAS Set Up Time Referenced to RAS (CAS-before-RAS refresh) CAS Hold Time Referenced to RAS (CAS-before-RAS refresh) RAS Precharge to CAS Hold Time ; (Refresh cyctes) Rec CAS Precharge Time (CAS-before-RAS cycles) ns Refresh Counter Test Cycle t BAS Pulse Width | tras 10000 | 395 | 10000 Refresh Counter Test CAS | tor 70: Precharge Time Notes: HB An initial pause of 200us is required after power-up Mil Measured with a load equivalent to 2 TTL loads and followed by any 8 RAS cycles before proper device Pl operation is achieved. In case of using internal refresh HM Operation within the taco (max) limit insures that counter, a minimum of 8 CAS-before-RAS initialization trac (max) en i me taco (ma) is specitied asa cycles instead of 8 RAS cycles are required reference point only; if taco is greater than the speci- Ed AC characteristics assume ty = 5 ns. fied taco (max) limit, then access time is controlled EB V4 (min) and V,, (max) are reference levels for meas- exclusively BY teac. uring timing of input signals. Also, transition times are KE trco (min) = tran (min) + 2ty (ty = 5 ns} + tase (min) measured between Vij (min) and Vi_ (max). GB Either tan OF tron must be satisfied for a read cycle. EB Assumes that taco < taco (max). If taco is greater MD twcs is not restrictive operating parameter. It 1s included ‘than the maximum recommended value shown in this 1n the data sheet as electrical characteristics only. Even if table, taac will be increase by the amount that taco twes © twes(min), the write cycle can be excuted by exceeds the value shown. satistying tew OF tows specification, BB Assumes that taco 2 taco (max). TB Ether tozc oF topo must be satisfied for all cycles. TB. Refresh Counter Test Cycle only. 1-97

FUJITSU MICROELECTRONICS W?E D MM 3749762 0019316 b @BFMNI T-YL-13-/7 MB81464-12 MB81464-15 aS yer ' teas esi. Re Vinn & os wey KN VAY) ry py rooneses 0 BMC ades MEX] SORE YE TE A we Vin Bee ree cad pa You toze toca fae Vt EER igi Bakes te Vin Mian [2 Don't care Write Cycle (Early Write) OE: Don't care os vec BS KN fl / ; Broun Ye $i 2 $$ EG Don't Care 1-98

FUJITSU MICROELECTRONICS 4?E D MM 3749?be 0019317 6 MFMI T-Yo-A3ss7 MB81464-12 MB81464-15 OE Write Cycle tne RAS Vine ——tRAs- Vi ‘ens 5 er View] mee N /7| aponesses Yin BY XT ae PR YE ye Ce e aes twen ayo wer tRWL- vie ‘ We soxe ome ba Vin Ty EE re GNPUT) — v\\,-eese vcr 2—$ {ona woes |_| tcac!) toEeD — ~tnac ta] tozo-—4 cath torn — y eee ar oez" a fo ie eras eae : EB don't care Read-Modify-Write Cycle tae nS vic RAS ve tat ii eas wl is ee ooh a i? tasn| ‘Appresses 1H” BBW, 20". KEE <Ooats. nee eo enenes ee gt ea | Taw WE vie Shae toze wre feu) ei nich 2 ——— oa De Vow: HIGH-Z- ¢ ); HIGH-2" (ureun Yon pre Con! on 1020 a vy. Bees st Rien ER Don't Care Note: 1) When OF is kept high through a cycle, the DO pins are kept high-Z state. 1-99

FUJITSU MICROELECTRONICS 4?E D Ml 3749762 0019316 T MFNI qe 33-17 MB81464-12 MB81464-15 pwns hau ten RAS Vin “Ras Yum tens — L—-tap- bal esi tora tr oS Mine [rica tons: ce iver fo Ryan | FA Ey tase appresses Yi" Xa Moe X soot KEK vie wil \\/ | toes ae: tozey ~toze \\ ‘pee fNpuT) vy r_ 0 ee Oe oe tozoh TOF Typssc yor “hes tOFF Da, Vou iciz——-{ Tare PEHIGH 2X Yarn PHHIGH 24 { Tym pL HIGH 2 (OUTPUT! = You . thee bez a ‘ote =| toe | TOE D toed (FD Don't Care Page Mode Write Cycle (OE=Don't Care) - tors i tap. | tes ter. - tRsH cL tase “| "SAH se) =f] . we Vine (| wou - ba Vou".

2 Don't Care

FUJITSU MICROELECTRONICS 4?E D Ml 3749762 0019319 1 MBFNI 7-V6-P3S7 MB81464-12 MB81464-15 Page Mode OE Write Cycle “Zee Et vooneses "ESSN Sas KEEN Ss Cn if a Te ows vie K Se _— fheun Vam Quaid 2a DEK ee toeo oe Of? toe A. OED. ba Youn teal) ps teac!} ml tac foureun ven —onep een won os / =" oe ee CL Ny Seine a 1D vont care INVALID DATA Note: 1) When OE is kept high through a cycle, the DQ pins are kept high-Z state. 1-101

FUJITSU MICROELECTRONICS 47E D MM 37497?be 0019320 6 FMI 7 Ye-. MB81464-12 I3v2 MB81464-15 Page Mode Read Modify-Write Cycle ARS vor \\ “as tm fers. tRcD_ -=——tprnwe Ty — “1 as os ea a ox Vint cas: teas: teas t 1 as TITY 7 ‘asal - He soonees "SHES 2s KERN os KLE we vu ine tos h tos , tos] wt 7 = oH on oH tren yi HIGH 2G He eH ZG pence 2s he vu ver 2 108 DATA ais BNNs Eh Prk | _| {Frise wore ‘eae Ge or toz9 = “i Losoee = x “i . ee Y/ eee ER don't Care RAS-Only Refresh Cycle (WE, OE=Don't Care) nas mM vue tors, Tear tq» Das tare <4 tore Don't care 1-102

FUJITSU MICROELECTRONICS 4Y?E D MM 3749?be 0019321 T MFT 7-Yo-A3v7 MB81464-12 MB81464-15 CKS-betore-RAS Refresh Cycle NOTE: Addresses, WE, OE = Don’t care var t 1 [| RPC CB don't care Hidden Refresh Cycle a var RAS $=} tras: var ters| AP. tap- “oS aoa d ‘aporesses Vi X actetss QM Souness p et] we Vine Z vm | toes- tape tore ba Yr we oi (INPUT) yc GH EBB Don't caro 1-103

FUJITSU MICROELECTRONICS Y7E D MM 3749762 OOLI2e 1 MBFNT MB81464-12 722397 MB81464-15 Refresh Counter Test Cycle ————trre - f AK Vie RAS Yan~ i tres tre. - l | ADDRESSES 4," {COLUMN ADDRESS } : We Vin “ vim h tose | DH ba Vie teac tOED vy -———"tnac- - ba OW. 7 KOUTPUT) Voy ISH Conap Ghz 20, petocaes toen toez oe Via oe View [0 vont care DESCRIPTION Write Enable. be low after tozo to change the data ‘The read mode or write mode is selected pins from input mode to output mode Address Inputs: with the Write Enable (WE) input. A and then OE must be changed to low A total of sixteen binary input address high on WE selects read mode and low before togp to return the data pins to bits are required to decode parallel 4 selects write mode. The data inputs are input mode. In an early write cycle, bits of 262,144 storage cell locations disebled when the read mode 1s selected. data pins are in input mode regardless within the MB 81464, When WE goes low prior to CAS, data- of the status of OE, Eight row-address bits are established on guts will remain in the high-impedance Oe, Outputs the input pins (Ap through Az) and state allowing a write cycle. . i latched with the Row Address Strobe The three-state output buffers provide (RAS). The eight column address bits Data Pins direct TTL compatibility with a fan out are established on the input pins (Ag Data Inputs; of “ Standard TTL loads, Data out through Ay) and latched with the Data are written during 2 wnite or read- Se ne Same polarity 9s dltain. Me Column Address Strobe (CAS). modify-write cycle. The later falling tau GAS. i hd sere ee aa The row and column address inputs edge of CAS or WE strobes data into the Unt! GAS Is ought low. Mr ans must be stable on or before the falling on-chip data latches. In an early-write S¥CIWr 16 CUNPUN go Acilve Alter edge of RAS and CAS, respectively. cycle, WE is brought low prior to CAS aitefled. The. oa trac and toca sid CAS is internally inhibited (or “gated") and the data is strobed by CAS with a he he outpwrs become ve by RAS to permit triggering of CAS as setup and hold times referenced to CAS. ter t pore ee OE an low, soon as the Row Address Hold Time in a read-modify-write cycle, thus the Tin valid while ‘he Deo ae (tan) specification has been satisfied data will be strobed by WE with setup | @ read operation, either OE or C and the address inputs have been and hold times referenced to WE. returning high brings the outputs into changed from row-addresses to column: In a read-modify-write cycle, OE must t# high impedance state. addresses. 1-104

FUJITSU MICROELECTRONICS 4?E D MM 3749762 0019323 3 MFMI 7-46-2377 MB81464-12 MB81464-15 Output Enable: each of 256 row-addresses with RAS CAS goes to high and goes to low again The OE controls the impedance of the will cause all bits in each row to be re- while RAS is held low, the read and ‘output buffers, In the high state on OE, freshed. write operation are enabled. This is ‘the output buffers are high impedance Further RAS-only refresh results in a shown im the CAS-before-RAS counter state. In the low state on OE, the out- substantial reduction in power dissipa- test cycle timing diagram, A memory put buffers are low impedance state. tion. cell address, consisting of a row address. But in early write cycle, the output but; Gas before. HAS Refresh; (9 bits) and a column address (9 bits), 1 fers sain high impedaec site een i TAS eter AS refreshing avilable on % b8 Sond can be defined a fl is low. In the page mode read cycle, lows: GE can be allowed low through the MB 81464 offers an alternate re: 6A" ROW ADDRESS — All bits are fresh method. If CAS is held low for cycle. In the page mode early write ie Lon stied period (tees) before RAS, defined by the refresh counter. cycle, OE can be allowed high through goo. tg ow, on chip refresh control COLUMN ADDRESS ~ All the bits cut the cycle, In the page mode reed ee oon ee te eee Ag to Az are defined by latching modity-write or delayed write cycle, Cover are enabled, and s snterecl levels on Ag to Az at the second OE must be changed fram low to high Tesch operation takes place falling edge of CAS. with toro. After the refresh operation is per- Suggested CASbefore HAS Counter Page Mode: formed, the refresh address counter is Test Procedure Page Mode operation permits strobing automatically incremented in prepara- The timing, as shown in the CAS-before- the rowaddress into the MB81464 tion for the next CAS:before-RAS RAS Counter Test Cycle, is used for the while maintaining RAS at a low through- _ refresh operation. following operations: out all successive memory operations in 4. 1) Initialize the internal refresh address which the row-address doesn’t change. idden Refresh: counter by using eight CAS-before- ‘ Hidden refresh cycle may take place = Sr Thus the power Cissipated by the nite maintaining latest valid data at, WAS «efresh cycles. falling edge of RAS is saved. Further, ho atau by extending CAS active 2) Throughout the test, use the same access and cycle times are decreased 1,‘ column address. becouse the time normally required to 1) tas gigga, hidden refresh means 3) White “low” to all 256 row address strobe a new row-address 1s eliminated, #2 AAS ‘on the same column address by using CAS-before-RAS refresh and the inter ee a ene Refresh; nal refresh addresses from the counter 4) feng iow" written in step 3) and Refresh of the dynamic memory cells is are used to refresh addresses ie., it Cseck and simultaneously waite accomplished by performing a memory doesn’t need to apply refresh addresses, nigh 40 the same address BY using cycle at each of the 256 row-addresses because CAS is always low when RAS — istornal refresh counter test cycles, (Ao through Ay) at least every four goes to low in the cycle ‘This step is repeated 256 times, with snillisaconds, TAS-before-RAS Refresh Counter Test the addresses being generated by The MBB1464 offeres the following Cvetg: internal refresh address counter. three types of refresh A special timing sequence using CAS: 5) Read “high” written in step 4) and RAS-Only Refresh: before-RAS counter test cycle provides check by using normat read cycle for RAS-only refresh avoids any output a convenient method of verifying the all 256 locations. during refresh because the output buf- functionality of CAS-before-RAS re- 6) Complement the test pattern and fuers are in the high impedance state fresh activated circuitry. After the repeat step 3), 4) and 5) unless CAS is brought low. Strobing CAS-before-RAS refresh operation, if 1-105

FUJITSU MICROELECTRONICS 4?E D MM 3749762 0019324 5 MFNI T- e-A3-17 MB81464-12 MB81464-15 Fig. 2— CURRENT WAVEFORM (Vcc =5.5 V, Ta = 28°C) an iit COCO TTT 0 Mos GuBUGEES=SEUSENN7 SESE URTSAEBUSEEES== ‘Ee -—-GRee eee bee ---Ceee eh eg SSE RS GOERS SSReemeeeSRRRReE SS ESSRRREE BEE EEE EEE CEE CCC LEA CIC KANDEL LAY Meo RES ETN cot CTT pee ee e HITT a A 4 pee emote Pe ee sere es eray ered eiereeece Eo YALE EY A 1-106

FUJITSU MICROELECTRONICS 47E D MM 3749?be2 0019325 7 MFNI MB81464-12 MB81464-15 TYPICAL CHARACTERISTICS CURVES Fig. 3— NORMALIZED ACCESS TIME. Fig. 4 NORMALIZED ACCESS TIME vs, SUPPLY VOLTAGE vs, AMBIENT TEMPERATURE wo w 13 Pier! TT Td : J 9 5M ga | | Tt Tf fol | [| go Mitt et | | ti go4 _ NEI Z.4 ||) | z os No #4 ew Lt | AT et Tl 5 a8 = onl -LU IIT YT PT i Tt Ty = & a0 30 30 <2 029 a 6080100 Voc. SUPPLY VOLTAGE (v) Ta, AMBIENT TEMPERATURE (°C) Fig. 5 - OPERATING CURRENT Fig. 6 — OPERATING CURRENT vs. CYCLE RATE vs. SUPPLY VOLTAGE = a= ase = ase = Vcc = 5:5V EF hte = 230n = sd = 7) PJ tity ett a) & 60} Hoty ey ft tt Q 30) g 50 Coe yt YL ef | pe sy Vit TT sf) eT) | © 10} % a0) pt TTT TTY st | TT Ty 8 8 4 * 2» oa 38 40 36 80 tae, CYCLE RATE (MHz) Vee, SUPPLY VOLTAGE (V) Fig. 7 — OPERATING CURRENT Fig. 8 - STANDBY CURRENT vs. AMBIENT TEMPERATURE vs. SUPPLY VOLTAGE Pa es 6 ise | | | | a dee] TTT 70 8S = 5 ef TT tT eit TTT Ty FA 5 E60 Boa ef | tt TT § | EPP PEE pi a ee g | a4] Tt sf tt tT é 5 a 2 ar) ~ *20 03040608000 35 86 80 Ta, AMBIENT TEMPERATURE (°C) Vec, SUPPLY VOLTAGE (Vv) 1-107

FUJITSU MICROELECTRONICS 47E D MM 3749762 0019326 9 MMFNT MB81464-12 MB81464-15 Cc Fig. 9— STANDBY CURRENT Fig. 10 - REFRESH CURRENT 1 vs, AMBIENT TEMPERATURE vs. CYCLE RATE 5 z “lranae a feel TTT a pecs [ [I | = = 80) ei {itt t pati tt | e 4 Zao} i : ef Ri sof ttt > 4 = 20 [7 elit a fei | j 5 2 Zz 2 & 20) 7 ett itty 7 2Zennn FT TTT Ty | PLE TTT 200 20 4080100 o 1 2. 3 4 6 Ta. AMBIENT TEMPERATURE (°C) Utge, CYCLE RATE (MHz) Fig. 11— REFRESH CURRENT 1 Fig. 12 —PAGE MODE CURRENT vs. SUPPLY VOLTAGE vs. CYCLE RATE i ieee! [TI iT [eccee Ej q|tme= 730 fees 88 ro [litt effi tit i Z ttt tt tt so _ {i tt | a %| PTT Tie P| | Ue $ ee —t_| : I F ee =2 Ppa | | | 3 —— 3 9 sitrr itt | st TT TTT Fig. 13 — PAGE MODE CURRENT Fig. 14 — REFRESH CURRENT 2 vs, CYCLE RATE vs, CYCLE RATE _ ° i face | [| | i fezl | tt | . so} 187 1208 E go) Yeo=56¥ : rfl 1A pftti tt | E A Peet yt S411 A :* p= TY ; i Pf pete i,t [t iJ Titi tt 2 4nnne Litt it sit T TTT 1-108

I FUJITSU MICROELECTRONICS WE D MM 3749762 0019327? O MFM MB81464-12 MB81464-15 Fig. 15 — REFRESH CURRENT 2 Fig. 16 — ADDRESS AND DATA INPUT vs. SUPPLY VOLTAGE VOLTAGE vs. SUPPLY VOLTAGE = 8 < 30 = A= 25 | Py = althe= 2908 4 t ons ro as is Po Fa 60} B20 | te Fait | > be 5 ey g, || tt] Seal fa 55 2 ao) a 251.0 Fa $2 #4 [Er | | iii tt i | = 2 - z PLP | | ati ft | 2 xl Zo 40 50 60 > 4.0 6.0 6.0 Vec: SUPPLY VOLTAGE (V} Voc. SUPPLY VOLTAGE (V) Fig. 17 — ADDRESS AND DATA INPUT Fig. 18 — RAS, CAS, WE AND OF INPUT VOLTAGE vs. AMBIENT TEMPERATURE hw VOLTAGE vs. SUPPLY VOLTAGE < 20 B a0 6 2 = ~ <u 20 Vin (Mia ~w 20 <a] HLET TT | es ey remy | Ft i519 35 109) a= > ~ et] ] ft | F aa z 0 z > 200 20 40 60 80 100 > o 40 5.0 60 T. AMBIENT TEMPERATURE (°C) Voc, SUPPLY VOLTAGE (Vv) Fig. 19 — RAS, CAS, WE AND OE INPUT Fig. 20 — ACCESS TIME mi VOLTAGE vs. AMBIENT TEMPERATURE vs. LOAD CAPACITANCE S30 25 =

7 Tan Be

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: PTL BE TT e4¢tt Lh RE |__| any 4en 351} < LA se g = Ll ile > 1 T > 20 0 20 40 #60 80 100 100 200 300 400 500 600 Ta, AMBIENT TEMPERATURE (°C) Cy, LOAD CAPACITANCE (pF) 1-109

FUJITSU MICROELECTRONICS 47E D M@ 3749762 0019326 2 MMFMI T46-43-/7 MB81464-12 MB81464-15 Fig. 21 — OUTPUT CURRENT Fig. 22 — OUTPUT CURRENT vs. OUTPUT VOLTAGE 150 vs. OUTPUT VOLTAGE - : || # 4 Bl ml | 7eNNEee 3 7 a | é WN Sl fA as \\ ? ZU | BTL PAN TI ra a re er ar Vou. OUTPUT VOLTAGE (V) Vou, OUTPUT VOLTAGE {V) _ Fig, 23 - SUBSTRATE VOLTAGE Fig. 24 - CURRENT WAVEFORM

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ve Fey Ty 28 [7 JT 2 = e AE EL i ee Nia =25°e Ze Toe BloeSsS oe NI 2 Ho] ett) INE 28) V 27 4 —° s| RAS = CAS = Voc or Vj G NEY] |Z foc oF Vin PLT Tiss LAT TT ‘O60 100 180200220300 O80 100 78d 20050300 1-110

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FUJITSU MICROELECTRONICS 4?E D MM 3749762 0019331 2 MEFNI T-46-A3-/7 MB81464-12 MB81464-15 PACKAGE DIMENSIONS (Suffix: -PSZ) roe view! TAS Ves 00, WE NC Ag Ac Ar Az Ao 20-LEAD PLASTIC ZIG-ZAG IN-LINE PACKAGE (CASE No.: ZIP-20P-M01) — ora 228.25, a a mua Jb eee 73038) ees (025+0 087 jt 05011 27) || 020+ 004 100(2 54) TYP TYP (05020 10) (ROW SPACE) Lea No >) LET YT Tr rT rT tT eorrom view) 9 (© 008 FUITSU LIMITED Z200018.40 ‘eee fiteten) 1-113

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FUJITSU MICROELECTRONICS 47E D mM 3749762 0019332 7-¥6-Q3-/7 MB81464-12 MB81464-15 PACKAGE DIMENSIONS (Suffix: -C) , —_ DIP-18C-A01 18-LEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE (CASE No.: DIP-18C-A01) pe ows T i i 290.259 a00:.010 _) SSS (02570 30) | prea || ois cantax ooo Sar 00s vor 1-114