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FUJITSU MICROELECTRONICS 74 vel 37497?be OOO24bS 4 I . ak

3749762 FUJITSU MICROELECTRONICS 8C 02665 D7-¥6-23-/7

. ! MOS Memories FUJITSU @ MB81416-10, MB81416-12, MB81416-15 . NMOS 65,536-Bit Dynamic Random Access Memory ! Peeoription ‘The Fujitsu MB81416 is a fully decoded, dj ic NMOS: : \\e Fujitsu is @ fully decoded, dynamic NMOS random access memory organized as 16384 words by 4-bits. The design is. [TET tT titty Ty TTT bet TI optimized for high speed, high performance applications such as bet : mainframe memory, buffer memory, peripheral storage and en- CTT Tie fr vironments where low power dissipation and compact layout are Hee Se Aa route Be tain Multiplexed row and column address Inputs permit the MB81416 to LTRS ; ie ee be housed In a standard 18pin DIP that Is compatible with the CSA JEDEC approved pinout. Greater refresh versatility is provided by a new GAS before RAS on-chip teresh capably. ‘The MBST416 HoH also features “page mode" which allows high speed random ac- pis-t8-c cess of up to 64 nibble wide words within the same row address, HE feta ‘The MB81416 is fabricated using silicon gate NMOS and Fujitsu's rrrTTrtriy ty Ty ‘advanced Double-Layer Polyacon process. This process, coupled = |~1~7— 7-1-7} with singletransistor memory storage cells, permits maximum cir- cuit density and minimal chip size, Dynamic circuitry tsemployed {| | | | {tt | | in the design, including the sense amplifiers. ~ [TTT TT laaast Clock timing requirements are non-critical, and the power supply tt te 2 AC tolerance Is very wide, All inputs and outputs are TTL compatible. mR oa inl AH ey Features PT ae TT

1 Organized as 16384 words by Mi Zme/128 cyclo Refresh (Ay~Ag)

ote Socctrodtywite Capes” TTT TELL 4

1 Row Accese TinelCyelo Time: Page Mode Capabiy for | pueblo | 1114

inser Gutsut unite Crt ttt rr max/200 min. ‘@ Output unlatched at cycle end MB81416-12 120nsec W Early Write or Output Enable LPP erry yy maxi290 min. controls output buffer im- COCeeE ccc ee ae kao nda CEE maxi260 min. in Chip Address and Daten Low Active Power (tc =min) latches LPP SO MBG141640 303mW (max) ml Standard 18pin DIP Clie ST] \\ MaB1416412 276mW (max) ML All Inputs TTL Compatible, low 1 > 27 MBB1416-15 240mW (max) capacitive load - 6 : All devices 26mW standby Throo State TTL Compatible mL ; il w Si +5V +10% Power jutputs ‘ex Suny § Onchip Substrate Bias. Ha § CAR botore RAS Retresh Generator IFAS Only Rotesh [ hebesbo-Fod [TT | * a on Cee CYT TTT Tre) NOTE: Tho following IEEE Std. 662-1980 Symbols are used In this data sheet: DO = Data U0, G = Output Enable : and W = Welto Enable. 7 i 1-84

FUJITSU MICROELECTRONICS 78 .DEM) 374972 OOozaLL o Bf, BUYTTSU NICROELECTRONTC T-46-23°19) MB61416-10 MB81416-12 MB81416-15 ee . | pnasie Block Diagram and i Pin Configurations 7 ° = Eas aby U “laws t “CLOCK wi) [is] 00, : ' mE] [re ae a “E faln Ue sae eo ee | nt | perrnee aL] me p-----4 tr . ° ’ [sy “tls Hy il 2 20) @_Vss 004 : vs 00, /3 16 TAS Whe 15] 005 W715 sop view Ml Ay Pe sh oe 4a Veo Ar Aa . ee Absolute Maximum Ratings (See Note) Rating Symbol Value Unit Batiog I symtot_vatve it Voltage on any pin relative to Ves Vine Your. =1to +7 v Voltage on Voc supply relative to Vas. Vv. -1to +7 v Ceramic —65 to +150 Geramie “580 418 Storage Temperature Tera. Betws Power Dissipation Po 10 Ww Short Circuit Output Current = 50 mA ; Utes ar ve iy sansa pew si a ee EN neta aces an nen al nee . Capacitance (T,= 25°C) Parameter Symbol Typ Max Unit Parameter syembot tye ant i Input Capacitance Ag~ Ay, Cin = 5 pF i . Input Capacitance RAS, CAS, W, @ Cina = 8 pF i ‘Output Capacitance DQ,-DQ, Cp = 7 PF Hy SS S— : Recommended Operating onditions Pe Min } (Referenced to Ves) arameter ‘Symbol Typ Max Unit Operating Temperature Hi ‘Supply Voltage Voo 45 5.0 55 v : Yyvonag Veg o o O Vv Input High Voltage Vin 24 = 65 Vv O°C to +70°C Input Low Voltage, i: allinputs except DQ Vit 0 = 8 | Input Low Voltage, DQ Vip* 10 — 08 v t | “The device will withstand undershoots to the -2.0V level with a maximum pulse width the 20ns at the -1.8V level, i eeeeFeFFFSFSFSFSFSSSSSSSSS i FUJITSU ! 1-85

FUJITSU MICROELECTRONICS 28 Def 374972 cooesL? 2 Pf t-42-23-4y MB81416-10 MBG1416-12 MBG1416-15 ! SSS . ; DC Charaoteristios (Recommended operating conditions unless otherwise earameter symbol Min Max unit i noted.) ‘OPERATING CURRENT* MBBI416-10 5 . Average power supply current MBBI41612 Ios 50 mA (RAS, CAS cycling; tao = min) MB81416-15 45 ‘STANDBY CURRENT i Power supply current (RAS = CAS = Vin) loca 45 mA j REFRESH CURRENTI* 1486141610 eo I. Average power supply current Me81416-42 loca 36 mA i (CAS = Vin, RAS cycling: tao = min) MBB1416-15 32 { PAGE MODE CURRENT MB81416-10 B ! ‘Average power supply current MBB1416-12 Icy 8 mA ‘ (RAS = Vj, CAS cycling; too = min) MB81416-16 32 : REFRESH CURRENT 2° MBBT416-10 42 ‘Average power supply current MBBISIE12 — boos 38 mA (RAS cycling, CAS before RAS) MB81416-15 36 - INPUT LEAKAGE CURRENT Input leakage current, any Input (0s Viys5.5V, Vog=55V, Vog=OV, in -0 10 oy all other pins not under test = OV) OUTPUT LEAKAGE CURRENT : (Data out is disabled, OV = Voyr = 5.6V) fou ~~ Lal OUTPUT LEVELS Output high voltage (Io = -5mA) Vout 24 Output low voltage (Io, = 4.2mA) Vou. 04 v \\Note*: Iog is dependent on output loading and cycle rates. Specified values aro obtained with the output open. log Is . cdependsi{ on Input low voltage level Visy Vas “OSV. FuvITSU = 4 1-86 & ET a te |

’ FUJITSU MICROELECTRONICS: 78 a 3749762 OOO2ab8 4 3749762 FUJITSU MICROELECTRONICS 8C 02868 Dp w.23-19 | MB81416-10 MB81416-12 MB81416-15 . AC Characteristics (Recommended operating conditions unless otherwise . noted.) . ' MBE1416-10 MBS1416-12 MH81416-15 symtet meerereto mnorereee unreree es Notes _Alerate_*Stangaré__n_Wox_Win_ Mar Wn” War__unt : Time between Refresh t ‘TRVRV — 2 - 2 2 ms fda Rade Cio Tind gg TREUREE_——) 5g 2p —2 fendi Cyc Tine neg TELE 9 = 39 = — 9 = —_S— Access Time from! 4,0) thac TRELQV = 100, = 120 150 ns Access Time from’ ©) & TCELQV = 50 S so 75 as Suit Btertun onaay "tee Teen 9 39) —g- 5 2 — Teapslontine ga 3 Precharge Time tap TREHREL 90 = 10 10 = ns SRS rise a ~~ eget — 0 od 1 or — ay Hold Time tesa TCELREH 0 = CJ = = ns RS Pecos Ve Pape SG oni) top ——Toenoet— ig =p = =" — “All eyles except page mode) toon TCEHCEL «400 — 6 - 8 - ns. CXS Pulse Width tons TCELCEH 50 1000060 10000 75 10000 ns KS Hold Time Nesn TRELCEH 1000 120, — 150 = ns RASto' ‘Delay Time COX TRELCEL 2 50 20 Car 15 cy . . Fie AS sat Up tng gg teint — ap 9p 2 fewAaes Sa Up Tn taste = = — PwAdses Hed Te pg nt fo 7 J = — . Column Address Set Up Time aso. TAVOEL a a) = 18. Gelunn Aas Hot Ting Tig —toeta p= 15 Sy = — Bead oneand Se Up tind“ Twice 9 = > = > == — Read Command Hold tine Ets “fotearcedteRS lew "tne 9 ee a te Goneand eens ge 068g gp 2 Write Command Hold Time TCELWH 20 =- Ey = _ w = cy We canine ue ati“ "ati 99 = 7 Wie Conmanat RRS end Tite ———~ggg TURE as = —=—g —= = — : ‘Write Command tot Lead Time TWLCEH cy - 50 -_ & = as BaiaisaUpting 1" vee = 2 2 Bana tno Fee — y= = 10 W Delay @ TCELWL 85 = 400 — 120 = ns. BS Wong tg tat ts i Aes ine tHE ge tata Sioa Dey Tings fr 3 2 2 Hold Time Referenced to TWLGL oO = oO = 0 = ns Ship Bt Tw 1 oy Fae" Tonge 3 S$ ——g 2 — fate Wade Ge Tine ne Feet 105-2 ty 8 —2 Page Mode Read WriteGycleTime _tpgug CENCE 160 208 = a9 => — Tage toda eas ete Gio Ting ego TENE _—180_—_—a6 = 0 = To RAS (8 belore AAS Roa tro TORREL ‘GAS Hold Time Referenced to FA (AS balore RA Rood) frou TARGET Precharge to’ Active Time Sap TREHCEL 20 = 20 = 2% - ns Refresh Counter Test! Pulse Width (10) ty TRELREH 2800 — 325 — 300 = ns fetes CouierecyeeTine 00) we THEIR 360" —= ot —= 99 == — ; SioRES mache setup Ting tog ate = Oatalnto AS Delay Time A) type TORE? Bata into belay Tine 0) gag tL 9 3 3} = — i a ; EASteeetSery) ton romves ae soem. “Toombs uncota hE ee tus Tent once, oe eee FUJITSU 1-87 . .

. FUJITSU MICROELECTRONICS 26 DE 3749 ?be OO | TYO-23-19 (MB61416-10 MBG1416-12 4 ‘(MBS1416-15 { . i AC Characteristics j (Continued) Notes: 7 taco (Min) = tayy (IN) + 2ty + tage (min): i 4. An intial pause of 208 regued attr fr= Gre, power up, followed by any 8 RAS cycles, 8. twice town and tayp are non-estrictive : i before proper operation Is achieved. If the In- operating parameters. They are included in ternal refresh counter Is to be effective, a the data sheet as electrical characteristics on- minimum of 8 CAS-before-RAS initlallzation ly. If twos twos (min), the cycle is an early ‘oycles Instead of 8 RAS cyoles are required. Write We ative date out cin wil remelt - 2. AC measurements assume t, = 6ns. open cout (high impedante) throughout the 3. Vy (min,) and Vy) .) are rete levels " i tGtimescuing ting cfinput signa fanot- ‘foun toup (in) and rye typ in) | ton times are measured between Vp, (min) willcontain data road trom tho slacted cll. It | ‘and Vi, (max). nelther of the above sets of conditions Is | 4. taco Is specified as a reference point only. If Satisfied, the condition of the data out is In- | tego treo) (max,) the specified maximum determinate, ; Tran) Thess lcorced by thecooust® 8. Elter fay OF tay must be eatltiod fora read ‘ that taco exceeds taco (max.), oycle. : 5, Assumes that taco taco (max). 10. Refresh counter test oycle only. 6, Measured with a load equivalent to 2 TTL 11. Either tpzo OF tozo must be satlstled for all loads and 100pF. cycles. . ‘Timing Diagrams Read Oyole \\ i my t tons os Ry VF SO psey se | 6 We RE ABiites KNEES KKXXRXKKAXKKKXXXXAAK Sa 050050050 il _| ‘ue me ‘orr 20 te ——_ oe ee © We XXXXXXXXXXXXXXXKXKAL _ AXXXXXXXXKXK Write Cycle (Early Write) J G=Don't Care tne vw i ts Vo - om an ly sh ' v7 =>) . A Me XQ iactatse RDM Santee XXXKKKXKRAXKRKARARARS weer ce . Wve XXXXXXX = SL RRKRRRRRRRRKKEREED tes. Jo “om XERRXXXXXRA exit KXXXXXXKKXXKKRRKKK) . ata Yin : yy, on = 59 ost FUJITSU - 1-88. : i (P7252 PSNR at . |

FUJITSU MICROELECTRONICS 78 DE 37497b2 000 are Teeyeasn MBO1416-10 MB61416-12 ‘MBG1416-16 . . (ont Write Cycle (Output Enable Controlled) tae: . vn tras j mn . ve sal swf Fem FJ tome 4 a i XK REE KKK Koo KXXXXXXXXAXAXKAKXAXKKKKKLND 5 . tw a Ve ‘ew | | tos: a Fa i Y = ; ae wane XY vs onan EKKRXKRNEKES 1. Noro ut wane AEB | 0e¢2 . a ver>| routes] |e Ty, SXXXXXXXXX XXXXXXXXXXXKXXK Note 1: ‘Woan lo saited and i tow nay ite Cyl the dat out be "VALIO" But wan yy 4 teat te ca ct wba Read-Write/Read-Modity-Write Cycle two: we Via ‘tras: vy a 2ST Mn. vn AME so foe AW SOREEK KOON BEM RXR EK LKR KE KEKE REND Wy, MXXXXXXXY , Now Vet ‘tpze: tos. pm. an won ax KDOK eth KXXXNRXKHRE ag tem wow Sa sayz ‘um Ce (0 Choe Le Ty, AXXXXXXXXXN XXXXXXXXXXXXXXK Kye" FUJITSU .

FUJITSU NICROELECTRONICS 74 DEM 37497be oodea?71 4 DP pve-22-17 DT . | 881416-10 7 s1416-12 ! 088 1410-15 . Timing Disgrame (Continued) Page Mode Read Cycle . _ Vw tras: : Vor RYT ies a7 : Vu. | i mo ie im so TIT | i 6 ye RMIBEX BEKXKRNASIREEEC XY) Ns KMKXXXXKXXKK eee [ tee ten] = Hines [et wt XXX Ky X ozo} toze et Mean ea OOD pata Vou Hinz egg art ‘era “TaD r Han, om von ‘oe “aie, | foe boa tone . \\ [| ee Ife Fe ne fos 3 wt QRRXXXKKN AXKKXKRN _AXKKG KN AXKXKXXKXKKED Page Mode Write Cycle : (@=Don't Care) : : we OY ™ a ek “ a ; “sn pen tase : at RNRBEM REE KXXXN ESE REX) Floor WE XXXL SAXXXXN [MORXEXY TOL etl XKKKRREKRND i tos ie | ; tor ke oH | BATA A RM BARE KRM BARE KOHN KONE KKK KKK KKEND | cr : Docrrcee FUJITSU - 1-90 :

FUJITSU MICROELECTRONICS 78 vel 3749?b2 0002872 b& f.. 4e23 MB81416-10 . MB61416-12 . MB61416-16 , (ontiued Page Mode Read-Write Cyole . am ‘™ ‘tras: : oS locas’ tas: tas: | 01" SOXBBEN RSE KKXHON we KXK KY DE ORERXRE : taosie! owsrh Hows t f+towoe}ay[ owt v sale aga: Nise] . ton had ton - ES mROBLO OG Sek 02 ay 0 a OL ALOLOLOLOLOO we Mae witha gue. tne’ ot va oun Vo. tox j Yorx toca . _ Vin loca | tore toez Va RAS Only Refresh Cycle NOTE: CAS = Vi,;: Ay, W, G = Don't Care ARS “ aa tee en ; + RXXXKXKDL alles KRRKKK KEK KER KKKKKKER GKS-Betore-fAS Refresh Cycle NOTE: A, W, G = Don’t Care : |< !rc. aS a AXXXXD wo YO ggg : i : ben can . FUJITSU 1-01

8 ve 3749?b2 OOO2873 B | _ FUJITSU MICROELECTRONICS ? rveasig | | MB61416-10 MB61416-12 | MB61416-165 . ‘Timing Diagrams: | (Continued) Hidden Refresh Cycle | . ' . fee ny, | a hy Ta . a , [rotten a alee, 8 “yy Oo FESS FETT Une CaeeeneRRNK AJ ve ROY cameenemrevan rea tor=el re ny a 3 ’ ve fox (oo or" SKK wane (XEK . EKS-Betore-RAS Refresh Counter Test Cycle : 7 ' vn tee Ld * =— a Ke ‘s : we i ©" RERXXEXXEXRKIM SK KRXKKKKKEKREXK KKK i . =I Ife : ; wouan " YXYRKRERLERRERY i | REXE i cA Yon “ee fir ; ‘ ames onenereeree ed er ‘nes ‘ew oa Wenn.” (REREREREXEEREY || wr XXXRREKE SRP ve oo Bite ™ CORXRERRRRE lel CaO . ‘Gewnme ,, OXXXXXXXXXXXXXXXKN XXXXXXXXKXKKD , Poortean Note 1: When tewo is satistied and G Is Low (Delayed: Write Cycle), the data out will be “VALID”, But when tow ls not eatilied, the data out will be "INVALID". i FUJITSU 1-92

L = we se . o FUJITSU MICROELECTRONICS 78 DEB) 3749762 GOOZE7Y O nye eg.19 | Ls | MB81416-10 i wpe1416-12 ' MBE1416-165 i Description _ Address Inputs of the state of the output RAS-Only Retresh ' A total of 14 binary Input ad- enable (@) ‘The MB81416's dynamic . Gross bits are needed to decode Output Enable ‘memory cells may be refreshed any one of 16,384 nibble wide by performing any memory cy- words from the MBB1416's The output butters ara controll ole at each of the 128 row ad- 65,536 memory cells, Ad- orate a i ther CHS or iq dresses (Ay through Apat least . dressing a Random 4bit word Snable (Sf ain tas every 2 milliseconds. When a \\s initiated by establishing 8 inth oH ni output but at Bre row Is accessed all bits In the row address bits on the ad- {a the high Impedance state, fow are rofreshed. During dress input pins, (Ap through pang 2 read ot age" a4 fefresh, A; (Pin 10) is not used A), and after they are stable, Now, the butters and elther Vjy or Va. may be ap- latching these address bits with phe a} burngan early wate plied to this pin, the falling edge of the Row Ad Cycle G has no effect on the _-RAS-only Refresh is a simplified drees Strobe (FAS), Then 6 ook oyele that consists of strobin tumn adress bits are establish OM»Put bulers. row address with RAS while ed on the address input pins A, ta GiB remains high. During a through Ae, Alter the addresses Date Inputs FAS only Retrean cyclo, OAS is are stable, they ara latched with Data may be written into the high and the ‘output buiters are the falling edge of the Column 'MBB1416 during a write or read- in the high Impedance state. ‘Address Strobe (CAS), Address modify-write cyole. The last fall-Strobing each of the 128 row timing Is made non-critical by —_ing edge of od orW, strobes addresses (Ay through A.) with the MB81416's “gated CAS" clr- the data into the 4 on-chip data Flag will rofreoh all 65,608 ccultry which automatically In- latches. In an early-write sysle, memory calls In the MBB1416, . hibits CAS until the Row Ad- Wis brought low prior to 5 RAS-only Refresh results in a : dress Hold time (yy) has been and the data Is strobed In by” gubstantalraducon in power satiated andthe desi with both the setup time issipation compared to'a full : puts have changed from row to (to) and hold time (toy) refer: RASIGAS column addresses. ehbed to the fang Sago of tmemnory yoke CAS. The outputs are in the ee togerdase of Go state ERS Botore FAS Rotrosh The MB81416 has 4 common _"edardless of G's state. Ina jetore RAS * UO pine (OG;,0,,Da,, and Selaved write or aread red. CAS before RAS refresh is an DQ,). Read or write modes are Sfter GAB, data Is strobedin by On-chip refresh capability that ‘selected with the write enable W, and set-up and hold times eliminates the need for external pin (W). An output enable pin ‘are roferenced to W. To avold refresh addresses. If CAS is t (G) controls the state of the out» buss contention on VO pins, It held low for the speciied set-up put buffers making delayed Is necessary during adelayed __{@ (rcs) before RAS goes write and read-modify-write write ora read-modity-urite cy- (08%, the on-chip refrash control cycles possible, The DQ pins le for & to be high prior to "¥ glock generators and refresh provide TTL compatible inputs GStainput'so ther the output S07@SS counter are enabled. and three-state TTL compatible buffers are In the high imped: An internal refresh operation outputs with a fan-out of two BAe ne ee automatically ocours and the standard TTL loads. Data-out writen, "0 refresh address counter Is inter- has the same polarity as data- ‘nal inoremardog sin repens in. n for the next fore on oui at th FAS refresh operation. 1 can be read from the wae table MB81416 with elther a read or a : 10 read mode or write modes _read-modify-write cycle. These oR are determined by the state of cycles begin with the outputs In Hidden GAS Betore RAS the write enable pin (W). A logic the high Impedance state. The high on W selects the read outputs contain active, valid A hidden refresh cycle may be mode and a logic tow on W data only after both CAS and @ performed while maintaining selocts thio write mode. When have been brought fow and the latest valld data at the out- ‘Wis high (tead mode), the data have satisfied the minimum ac- —_put by extending the CAS ac- Inputs are disabled. If W goes —_cess time from RAS (taac) and tive time and cycling RAS. The low and satisfies the write com- the minimum access time from refresh row address Is provided mand setup time {ucs) before —_the output enable toes Outputs _by the on-chip refresh address CAS goes low, the data outputs contain valid data as long as counter. This ellminates the will remain in the high- both CAS and G are held low. need for the external row ad- Impedance state for the dura- ‘They return to the high im- dress that Is required by tion of the cycle. This allows a _pedance state when elther GAS DRAMs that do not have CAS: ‘write cycle to ocour regardiess. or @ go high. before FAS refresh capability. *Note: GAS Betore FAS refresh avallabio on request. . FusITSU 1-98 :

FUJITSU MICROELECTRONICS 78 veR 3744 ?be gogea7s i I. 16-2351 MBS 1416-10 MBO1416-12 MBG 1416-15 . SSS Description, t (Continued) CAS Bofore RAS Refresh ‘Suggested CAS Before RAS Page Mode | Counter Test Cycle Refresh Counter Test Procesur® pace mode memory cycles pro- A special timing sequence us- The GAS before AAS Refresh vide faster acoass and lower . . . ing the CAS before Counter Test Cyole timing Is us- power dissipation than normal Refresh Counter Test Cycle pro- ed In each of the following memory cycles. in page mode, H vides a convenient way to verify steps: it Is possible to read, write, or Po: the functionality of the CAS. 1, Initiallzed the Internal refresh f@ad-modlfy.write, As long as 1 before RAS refresh circultry. the applicable timing re- } oRS counter by performing 8 i ‘The cycle begins with a cycles. quirements are observed, It {s i before RAS operation. Then ‘ Possible to mix these cyoles In i CAS Is cycled “high” and then 2. Write a test pattern of any order. A page mode cycle i “low”, This enables a read, ‘lows” into each set of 4 begins with a normal cycle. ! write, or read-modify-write memory cells at a single col- Wile RAS Is kept low to maln- H operation to occur, Four umn address and 128 row taln the row address, CAS Is i memory cells are accessed with addresses. (The row ad- ‘eycled to strobe In additional i the location defined as follows? Grosses are supplied by the column addresses. This ! ‘on-chip refresh counter.) eliminates the time required to | & Using read-modity-write setup and strobe sequential 1 Row Address — ‘cycles, read the “lows” writ. row addresses for the same Bits Ap through A, are sup- ten during step 2 and write Page. Up to 64 nibble wide plied by the on-chip refresh “highs” Into the same words may be accessed with Counter, Bit Ay is set low inter: memory locations. Perform the same row address. rally. this step 126 times so that ete are written into me : ' sets of 4 memory cells. | ote aa nough are 4, Read the highs written dur- strobed-in by the ‘ating edge of Ing step 3. CAS as In a normal memory cy- 6. Compliment the test pattern cle. and repeat steps 2, 3, and 4. ‘Typical Characteristics Curves . (CURRENT WAVEFORM (Vcc = 5.5V, Ta = 25°C) Favors cveut ona RANEKS cveLE _RREONLY REFRESH cvcLE TAGEMODE CYCLE EXEREFOREAIS nEFRESH cvCLE PREECE FREER ESCO ERE EEE EERE REC ooh oe ROOT ee COTE RE EEE EEE CEE ocOeecee eee SS oS Se 20 SE eo AA-EH | COR Oe es | | i mn EECCA eee BBG CORSE RE | SR ee ool -- UHHH CHEECH EEE [RD 1 ee SE A i NEE SF | ETE HITACHI IEE CCC oa CAE COA Ce ee eee COT an BET TSITOICUT INSTR INSET) a ne ee SEE er a i i z eeeSSsSsSsSSSSSSSSSSSSSSSSSSS | Fugsrrsu be pa

FuuITSU MICROELECTRONICS 78 DE 37497b2 ooo287b 3 i

3749762 FUJITSU MICROELECTRONICS TBC ULBI6 — Dag-23219

| (MBO1416-10 Be1416-12 p81416-15 Curves (Continued) pe] er —_—s OAC “TT CeCe ee | PCT TTT i.e 1 ifeet] pee os a . anne JD poet PCeFT oat a CTT os OPERATING CURRENT vs ‘STANDBY CURRENT ws i. LI] eas. =| 1] Cone RELL LE ieee Jaa cea =na cor aan eT rrrr POT A : ruyrsu- SSS i 1-95,

ey JETSU MICROELECTRONICS 78 DE) 3749742 DO02877 5 [-

3749762 FUJITSU MICROELECTRONICS TEC 02877 — Dgygeny ni

FUJITSU NICROELECTRONICS 78 DEM) 3749742 OOoza7a 7 |

3749762 FUJITSU MICROELECTRONICS TBC 02878 Oxyg-23-1

MBS1416-10 | mne1416-12 MB61416-15 7 i . a" Typical Characteristics | Curves AMBIENT TEMPERATURE CYCLE RATE i wants ! 3 ee rn 7, LE" Peles : | OS i |_| LET TT te EpAnne PECTIC E45nne ; ae PAH Ta, AMBIENT TEMPERATURE (°C) ‘tae, CYCLE RATE (MHz) REFRESH CURRENT 2 nepnesi! CURRENT 2 . ‘SUPPLY VOLTAGE AMBIENT TEMPERATURE eet TT :. [sno | tLe T Be LT Teen | ac EEE . Es £6 |_| ' PCT TT eTTT TTT] i po ee “ve suntv VOLTAGE vaAumoerrouesnavune ADDRESS AND DATA INPUT ‘ADDRESS AND DATA INPUT VOLTAGE vs SUPPLY VOLTAGE ‘VOLTAGE vs AMBIENT 40 ‘TEMPERATURE LEFLLL fee ee ag : EE scat

3 So} icine,

Ali TT H“CPTT : ta DCCC : ‘Veg. SUPPLY VOLTAGE (VI ‘Ta AMBIENT TEMPERATURE fC) Furey 1-97

t . : ° oO | TUUETSU ncRoELEcTRONTCS 78 Dell a7uq7be goo2e7s 9 Bf T-4e-239-17 ! MBG1416-10 t mBe1416-12 mBO1416-15 : Curves (Continued) pss] | TT pterl [| S| eo | CA | ELE SI TTT 11 : tol hl abe ba bob SUPPLY CURRENT vs SUPPLY VOLTAGE DURING POWER UP ae 23, 3° Be “PP “PPE 2c pT TT BAT et ele JUSeeen % or ea a) ES § errr | ano eLLETT sLLLI TT) aan rere i 1-98

FUJITSU MICROELECTRONICS 78 DE) 3749762 OOoesao 5 | eee Ri | MB61416-10 } netatente MBS1416-15 bar (Continued) . SUBSTARATE VOLTAGE Heseces 8 1 | ECACLLY | Poco ou COCSSSS eLLIT TTT +] > ‘50us/Division . CURRENT WAVEFORM DURING POWER UP (ON MEMORY BOARD) rT ee Tee i 2M | | gy | tT tT Ul BLM bale roles a. | | tt ey : ; 5 T \\\\ ‘capacitor (0.14uF) : A fey | : "heer tA eer] | ‘ ° 10 Division ve 100,/\\vion & s

“J EYsITSU MICROELECTRONICS 78 DEB) 374972 O00z881 7 Deve-a3-09 Ee MBS1416-10 ‘MBG1416-12 ‘MBG1416-15 . : Package Dimensions Dimensions In inches 18-Lead Cerdip (millimeters) Dual In-Line Package . DIP-18C-CO1 one nega mae aT i MOAT A Ao yen | WY | a | i Ferd soon! . ™ a LT ches . ean pn ae Bint 18-Lead Plastic Dual In-Line Package DIP-18P-MO1 Mm Mmm mfr mir oe ™ I, ae ae ee ~ maf fn ne } fers 100(2.54) | ant1.19) 0110.38) 920(0.511MIN 2 coyeun HL unas t 4-100

FUJITSU MICROELECTRONICS 78 DEM 3749?b2 O00e882 4 Drvc-23-19 Ei MBS1416-10 : MBO1416-12 MBG1416-15 . Package Dimensions : (Continued) Dimensions In inches (millimeters) ‘18-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER (CASE No.: LCC-18C-F02) | ce I noosto201rve P—] cy os.601 | ie i a scoleoat” : a cw. | p) C4 “aaa aT “Shape of Pin 1 index: Subject to change without notice : 1-101 -

Product Information

MB81416-15 specifications and overview.

Summary

MOS Memories

Description

The Fujitsu MB81416 is a fully decoded, dynamic NMOS random access memory organized as 16384 words by 4-bits. The design is optimized for high speed, high performance applications such as mainframe memory, buffer memory, peripheral storage and en- vironments where low power dissipation and compact layout are required. Multiplexed row and column address Inputs permit the MB81416 to be housed in a standard 18-pin DIP that is compatible with the JEDEC approved pinout. Greater refresh versatility is provided by a new CAS before RAS on-chip refresh capability. The MB81416 also features "page mode" which allows high speed random ac- cess of up to 64 nibble wide words within the same row address. The MB81416 is fabricated using silicon gate NMOS and Fujitsu's advanced Double-Layer Polysilicon process. This process, coupled with single-transistor memory storage cells, permits maximum cir- cuit density and minimal chip size. Dynamic circuitry is employed in the design, including the sense amplifiers. Clock timing requirements are non-critical, and the power supply tolerance is very wide. All inputs and outputs are TTL compatible.

Source title MB81416-15 Datasheet(PDF) - fujitsu semiconductor

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