MB674205 FUJITSU | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
DESCRIPTION
‘The Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to provide high density, low power, and operating speeds that are comparable to standard bipolar logic. The AV (MB65xxxx) series is an ideal choice for LS! and VLS! applications that require up to 8000 gates, 2304 bits of RAM, 4608 bits of ROM or for bus interface circults resistors for easy interfacing with bus organized logic. The AVM (MB66xxxx) series of ‘memory arrays include, in addition to the ‘The C4002 and C1502 have up to 2304 bits of RAM organized In an optional by-nine memory configuration that is system from 256-by-4 to 32-by-32. The AVM memories contain duplicate decoder and address register logic so that they may be split and used as two Independent memories without borrowing any of the unit cells. All AV, AVB and AVM arrays use the same basic internal cell structure and common logic Macros. FEATURES © Pull-up/pull-down input buffers available. © 1.4 ns gate delay typical. @ Single SV power supply. (2-Input NAND gate,F.0.=2) © TTL compatible 1/0, CMOS ® Static RAM or ROM on chip. Input and Schmitt trigger Input. © = Silicon-gate 1.8 micron dual metal. © Popular CAE workstations supported. © 100% automatic placement and © Over 100 unit cells available for design. routing with guaranteed 90% ceil utilization. © Predesigned software macros avaliable. (F-Macros). © =Three-state and bidirectional outputs available. © Fast turnaround: 5 weeks after final validation. © = High-drive output. * Evaluation samples available. Av-omos senies [oes [ mane [Ges [v0 | Gu Spesd] Fears] [Tezeoay | weesoon [260 [108 [am | ra ery | |_ceoooav | meesoxx | e000 [160 [tans | High Denaity | AVE-EMOS SERIES TT cssave_[ Nowrsun | ss” | moet | 14m | Haron | [exsonve | wesrsen [ese [se co" | sare | von | [cracave | watrenn [tee [co eof | tare | avo | | creooave [wesrine [vere [ra coy [ttn | Horie | AVM-CMOS SERIES |~Crsozavi| wessaox | 166 | vor nao? [tan | «K ROMAK RAN pled or Toprocscad Ts any feeth or Oy wig tAeabe oe techeterrod wo any tied Dory wliRbat the pas welt Senso SY Ritu Leone ™Y 1-41
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS ' (Vee= OV.) a ee a [pu vorage [vi | eres [= | vores om [output vonage | vo | Mesos TT Motos | vote | SS TT [output current®avavn | tos [oT ms Storage Temperature | Tora [esceramie [| ts0ceramie [°c [=orasic | | asrmate | | 1, Permanent device damage may occur Ifthe absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions of recommended operation. Exposure 10 absolute maximum ratings for extended periods may affect device reliably 2, No more than one output can be shorted at a time and no output can Be shorted for mare than one second RECOMMENDED OPERATING CONDITIONS (as = OV. [ream [ome [vom [oes [mim [om | [supe vonage | oo | as Tso sas vats [Ciro ign vonage | vm | eT Pvt | tercmosimouts [vu | Vooxonr [= | = ons | teoutuowvorage | om | | To ts | terewosinmue | ow | = T= Texas [wots [anvion Tomperaure | tm | 0 | = | m [| AV, AVM SERIES CAPACITANCE (Ta = 25 °C, Vop= V) = 0 volts, f = 1 MHz.) [_—rarameter —[symbet_[nimam YT tynteat [Maximum [unt | put capactance | on | = | | ek [ou capsctance | Cor | = | - | 28 nr [vo pncesactancs | eyo | = = Pn AVB SERIES CAPACITANCE (Ta = 28 °C, Voge V, = 0 volts, f = 1 MHz.) ee [won capactance | ow | - | - | eT | ouputcepacance | cor | - | - | fr | [Cuopmeapactance | Go | = | - | a |e 1-42
DC CHARACTERISTICS, (Recommended operating conditions unless otherwise noted.) Power Supply Current (Steady state, V, = OV or V55)| HA ‘Output High Voltage Vou Yoo oy ® -0.4 MA) for Driver Output v vt Output Low Voltage Vou Ves (log = 3.2 ma) tor Driver Output Vou Ves (ou = 10.0 ma) Input High Voltage [Veg arts for CMOS Input A EL Ae | input Low Vortage Ta ots a a YC Input Leakage Current 7 nA (= 0-Voo) Input Leakage Current BA (3-state, Vi = 0 - Yoo ) Input Pull-Up/Down Ka Resistor (Pull up: Vy = OV, Pull down Vis = Voo } AC CHARACTERISTICS DELAY MULTIPLIERS FOR PRE-LAYOUT SIMULATION (See AV Series Gate Arrays Unit Cel Libra a Propagation Delay a ee Se |_dsabie time OT tazitee | tyexoas [| txre | om a Hold Time a [_ pace wratn tow AC CHARACTERISTICS DELAY MULTIPLIERS FOR POST-LAYOUT SIMULATION (See AV Series Gate Arrays Unit Cell Library) [renner [sym | tiamin [nee [women [or eis oe 1-43
bate illal PROPAGATION DELAY CHARACTERISTIC Ta = 25% tup v8 Cy tan v8 CL Note: During the simulation, external tup 15 tan 15 O4L, HEW loading capacitance is assumed (ns) ‘OAL, HEW (ns) 047, HET to be the same as the testing 10 * 10 condition, |.e.: 02B:60pF 04T:65pF HET:85pF, 02L:60pF O4T, HBT 028 O4L:65pF H6W:65pF 5 ry 5 4 028 02k o2L 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 LOAD CAPACITANCE C (PF) LOAD CAPACITANCE C, (pF) AV AND AVB-CMOS GATE ARRAY CHIP LAYOUT AND ORGANIZATION CHIP LAYOUT AV AND AVB SERIES EXCEPT C&600AV AND C8000AV
1 AFHEASE =a
| HERE H ' RHEE BA! I B Bea 8 He! n= i= Ep: Ae! , HA ES = | HEE BH | Hates He! | bea ea He} ‘“E REE BAY OBEEE HAO 1-44
| _essoave [967 er ES CE ST | | erzoonve ees] | ereooave [ree a] |___ezoooave [aoe ete tees] SO [——esoony seco as ser SS Note: 1. UO numbers parertheoes float 0 avlabie when hii cupute ae use 1 | C6600AV, C8000AV AND AVM GATE ARRAY CHIP LAYOUT AND ORGANIZATION EE CRM AND AVM GATE ARRAY CHIP LAYOUT AND ORGANIZATION C6600AV, C8000AV CHIP LAYOUT OPT] Ena CEH 8 EEE For CS600AV each block may Lam FEST MRA EAH aE COTA Ra aH | For CBOOOAV each block is fixed PH 0 ECE Und for each Block should not HU OUTE TES exceed 90% of the total COPEL) EO TE avalablo in that block EEE EE OO eee Vetbatnerneeee LULU EEErrereety] PEEEEEEE EEEEE ee LI C6600AV, C8000AV ORGANIZATION ee ers ee es eed |_—cesoonv | __osee | 4 ro0o-ao00] - | verano | 100 | [caoooay [e000 T2000 too Po Eto Cd 1-45,
MB66xx0K% MB67xxxx C1502AVM, C2301AVM CHIP LAYOUT The maximum basic cells used for the basic cell block | oO oO Oo oO Oo should not exceed 90% of the toa roa, OPS TRC] Cy The block te configurable HEE EEE ° (or tither 1024 ot 2304 total bite OP HT asic cet stock Piltiiiti| OI) word to 32-bte per word, or 9-bits per word to 36-bits TUUEOEEE CEL EEEEEE EE EEEEELEEEEC EEE TEE 8-bit word sizes and larger (for C2301AVM) oF 18-58 MMMM CHSOZAVM) alow dhsion of the RAM blok nto two Copan RAM or ROM BLOCK Date 1] separate PAMSS. WEE HH ROM can be provided n OW) place of RAM. The ROM block la configurable for OOo OOO : sither 2048 of 4808 total bits. (C4002AVM CHIP LAYOUT For automatic placement and routing the maximum basic oo tat cas ot onan 9% ot tellus Cnuit The RAM block is configurable for 2304 total bits organized Basic Cell: WUTUREER EE from 9 bits per word to 36 bits per word. eee ' Hu ' 18-bit word sizes and larger allow division of the RAM block HEL ase] Into two separate RAMs. 0 otiiitiLrom ia ROM can be provided In place of RAM. The ROM block Is oo oo configured for 4608 total bits. C1502AVM, C2301AVM, C4002AVM ORGANIZATION [eee [seworican [ enw [oecoumn [nawone [rio em] crsozavm | vse | ts |e bo aoe | vor irom)" | [czsoravm | __2a75_—s| es | os | abetoazon | ti cnton? | Note: 1. Wan POM i proved 146
An unprogrammed gate array is an array of basic cells. Thus the “gates” in a gate array are actually the basic cells which will make up fal loge. Fulteu's basi col Contain enough Wansltor to frm a tue input NAND gate Se ee ; FF eS SS ST | ‘ ° [PE tt " — es, P N Unprogrammmed Basic Cell UNIT CELL A design is Implemented in a gate array by logicially combining unit cells from the Fujitsu unit cell library to form the logic. Fujitsu provides unit cells to perform most common logic functions and the designer need only name the unit cells required to form the higher level logic functions of his design. x A Yoo] =p v ° x A had 8 N2N, Vss' ‘Two-Input NAND Gate Unit Cell (One Basic Cell) A two-input NAND gate requires only one basic cell to implement. Other unit cells may require as many as 60 or more basic cells. USER MACROS: User Macros are groupe of unt cate which perform an identifiable function within the design i sa user macro because fi defined by the designer. The primary utility of a user macro Is that it allows the designer to compose a macro function from unit cells once, then use it any number of times simply by calling it by name. PTT TT Tee een ee ey i i onD>-+ +> pout me H ' H ' fs ee ee H } amb} cLN> T H User Macro QAC is Composed of Three FOM Unit Cells 1-47
F-Macros are created and offered by Fulitsu to emulate the function of popular industry-standard TTL. devices. They are Identical In application to user macros. Using F-Macros, a designer may convert an existing design directly into gate array. For example, the 74LS191 function Is emulated by the Fujitsu F191 F-Macro. VO Cells The 1/0 cells located on the periphery of the gate array chip are programmable to any of the Input or output buffers avaliable, The ‘actual location of an I/O butfer on the chip is determined by the location on the chip of the associated circuitry and any pin location requirements that may be in effect. eT tor I<— oT 1] suse Bidirectional Butter DESIGN DESCRIPTION DESIGN DESCRIPTION Fujitsu requires only two basic Inputs to complete a gate array design: A Logle Description and a Test Description, The logic desoription defines the logical function of the circuit to be implemented in the array, The test description defines the electrical operation required. AV, AVB AND AVM LOGIC HIERARCHY ‘AVM only 7 Unit Cot [omen Unit Col i Unit Cot | Cot Level Note: 1. ROM can be made availabe In piace of RAM. 1-48
CBB00AV, CB000AV LOGIC HIERARCHY [ons [ aoe | [axe | [vocm Block Love [ence] [ee Nerovert [om eu ] | vse cn] [ once] Cortera For clarity, Macro Level and Cell Level components are shown for Block A only. 1 | All Logic hierarchy blocks contain the Macro and Cell Levels of hierarchy. LOGIC DESCRIPTION ‘The Logic Description, sometimes called a *notlist.” calls out tho unit cells utllzed and thelr interconnection to form the designer‘ circuit. Fujtsu uses a proprietary description language, the Fujitsu Logic Description Language (FLDL), to enter the logic descrip- tion language into the design flow to produce the array design. Designers may prepare thelr logic description using FLDL or use other description media which Fujitsu will convert to FLDL. Designers using Dalsy. Valld or Mentor design workstations are pro- Vided with conversion programe as part of the Fujtsu Design Kits for thase workstations. In all cases, the design description must follow the fundamental design description structure provided by the logic hierarchy. In many cases Fujtsu will provide turnkey design services. LOGIC HIERARCHY ‘The Logic Description Is organized into a hierarchy of design components. The logic hierarchy provides the fundamental structure for all logic description inputs and allows a designer to divide his logic into major macro functions and folow a step-by-step ‘approach in describing their interconnection. User Macros may be created to allow repeating the same logic function many times {nthe design without describing the entire function each time. Fujitsu provides predefined macros (F-Macros) which duplicate the function of many popular Industry-standard TTL devices and RAM macros which provide from 1K to 2K of single-port static RAM on chip. Also, ROM macros can be provided. The CS600AV and CB000AV are further divided into “blocks” of cells to ease the layout operations. CHIP LEVEL The Chip Level of the logic description defines the interconnection of the design components to each other and the I/O calls. For most AV-CMOS family devices, all types of design components including user macros, F-Macros, RAM macros, ROM macros, ‘and unit cells may be interconnected with each other and the 1/0 calls to form the chip level logic provided the basic cells total Tequired does not exceed 90% of the basic cell total on the array. For the CB600AV and C8000AV. the same basic cells total restriction applies; the chip level of hierarchy describes only the interconnection of the blocks with the I/O cells to form the chip level logic. BLOCK LEVEL The Block Level of the logic description defines the interconnection of design components to form each block of the logic descrip- tion, CBS00AV and C8000AV allow up to $0% of the available basic cells to be utllized for each block. Designers may utilze any of the available design components, including user macros, F-Macros and unit cells for interconnection within the blocks provided the basic coll total required to implement the block design does not exceed the maximum allowed for the block. CS600AV provides a fiexible block arrangement, allowing block sizes to range between 1000 and 2000 basic cells provided the total does not exceed 90% of the total avallable on the array. 4-49
The Macro Level of the logic description defines the interconnection of unit celis to form user macros. F-Macros may not be used to form user macros. Nor may user macros be nested to form other user macros. The total number of basic cells Included In one User Macro can be larger than the total number of basic cells available In one column of the array provided the number of BCs In any of the Unit Cells used In the User Macro does not exceed the total number of basic cells avallable In one column of the array. TEST DESCRIPTION ‘The Test Description defines the electrical pertormance required of the finished array. Test descriptions are used for all simulation operations and are ultimately converted into final test programs for prototype and production testing. Fujitsu utilzes the proprie- tary Fujitsu Test Data Description Language (FTDL} for all test description inputs to the design operation. As with the logle description, designers may submit test descriptions utlizing other media and Fujitsu wil convert to FTDL. Designers using Daisy, Valid or Mentor design workstations are provided with conversion programs as part of the Fujitsu Design Kits for these worksta- tions. Turnkey services may be available, A complete test description will Include D.C. testing and functional testing. Delay testing ‘may be performed under some conditions. DESIGN DEVELOPMENT FLOW 1] DESIGN WORKSTATION SIMPLIFIED FLOW ‘Schematic Capture ore [ sss | Timing Verity FLOL FTOL Convert Convert WORKSTATION DESIGN Fujitsu provides workstation support software free of charge to designers using workstations manufactured by Daisy, Valld or Mentor. This software Includes a complete design library of unit cells, 1/0 cells, and memory macros for AV-CMOS gate arrays and conversion programs which generate the logic and test descriptions in the FLOL and FTDL languages required for design input to Fujitsu. FUJITSU DESIGN DEVELOPMENT FLOW SUMMARY Fujitsu accepts a variety of design Input media but all media must be converted to logic and test descriptions using the FLDL and FTDL description languages. Fujitsu may request additional engineering fees for conversion. Logic and test descriptions are col- lected into data fles for access by the Fujitsu CAD system. The test data file provides the basic Information used to conduct simulations and generate the final test program. LORC The Logie Design Rule Check conducts a verification that no design rule violations for interconnect. hierarchy or design description language syntax have occurred, and that the description is complete. Fujitsu will work with the designer to resolve any discrepan- cles before proceeding with the design development 1-50
‘The Functional Logie Simulation is conducted using minimum, maximum and typical values for process, power supply and tem- erature conditions, with estimated interconnect metal loading. The functional logic simulation must successfully demonstrate device operation according to the designer's test description before any layout operations are attempted. FINAL VALIDATION Final Validation Is conducted to produce the device operating specification for approval and signoff by the designer. The simulation s conducted using values for Interconnect metal loading based on the actual layout. Full range values for process, temperature and power supply variation are also used. A final operating specification Is presented to the designer which defines the parameters which will be guaranteed by Fujitsu in the prototype and production devices. FUJITSU DESIGN DEVELOPMENT FLOW SUMMARY Logie Fite Functional Simulation Functional Simulation uses minimum, maximum and typical values for process Functional variations and operating Logie Simulation conditions with estimated Interconnect metal loading. Layout and Route Final Validation Final Validation uses Interconnect meta! loading ser values based on actual layout conditions. Simulation Ie conducted using expected variables for power supply, Prototype process and temperature. ‘The result Is a final device Performance specification. PROTOTYPES At the completion of the design development Fujitsu provides the designer with prototypes for on-site design evaluation, Ten Prototype devices (Five for C8000AV) are provided with the development fee. Additional prototypes may be provided for an additional fee. 1-51
wvenrer, [vin [nvener dt nae | tes cock ourer ano [3 _| SuPeth ramuy [van | Power merer | + | Kaa | oatea nox tor comp [3 | [ite [otek auter | 2 | ce | stock ceckauter | 1 | [ces [rover ceckeuter [a J -) - +. - 1 Nano FaMiLy (“yay [ erpanano [+ | nee | eaputronermano [6 | [onan | s-rpanano [2 | wen | e-rpst rower nano | 6 | [Cen [arpa ani 2 [es | o-trt Power nan [7 | [zs | 2-hput Power NANO [| 3 | Noe | 12-mput Power nano [9 | [nie | a-hest Power Nano[ a] Now | 16-hout Power nano [11 | [nae [input Powernand [os f= [ AND FAMILY [yap [arpa Power and? [na | era poner and [3] a NOR FAMILY (“fay [@rpanon [+ [mo | sxputromenon [6 | ran | snputnon | 2 [ras [ eimput Powernon | 6 | | ran | einpwon [2 | nap | o-houtPowernon | 7 | |_mza_| 2rpurPowernoa | s_ | aca | r2tmputPowrnon | 9 | [35 | Schout Pover non | 8 | nos | te-rpst rover nion | 11 _| [nas [ainputrowernon [ «J - [= OR FAMILY [~pap_[ocrput Power OR [_@ | map | twpmhomron 3 | SS enonicon [uso Powerenow | [nas [ fowreon +d AND-OR Invert AND-OR Invert ed ee AND-OR Invert AND-OR Invert ee ‘OR-AND Invert ‘OR-AND Invert a ee OR-AND Invert 4-Input OR-AND Invert a 1-52
[vor | It |__runction | gare | woe | | rimetion | aaa | MULTIPLEXER eu Set ware [rea [Power Sano ewe | 6 | vee | power Donec 8 | |_t28_| Power a-anoe-wite [79 [uz | Power 2-one-wiee [9 | [rae | Power ano a-wse [5 | ae] power-on a-ie | [tas | Power sAn6 sce [7 [vss Power-on sone |? | Power AND S-wide | 9 | uaa] Power 4-0A 9-wide = L_tas [Power «ano a-wite [11 [use | power son ewe | 11 | Fame [_ Fee _[reverore | Sans Sara" [Fs | Power DFF with Proset | FOE | Positive Edge Power OFF | | with Clear Bower DFF with Ciear/ Positive Edge with Cle: |_ tor | Beagorr wenn [19 | roa | patie sae win Gear [9 | | Foe | Power DFF with Clear | ° | Positive Edge Power JKFF with | 2 | [sos [ore 7 [ra | Power acre wth ear | 1 | [rer_[orrcmene [9 pram Preset [roe [ore wintaten fe [= fo = dT Famiuvusine [fom [ore [6 Trop [ orrwinsovmest | @ | TRANSmissiON | Fon [oFF winset_ [7 | roa | ebeorr | at_| GATES |__F00_| BFF with Reset | 7 | ron [aoe ore win cioar | 26 | LATCH FAMILY [tre [tit bata tateh [4 [ura [abi bata Laton [ 3 [ik [osta ator [un] ata tatch wth ears | tm | 4-Bit Data Latch with Cloar SET REGISTER [rs [oons,g, + [ra | em wh aneina 4 bit Sin Pout with Syne Load DECODER FAMILY “pez [74 Dwccw [6 [6m | Sabena <= Note: 1. C47 Is not avaliable for C-OS0AVE and C540AVB. 1-53
SELECTOR FAMILY] ‘tap | 2:1 Seloctor | 2 van | teselector 2 [rec | bual2it Soector [4 [van [ual t:2 soloctor | 8 | [reo [ait sotector | 2 tsa | at sector Ts COMPARATOR [oR Magnitude Comparator ADDER FAMILY [Ain [tbh Full Adder [¢ [ash [spe ruadaer 50 1 2-bit Ful Adder [we [- [= T- Sern sere Ca [sea tse [a Sr 7 peay unre eater tomy con [3 [oe | ate anon [7] [sos [aur oouyeny fe | =p -] MOCELL FAMILY [ag [input Butter 0] 1k8 [clocked input Suttertinertnai] 0 | | rau? | 128 with input Pul-up [0] ikeu? [ike with input Put-up | o | [e007 | 28 with input Puaown | 0 | a0 [me with put Pat-cown [0] [1s | Clocked input Butter [0 | ig | CMOS interface input Butter LB with input Pullup De (True & inverter) 1w0® | 18 with Inut Pul-down | 0] eou® [20 win pt Pu | | Trigger input [Het [Tristate Output & input Butter] 0 | Lari? [irs win input Putcu [0 neru® [Het win input Purup | 0 | | rrs0* [itt with input Putedown | 0 | eto? | Her win input Put-cown | 0 _ | [oze [ouput surer || oar | trvetate output outer | 0 Power Output Butter (True) | 0 _| Power Tri-state Output Buffer Power Tri-state Output and (True) Input Buffer (True) Tri-state Output and CMOS fer (Tr | newu? | Hew wih input puup | o_ | tntertace input Bufer (re) [newo? | Wew with input Put-down [0 | ecu? [HEC win input Put-up |_| Power Tri-state Output and HBC with input Pulldown | 0 | owes [_Heev? | i ee [reeo? | Hee with Inout Pulcdown [0 | Note: 1. SMI and 8M2 must not be used together In one eh, 2, Avaliabie ony for AVE. 1-54
Fujitsu's F-Macros are direct software macro implementations of popular industry-standard TTL functions. They may be used in the design exactly the same as user macros. Designers’s converting existing TTL designs to gate array will find the F-Macro a particularly useful implementation. F-MACROS REPLACE THESE TTL DEVICES [7400 agg as aie re Za A ZT [7404 rat00 60 rare es LS ES EZ RS OE ST OE 731 ET | CS OZ A O31 | [__zazo zat rare a | zaznzato7 rare ae | zaes za108 rar 106 | [zor Prato rata as EZ Orr Oo [age zag rasa [zeae [se rate raze ZC A OZ OZ | zaga Te zat20 ga rage ta [vss Prats raiso | 7 | rT | | rae rarne as aars [zs rata 49 razr a | | zase [rata 63 aero [zea [es zatso ae | |_zaco_ [rats [sa raves so
75 ZT OC OZ |
a 7r 7 SO | [rare [se rasa [98 aes se |_zaze_ [zag [a9 zasse 8 [yar |e tatsy [a3 ass | Zr [rae [te zango ee rare ss | Zr A TT G7 RT | |_zaas_ [graze to | Zr A xT SO 7c Y ST | [veer Prange 70 vases ZS EC OZ Z| eZ EC OZ OZ | Za TC OZ ZO | ZT EC OO ZO | ZS 5 OT | EZ ON | eZ | [vor Note: 1! These F-Macros utlize complex unit cals and may not be avallabie for smaller arrays. 1-55
[asia | sword za-bt [sword x apt | [sie [az word x zapt [se word ete | [asic | azword x 20-pe | seword x t2-pit | [rst se-word x reve | sz-word x toot
84 WORD [rer eewort tee P
RAM MACROS =e [Reta tword x tape word x apt ae a RAM MACROS 128-word x 8-bit 256 WORD. [res aeworax ape 256, WORD 258-word x 4-bit C1502AVM/C4002AVM SWORD og [aio eeworaxaeee cr 128.WORD [as tte tee RAM MACROS aaa 256- ZENO. ROM MACRO LIBRARY ROM MACRO LIBRARY ¢2301AVM ROM MAGH [van eewor eee ROM MACROS YRn (256-word x 8-bit Note: Contact nearest Fultu Design Center for ational ROM data 1-56
PACKAGE AVAILABILITY MATRIX MB67x00K eee PACKAGE AVAILABILITY MATRIX Ee DUAL IN-LINE PACKAGES, PLASTIC SHRINK TYPE (SH-DIP) DUAL IN-LINE PACKAGES DUAL IN-LINE PACKAGES, PLASTIC (PDIP) PLASTIC SKINNY TYPE (SK-DIP) PacKace| row-| poe-lpor-lpor-lror-| | pacace om Jor lor |ow- | om ase ee br i emos [score [+ [eo [eo Pe ToT ee Pet | [oom [oe Te fe TT [ewave [o [eo [oe [oto T ete Tet | [soe Tet. Te Te [ecoave | [Te Tepe pete Tet) [eve Te ee Te. lizoonve[ [|e Pe Tete Tete) femme. Te. Te TT 5) A OD | |icconva [Te Po Pee Pe Te | Ficus Te Te 1 | [zoooavaf [fT Pe Te Te Pete} [accnve [ee Te TT [zzoiavef Te ee) [ora ee A A A a OO | [acon [Te Te eT econ ee [sooeaveal [Tecan [sowoav [Te |) eco ro feeooay [OP [eso [eowoav [OT Coco PLASTIC LEADED CHIP CARRIERS (PLCC) FLAT PACKS, PLASTIC (FPT) See rr PPE EE pRooucT] 28 | 44 | 8 Propuct| ‘te “ 180 omos ['asoava | e |e [| [ssa Te [oe Te Te Te TT [swoave [eo | e [| [soo Te Te Te Te Te eT [esoave [+ [ie TT} [ooo TT fe Pe Pe Pe Ty | weooava |e [oe [| [move Pe eee | ssozaveal Te Te Te) [isczaf Oe ee eT [ weooave |e [oe [oo [} [romvet TT eee TO | zoooave [Te [oe TO} [rove Te eee [oa] pe ee) eo de eee | acooav [oe Pe Pe Te) foo Te Pee Te Pot [svoonv [fe Pe Te] [oom PO Te Pee Te Poy | soozava| [acca PO eee [ sooo [Oe re ow Te Te Poo [ esooay [foo PO po fototol [sooo [TT Loom [Oe fot eyo | ‘¢ = QUALIFIED PRODUCTION OFFICIALLY AVAILABLE NOW (D- PACKAGE COMBINATION UNDER DEVELOPMENT Note: ‘ontact nearest Fultsu Design Center for current package information and power supply pin restrictions Siastic FA packages (64, 50, 195, 178-pin) are how under Govelogrrant 1-57
PACKAGE AVAILABILITY MATRIX QUALIN-LINE PACKAGES, GERANG (COIP) Fe GGG rouse] om} eoe-| eo S cmos [wwe [sfefeteletetel | [exe fe pe tetetetetet 1 [eexe [pete tet tt Ce cc Penn] [oe Lee a [exo] [emo [fo 1] a [mama] PP ee [won | [eon PPP TJ CERAMIC LEADLESS CHIP CARRIERS (LCC) Ce es Cri Cansuens (aces ‘CERAMIC PIN GRID ARRAY (PGA) (zxcsase | ss [sae [use| we [ace [ee [oem | eee | ee | cor [or] moses | = [ee | se [= [a |e F; cmos [asoave |e | @ | | | fy ot ot oy [saoave |e | e |e | of | |e J [J J | [ascave |e | e [|e fo; [te ty yy [reonve |e | e | e | O| | Je fT yy [wom | [es fe |ofolote fe tT. | Tf [recone |e [ie [fe Pofol pete TTT [ecoomv | | e |e |olol|ofetfe te. {Tf [aooav [| | ete }|olofofetfey]-.}] | | [soon | te |e | of ofote [ee Ty [esonv | [|e |oft | [ete ye Te T | [eo [| te | ol [ [{efeT]e{e | | 7 amrco moouoTon ornanw nnuaBiE NOW (- PACKAGE COMBINATION UNDER DEVELOPMENT Note: 1-58