MB61VHXXX FUJITSU | Alldatasheet
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1a) pele ter FUJITSU min CMOS Gate Array GENERAL INFORMATION The Fujitsu CMOS gate array family consists of twenty: devices with their complexity of 2640 to 8000 gates, eight device types which are fabricated with advanced The “AVM” version is a gate array with a memory block silicon gate CMOS technology. And more than 14 devices on a chip. The device size ranges from 1564 to 4087 gates are coming, Fujitsu CMOS gate array are configured In a with 1K or 2K RAM, or 2K or 4K ROM. Just as “HB”, matrix of Basic Cells arranged in columns positioned the “AVB" version can supply high drive capability, side by side and Input/Output Calls on the device periph- The device size has variety of 357 gates to 2052 gates, ery. One Basic Cell is equivalent to a 2-input gate, The The “UH™ technology can provide ultra high speed by its custom logic function Is realized by interconnecting Unit fine gate length. There are also two versions for “UH": Cells with double-layer metalization or tripletayer for “UH” and “UM”, The complexity of “UH” Is 20160. largest arrays. The lower density “UH” devices are now under develop- The Fujitsu CMOS gate array family contains four tech- ment, The “UM”, just as “AVIA”, integrates gate array nology options: “H", “VH", “AV”, and "UH". and memory on one chip, The complexity of "UM" array The “H" is high performance and provides STTL speed. is 10080 gates or 15120 gates with 12K or 6K-bit RAM, Two versions using this technology are prepared: “H” respectively, and “HB”. The complexity of “H” ranges from 440 gates To assure quick, simple and error-free implementation up to 3900. The “HB” version can provide high output of the metal Interconnection routing, Fujitsu utilizes a drive capability because of its special output buffer unique Computer Aided Design (CAD) system which fully design. The complexity ranges from 440 to 1440 gates, automates LSI design. The CAD system performs 3 The “VH" Is very high performance and provides ECL complete logic simulation, Incorporating AC parameters speed with CMOS power consumption. There are three bated on the mask design, prior to the device fabrication, options from 2640 to 8000 gate sizes, Because of this design process, error-free LS! can be The “AV” is the advanced “VH" technology. And there developed quickly. are three versions making use of this technology: “AV™, “AVM", and “AVB". The “AV” version consists of 5 TNT aaa TiTige ° Spbveumureiwiadsseists OT tae ra a Ba ie 4 UU = Scape RRaeR eC C-15006UM Die, Before Metalization C-2000AVB Die, Before Matalization . at ase cae een tao oe = Soe et eed ery AN Sys Peace MME PO PHURE Lazo faa y ae: y Meme |e | 2, SER UTATTON | C-15006UM Die, After Metalization : C-2000 AVB Die, After Metalization
2595 C14
MAANOIEES. AUR FUJITSU CMOS Gaie Array Hwee
FEATURES
© 28 array types and more array types to come . ® High-speed Silicon Gate CMOS process © Double-layer metallization, or Triple-layer metallization for C-20000UH, C-16006UM, and C-10012UM © Variety of software macros called “F-MACRO”, equivalent to MSI Functions ©@ TTL compatible Input/Output, CMOS Input and Schmitt-Trigger Input . ® High drive capability Output Buffer for “HB”, “AVB", “UH, and “UM” © Input pull-up/pull-dowm options for “HB” and “AVB" ® Predesigned Memory Macros for “AVM” and “UM” ‘ © +65V single power supply © Fast turn-around on design © Simplified customer interface (only logic design and test pattern information required) © Fully supported by Fujitsu CAD system (logic validation, physical layout, metal interconnection and test program) ® Design Support on major CAE workstations @ Wide variety of packaging options ® C-440H, C-700H, C-1275H, C-2000H, C-3900H, C-2600VH, C-3900VH, and C-SO00VH are alternate sourced by Texas Instruments Incorporated, USA. EBL pty ne As fi J, Te ey ea sap che SSX APs N N High Density PC Board with Fujitsu Gate Arrays Basic Coll Equivalent Circuit . ae. ng I = << pIS SY 4 ees . +H i ae mm Fujitsu Gate Array, Replacing a Lot of MSI/SSI Basie Cell Topology a 2 2596 opoL .
(Mi EE FUJITSU mom CMOS Gate Array DEVICE DESCRIPTION mm [a a ae] eS [ cason | wootnunx | swoon | 4m | oe | le [errors | wesanenx | sooo | 4m | 72 | ovat [erarene | wocsnbeex | vetoowe | 4m | a@ | Saar cascovn | wasoviinn | 260mm | 2am | 100 | own wscoviion | eoooenm | 2am [veo | * 1: 2Hnput gate equivalent, 2: F/O = 2, 2Z-input NAND gate. 3: BV +10% or 4.5V + 20% operation possible, For details, plesie contact Fujitsu. 4: Wider tamperature oparatian possible, For details, please contact Fujitru. PACKAGE OPTIONS nology - ~T. [caso [oe Jon [ow Joe [oe onalee [eal [ate Te Pe Te Te Peron || do oe lovelies Jowalee [al Te Te | | AO OO CCC [ean CD a = a Catone [eas Pal fe [eee Te [erm few [realon [veafoes[ af TT | a A fp esecove fee le eee es ee 3 - ~ —- . 7 2597 o-02 .
Power Turn-8 Tach. oh [_s0mW typ. | Seeks | caaow | | _somW tye oav mex | Sweets | C7704 | lor souk mex, |-Sameis_| e276 | 42V mi. nov min, fortnput, {Sweets | 20008 | [ t00mW we. | -04mA tate el ee, [som we. | Bina tout [_Sweeks | C2768 EOWA max, c.2600VH 4.2N min. OAV max. for Input — — | 1oomWtyp. | stlon= | stlon= Butterand | Sweets | c-900vH ssomwiye, | AA | SN Output [Seeks | Ce000vH | B&: Values for Normal Buffer and Clock Driver, : 6: From the customer’s design approval to engineering sample shipment. | 64 | 70 | 2 | 100| 26 | 40 | e+ | 20 | 44 | oe | eo | 4 | 00 | 136] 170] 206 | 256 | Hp fet | r | | [| [ [cso | Pe | [=| fe fe fe [ete] ff pe ee iel-[-| [| |* fe [et Te] | Pf ft y eszren | pf fe ff fe fet ee tf fff ene rt {i pf tt fe ft teens] Pet [ [fe fe te fete] To eT Tf [| casone | f=] [=| | |e [+ [ee] =] |e [fe TT | fT | eve | ppt] je fete tetele fe |] ff [ esarsne | P| [| je fp tafe fe fe Peat Pe] fete] fe | pet=|> fe fe [ [ [ [ essoovn | a ee Oe ee Note: ¢: Ceramic package ®: Plastic package ft: Plastic (Shrink type DIP: Lead Spacing center to center: 0.07") Plastic PGA packages and more than 100-pin plastic Flot packages are under development, Contact Fujitsu for availability, : ‘ 4
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LUM maa) ae FUJITSU Emm CMOS Gate Array DEVICE DESCRIPTION (2 3 | c2svoav | mecsénn | 264oone | 14m | 108 | Clock Driver [ esnoony | woesoun | eezzonm | 14m [127 | St a rrr en Input pull-up/ MB 68Oxxx | 8000 gates 1Ans Buldown [ean [ern [st [to] cr [eiawave [wero | atom | ram | ee | rene [caomave [weston | aetem | 14m | 0a | 1: 24nput gate equivalent. 2: F/O * 2, input NAND gate. 3: The values In parenthosis show the maximum number of signal pins when no high driving capabality (lo. = 10.0 mA) is used. 4; BY £ 10% operation possible, For details, please contact Fujitsu. 6: Wider temperature operation possible, For details, please contact Fujitsu. PACKAGE OPTIONS ° So Dual Indine Package | Flat Package | oe SIsIeTe nie [40 | a2 | ae | o* | 10 | 20 | 24 | 20 | a | | _cssooav [| TT [ee | Pl yt tT ye ae eee ee | caoooav | | | | | tT | tf tt tt yt ft 5 corona __fov fen fee fis degen itd ap Pe pb |_cstoave [em [on [ow [ow [ow [owalow | eal al ate [fe Te Te | BD | craooave [|| fom fom Jowelow Jowafona] af {Pete Ts | | creooave [| fom [ow [owelon Jowalenal ef TT Tye | | c2oorve ff | | [es few [ow fownfonn] ef | TT [|
2599 D-04
- Gama CMOS Gate Array DEVICE DESCRIPTION 1664 gates . 4K ROM Clock Driver
2376 Schmitt-Trigger
2k ROM Normal Butte . 4087 gates Bidirectional 4K ROM 1: Zinput gate equivalent. 4: BV £ 10% operation possible, For details, plese contact Fujitsu. 2: F/O = 2, 2-input NAND gate, 26 ns RAM acces time. 6: Wider temperature operation possible, For details, please contact Fujitsu. 3: Including 7 RAM Test Pins or § ROM Test Pins, PACKAGE OPTIONS . Fa | ewee [seen nee nol a |_esoozavm | oT Tt tT TT | | ft ty DEVICE DESCRIPTION Cen? thax. Operating* Sy meme | le | men’ |e | i | voomen || EE Normal Buffer Clock Driver 15120 gates | 1.0ns RAM access time Normal Buffer a -=Eee= i -10012UM with 12K 153 RAM Driver Output RAM access time 1; 24nput gate equivalent. 3: SV 210% operation possible. For details, please contact Fujitsu. 7 2: F/O = 2, 2-input NAND gate. 4: Wider temperature operation possible. For detalls, pleese contact Fujitsu. PACKAGE OPTIONS Se nol * | 16 | 10 | 20 | 22] 26 | 20 | 40 | 42 | ae | oa | re | 20 | 4 | oe Tae | a De ee a ee | _evoorom | of tf tf | ft tf fj ft | ft | ft ft ft 7 . 2600 0-05
FUJITSU MICROELECTRONICS 78C D MM 3749762 0003952 4 T- Yo-l-09 FUJITSU CMOS Gate Array muna Power Turn? ech OAV max. 3.2mA atlon= | oavmex, | 22Vmin. | O.8Vmax. | Butferand | Sweeks | c-ss0ave | AV 6: Velues for Normal Buffer and Clock Driver 7: From the customer's design approval to engineering sample shipment. [4 [ 70 [ 00 [ too | 25 [a | e+ | ae | ae | oe | e+ | oe | 8 | 105 | 170 200 | a0 | | pet fete {fe fe Tepe tee fe fe fe Tf YP e2eooay | | a ae eC a a eC ee eee a ee Ce a a eC Note: #: Ceramic package s Plastic package I: Plastic (Shrink type DIP: Lead Spacing center to center: 0.07") Plastic PGA packages and more than 100-pin plastic Flat packages are under development. Contact Fujitsu for availability. oe . ; . 6 _ 2601 D068
FUJITSU MICROELECTRONICS 74C D MM 3?7497?b2 0003953 0 om T-Ya-n -04 (EEE . FUJITSU CMOS Gaie Array mieneins “Power DC Characteristics Tun? 7 Tech aie etae | Outout High | Output Low | Input HighS | Input LowS | Input Leakage | Sound | Device Name | aciogy Voltage Voltage Voltage Voltage Current im [me | omen 4.2V min, | 0.4V mex. H10HA max, -0.4mA | 3.2mA uffer and . state Output . fom “_ 6: Values for Normal Buffer and Clock Driver. 7: From the customer's design approval to engineering sample shipment. Leadless Chip | J.Leaded Chip Carrier Pin Grid Array Package Device Neme [e+ | 70 | 60 ] 100 | 25 | as | oe | 20 | ae | oe | oe | 4 | 08 | 15] 170] 200 | 200 _| a A Ce a eC DD Ce Note: ¢: Ceramic package =: Plastic package . 4; Plastic (Shrink type DIP: Lead Spacing center to center: 0.07") Plastic PGA packages and more than 100-pin plastic Flat packages are under development. Contact Fujitsu for availability. Power DC Characteristics Turn® Dissipation . 8 around | Device Name | Tech Output High | Output Low | Input High® | Input Low® | Input Leakage nology av ius Voltage Voltag Voltage Voltage Current Time $ 0.4V a 600mW typ. atlou=. C-20000UH 3.2mA 40HA max. 4.0V min. or for Input O4mA | G.4mA 240A max. available for 3-state for Driver 500mW typ. ger 10 weeks | ¢-10012UM &: Values for Normal Buffer and Clock Driver 6: From the customer's design approval to engineering sample shipment. Device Name [ s+ | 70 | 0 | 100 | 20 | 4a | oe | 25 | a4 | oe | os | | 0 | 108 [170] 200] 250 | a ee ee eC Note 4: Ceramic package m: Plastic package 1: Plastic (Shrink type DIP: Lead Spacing center to center: 0.07") 256-pin PGA: 60 mil and 100 mil pin center to center are available,
2602 D-07 :
OQ CQO) EE Eevee ee FUJITSU MICROELECTRONICS 76C D EM 3749762 0003954 2 mM T-42r.-11-09 UD FUJITSU ime CMOS Gate Array CUSTOMER/FUJITSU INTERFACE DESIGN PROCEDURE DEVELOPMENT FLOW ON WORKSTATION Customer's Role Interface Fujitsu’s Role OE [Schematic Capture (ret) i S. for Correction SL a od —_ + Simulation u Conversion Conversion i P.O. 3 7
2603 D-08
OOO, Q,Q,QG,G,G,,G,G EE EE EEEE—————EREeeVOeeeeeeeeeeeeEE Sa... FUJITSU MICROELECTRONICS 78C D MM 3749?be OO0395S 4 mm T-Ya--09 DUS ‘7 FUJITSU CMOS Gate Array memien NEW PACKAGE FOR GATE ARRAY : 16-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-16P-M03) —“BAAAAAAR ] He .002(0.05)M1N (STAND OFF) Details of "A" part .008(0.2) 350(8.9) f Piiram INDEX BMG) Stes) THeRHEESE _{k ooogdgddcGddOo0d an 0770.68) -482(12.25) -510(12.95) ‘a Seats)
01986 FUJITSU LiMiTED F1s008s-t¢ Dimensions in
20-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-20P-M02) .002(0.05) MIN oopoonaano| (STAND OFF) HHH RHA AD ai700) i -350(8.9) 311(7.9) fo RRARHEREES . HHHEBUHHE ES Details of “A” part 008(0,2) : TEAR mae CTT T . “||” .024to.6) TYP [_J 0210.55) oath | .00710.18) ‘ . MAX .027(0.68) ©1985 FUJITSU LIMITOE F200068-16 Max Dimensions in . . inches (millimeters)
2604 D-09
eee eee .S.SaSaaxxxxaQaQ2Q50:°0°0; FUJITSU MICROELECTRONICS = 78C D MM A7497b2 OOOR4SE & MT -Y¥a 4-09 CERTTOERTAN FUJITSU Imm CMOS Gate Array NEW PACKAGE FOR GATE ARRAY (Cont'd) 28-LEAD PLASTIC CHIP CARRIER (CASE NO.: LOC-28P-M01) .007(0.18) .010(0.25) . R.030(0.75) nono nM =a TYP LILI rm Zoos (rR Colin ol oto iol q b —_ =) & q h = ce = ora) Et = ee Bo jee EP 498288 | h EST oss0ss, = | . d h sre = = 4 E — = =. | — 5 eesti ay | -456(11.58) | MAN | [Lsou.zm , .486(12.32) So RosT | .178(4.52) | © 1986 FUsITSU LiMiTED c260818-26 | Dimensions in inches (millimeters) 84-LEAD PLASTIC CHIP CARRIER (CASE NO.: LCC-84P.M01) .007(0.18) -010(0.25) . R.030(0.75) TYP —— 7? {te L sbetobititelstobtdebebsiotelshehebebetely \\, q ; = 0170.43) B O O 8
115888348 F heal a: 3
, 304 B Fs ! .02610.65) FE = 119888038} | F je 3 E .178(4.52) 1985 FUJITSU LIMITED ceaosi8.26 inchie (ilimetrs) 11 - 2605 D-10 .
FUJITSU MICROELECTRONICS 78C D MM 3749?be OOO3557 & Me T- 42-11-09 : TEA FUJITSU CMOS Gate Array niin LY Ee NEW PACICAGE FOR GATE ARRAY (Cont'd) 68-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER (CASE No,: LOC-68C-A02) (@PLCS) TYP = edsedelsye)elele]e[sie)eLe]s1 = = c} R.008(0.2)TYP = 5 G / (6sPLcs) PIN No.t INDEX = = a = = af ty = 5 aT : an |an NARAAAARARARARAAAAD 940(23.88) ! [Losots.27i Sonos -960(24,38)50 - iP BOOTRO.S2 TYP ‘os0tt.27) £100 (2.54) BEO(2T.BOITYP TYP MAX ©1985 FUJITSU LIMITED cés0025-1¢ Dimensions in inches (millimeters) 256-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE (CASE No.: PGA-256C-A01) .0059(0.15) ~0098(0,26) °'* saesenenensasanaies B39 9900 9096909009090 Oo 80 0 0 0999 QQOOO ®OO9Q 88980 e808 .900(22.88) at ones S999 S999 @ 83 O Losofofoo} INDEX AREA | SssgesehaSasahesss -050(1.27) -975(24.77)8Q TYP INDEX PIN -071(1.80) -250(6.35) MAX FUJITSU LIMITED R2560018-4¢ Panes eutttneters) - . 12 E
2606 D-11
“FUJITSU MICROELECTRONICS 78Cc D mM 3749762 0003954 T T-$2-11-04 nes FUJITSU , inn CMOS Gate Array LOGIC CELL FAMILY (1) Inverter, Clock Buffer Family. five [ron ara Te a A [vit [Double Powerware [Pein [true eufter at [ee [ TruePower Butter Pd [eit |“ DoublePower suffer TT | | | | [BiH | GuedruploPonerBuffe S| oh | | | | | | [Kia [cock euter | ee [ke |“ Gtedciock anoveuter SST St Ts | 8 Ps fd , [Kaa [Gated Giooktondautfer SSS] 2? | 8 | dd , [x68 |" Gated clock WAND) auffer | | | | | dd , [KAS | “Blosk Glock (OR Butter | | = | | = | dT | [ “koa | slock Gock aurterWon-ineringd | = | | | | - | ——1 (2) NAND/AND Family . [ono Taviavi| ave [va [a [8 _| EO [v2 [Power input and ee [nas [Power SinputNaND iP | [ "Nak [Power 2inputNAND iP | [van "| sinputnan eae ee [nar | “Power dinpur aw fs fs fd [Nab [Power dinputwand iP 8s | _d [Nan [input AND [nap | Powersinputawo 8 8 | dd [Nae | PonerdinputNaND | | | | a [N68 |“Powerinpuewawo sf | | 8 | |e [Nap |"Powerdinpuxawd re = | dd [Nes |“Powersinpuenan Ts Te fe | eT eT | [Nop | PowerdinputNaND | | [Nice | “Power i2inputnand SSCL || |e] ef [Nes | Power winpuenano Pf ff a 2607 D-12 .
FUJITSU MICROELECTRONICS 78C D MM 3749762 00039559 1 T-4a-i-o9 BASEL FUJITSU ett . niin CMOS Gate Array {6) OR-AND-Inverter Family | waom Taviavia[ ava [va [4 [1 | e33—|"Swice BOR Gin OAT SCSCiSC Te a [cts | awidesOR dinputoar | |e | 2 | 2 | 2] | [e286 | awide20R AinputOat | 2] | |e [sit | 2wide 2AND2OR dinputOAr Sd «| 2 | 2 | ef 2 (7) Multiplexer Family rune [724 [ower AND dwide Mutter Side | 6 | 6 | 6 | 6 | 6 [126 | Power 2AND Givide Muttplorr ~*~ 10] 8 | a | 9 |e |_| [128 | “Power 2AND Govide Mutter | 2 | np | | | at [132 | Power SAND 2vide Mulpiexer SSS] | 8 | 8 | 8 | TY | 133 | Power SAND Saige Mulipiexer | 8 | 7 | | [ts4 | Power SAND divide Mulipiexer SS? St] 8 | 8 | 8 | 8 | [-Ta3 | “Power 4-AND aide Multiplexer ———~Ss| to] 9 | 9 | 9 | 9s [9 _| » [re [rower aan aside Muttpiowe fa ao oo at _ [ v2 | Poner2.0R 4nideMuiipixer SS | 6 | 6 | 6 | 6 | «| [“U26 | Power 208 GovideMuttipxer S| | 8 | 8 | 8 | 8 | 9 |, | u28 | Poner 20 Bide Multia | | at Pt | po] | “usz | Power3.0n 2avide Multipiner S| | 8 | 8 |] [vss | Power s.on awideMuidpiexer | | 7 | 7 |p [usa [Power 3.0n aonide Muttiexer SSS] | 8 | 8 | 8 | 8 8 | usa [Power-on 2-videMutipixer «| «| | 6 | 6 | | vas | Power aon aavide Mutipier ————~SSSid| = | 8 | 8 | 8 | 9 [3] [vas] Power on 4wide Mutter sf | tt | | | PY (8) Transmission Gate Data Selector Family ee ee [unum [Aviavin[ ave [vi [¥ [ He _| [rae ait settor a fe fe se | 120 | “uel 2:1 setector a a a a [“r20 [at sector ee 2 [van [t2seeor | | | 2 [-vsp |“ busit:setetor 8 ss [ea [4 Sater = os pe fd 15 :
2608 D-13
FUJITSU MICROELECTRONICS 74C D M@@ 37497be OOO3S5L0 & me T-42.-11-09 FUJITSU CNICS Gate Array binicna (3) NOR/OR Family OO [rar —|Poner Zinta a a [R23 —| Power 2inputOA 3 a a [onaK | Power inpuwWon |__| = [=] = |= [=] [Rew —| “Bout Power Zinpat OR ap ee ee [cae | “Power SinpstNOR [3p oa a a p ee oe ee ee ee Se er Se a [Raa | Foner ainputOR a a a ae [Re6—| “Foner intone [cae —| oversinpaon |e |---| | J [R68 [Power BinputNoR a pp [Ree [Power tina Now |e [9 [Ree | Power teinguwWon | te ao a a (4) ENOR/EOR Family [unum [AVIA ave [va |W [ne] Lew Bae OR Hew —[ paseo tt ee [x25 | rover Exeunie OR a a a a [ean] sinputexciste NOR [a6 | Foner Sinput Exeuste NOR [xa] Binput Excuse OR [x48 [Foner Sinput Excusie oR | P= = (5) AND-OR-Inverter Family [pm | aatte 2aNDSipAGL—___] 2 | 2 [2 [2] 2 | 2] [14 | aaide BAND dinput AO! | | [a | a] [pat aide 2ano dinput aol | 2 | 22 | 2 | 2 [Post | “Sass 2AW0 dinput Aor a | aa | 2 | [936 —| “aaa 2AND Binput AO! a= [= [= = [oper —| “aes 208 BAND Ainpwt ROT} =} ap a a Note: a C47 is not available for C-350AVB, C-540AVB, C-440H, C-770H, C-440HB, and C-770HB, ° ‘SM1 and SM2 must not be used together in one chip. * under development — not available a 14 2609 = D-14 ;
. FUJITSU MICROELECTRONICS 7ac D MM 37497be OOO35b1L T T-¥2 “09 . FUJITSU CMOS Gate Array moc (9) Flip-Flop Family [oan Tavavm[ ave [va TW [a _| [02 | Power oeR = es es | £05 | Power DrEwimPHESET = ss ee | Fo4 |" Powar OFF wih CLEAR andPAEseT [= [40 [40 | a0 [to [90 | [Fos [Power orFwin clean f= fe fe fe fe | A A [ror | orewin oven =e fe fe fs | *[ [roe [Orr andinwh fe ee fe | roo | tainaesey eonerowworrwincisas We Poe Po a and PRESET [ FOE | "Poste sdos docked Power OFF wih CLEAR |---| 4 [yo |e [| 0 [Foe | Poste aye clocked OFF with Lean [=e [se | [| 3] [rom [ore es fs | “Fon [oer wim seh a a [Foo | oer wih neser a [ “ror [OFF win Set ndReser = fe fe fe SN [Fon | abit Der wits CbEAR a fas asa | [ros [Taser nono == [et [Power seer wi EAR aa a [Fs [Power RFF with CLEAR end PRESET a fe fe | [ Fab | “Posh edge clocked Power JRFF wits GUEAR | ~— [va [a [te] | 2 [ SoH [Saw 2input OFF with Gor and Gioseinivoe [va [ =| = | = [=] | 80s_—| "SCAN sinput DFE with CesrandGiostanin [48 [= | | | = |=] | “sok |" scaw Ginput OFF with Giorand Goscionine ve [| - | - | - | - |=] [sin | "Scaw Jc FF wit Gearand Glockinnie [se | = | =f =| = [so | taamrorrnmewnene’ [wf Clock-Inhibit : [Sa | SCAN input DEF with Glennie Pa [808 | SGAN Tinput 481 OFF win Coston [az [SHA | Scaw tinpur ee OFF win Gostcinnioe [es [| | | - |=] [ee | Satagmemerinommres [ee [PS Q Output [ove | Seeommemorrmmcvtnted [le | | P - - - XQ Output SCAN 8-bit DFF with Clock-Inhibit and [om _| SetSaatnseerere |e PP SCAN 8-bit DFF with Clock-Inhibit and Pow | steamer Te [SP [sor] “roit scan bre win keane Note: El C47 is not available for C-350AVB, C-540AVB, C-440H, C-770H, C-440HB, and C-770HB. ‘SM1 and SM2 must not be used together in one chip. * under development — not available _. : 16 _ 2610 &-01 .
FUJITSU MICROELECTRONICS 7ac D 3749?b2 OO03%t2 1 THY2-1-04 I FUJITSU muna CMOS Gate Array (10) Latch Family Number of Basic Cells a [+6 | [purr satsnwimccear CT | | | a | | [ure | tito tach aaa aa [urs [abit date tatceC~dC dP tt | tr | rc [ew [Tait bot batch with LEAR | | te | ts | Yt (11) Shift Register Family [uN/oM TAVIAWMT Ave [| va [W [Ha | [Fst | “atitsoratinParaic-outshintRegiter «dS | te | 8] te | te | 8 | [82 | abi Sift Regier with Synchronous Load [|_| 90 | 20 | 90 [20 | 00 _| | “F8a__| ait Shite Register with Asynchronous toad [>| 84 | 4 [a4 [4 [3a _| a SCAN, Clear (12) Counter Family orm [aviv ave | vH TH | we [ett | FinFlopforcounes ot ot oP | [cat | ath Binary Asynchronous Counter Sid i) ae |e [04a [abit Binary Synchronous Gounter_———+d| | ae (| | ae if ee [c48 [abit Binary Synchronous Up Counter —*+) ae | as | aaa Ya [045 |“ abit Binary Synchronous Up Counter ‘|_| 48 [3 | aa aa | a3 | 047 Tif] Ait Binary Synchronous Up/Oown Gounter___| _— | 68 | es | 68 | 6s | 68 | a Paralle! Load po | torment Parallel Load [sor | ‘it Counter wit Scand OueAR Sid | = | - | - | 6 [| (13) Adder Family Fone a A [TAIN | toitFulaade Sd tf] | 8 | ef | I [adh | 4bieFuttadier id | sso] | [Act | Carry Look Aheedfor #bi Ful Adder | «| - | - | - | - | -_| A 2 RN 7 . 2611 E~O2 .
FUJITSU MICROELECTRONICS 78C D BM 3749762 0003963 3 Te 42-11-04 : FUJITSU CMOS Gate Array lnm (14) Others ee [ouom Taviava| ave [va [a [ne _| |_mca | 4bitMagnitude Comparator | =| af a faz aa [pez [2s denoder PP I [“SMiBH | Sehminetiiggertmout SST 8 | Pe | | swafel | sehmintriggerinevt | | | Pf , EA [apa | suffer Oey ca) | | | dP [Yd [805 | butter (Delay) dT 8 8 Td , [906 | “putter (Galey eat) a= [PES | Stbie Even Parity GeneratoriGhecker [| tz | | - | — |= {| — | [Pos | stbie oad Paty Generaor/Ghecker if 2 [| =| |---| [ “Pee [eit Even Party Generator/Ghecker——_——+| ef | =| == | =| [Peo | “etic even Parity Genertor/Ghecker «| a2 | | ‘| - | - | - | | “Pos | “ebie oa Parity GenerateriChecker <i a2 | — | - | - | = [| -_| [P24 | 4 wide 2%0 1 Dateseector | | (| | dT dd [be4 | 2t04 Decoder with Enable ST TP [pes | sto8 Decoderwith Enable S| oot | <P | Td A a [tar | Four at sector SP A [Tar | Fouroid at Sector SC*d td [tan [4:1 Solecior with Enable S| | | dP Td [T48 | Fourold 4:1 Selector with Enable sd te@ | ‘|= P= | = | -_| [T46 | Ninefoid ait Selector with Enable ita | «i dP (dT dd a [sto | osuekce PP [sts | isuek ew LO [201 |p oo fe fo fo [vat | Speci oir Wa RAN [Wn] Speci cot WON RAP) ["yna | Specil Goi casas WAND] | | dP [vwa | Speci con war, RIN, NaN RBA] <P [vie [Seeciol cuir (@artaray 80 Note: {iM C47 is not available for C-350AVB, C-540AVB, C-440H, C-770H, C-440HB, and C-770HB, Bd SM1 and SM2 must not be used together in one chip. . © under development — not available . 18
2612 E-03
EAS —— i _ O_O FUJITSU MICROELECTRONICS ?ac D B@ 3749762 O00O3964 5 me T-42 <i! ~0F CRA SEu EA FUJITSU monn CMOS Gate Array (15) Memory Macros For C-1502AVM & C-4002AVM For C-18006UM & C-10012UM [Name [Fanetion Xam Fraction] [R610 | Gfx 60 Single Port stato RAM =| [Res |"“eaw x 180 Oval Fort RAM with Address SCAN For C2001AVM [Nome [Funation id , [ “Ret [etx 166 Single Por StavieRAM | [ “Ras —[ 2500 x 4 Single Port State RAM | (16) 1/0 Cell Family ee eee : [onom TavavmT ave [vi [|W | we] NO [ort [Power Output buffer ime) Si | = | = |---| [028 [output eufertiy | | | | | | [oat [Power Output butter We] SSS | | oP [oar | “Sinput AND Tristate Output Buffer =| o | — | - | - | - | -_] | oaw | Power 3input AND Triste Output Buiter | 0 |= |= |= |= |= [oat | Tristate OuputBuftertmereh | 0 | | = ‘| - | - | -_| | oaw |" Power Tistae Output Buffer (inner) =f of - | - | - | = | -_| [048 | “input AND OvinutButter | | Pd dd [oar | Tristste ourputautter(Te) | = | |e fo | | | “oaw [Power Ttstete Outputeufter Tue ———«| | | 0 | - | - | 0] [oat [Power input AND OuiputBuffer «| | = | - | - | - | - | [ot | Triatte Output auffer(Trvel | | | PP dd [o6W | Power Tistte Output Buffer vel | |= | = f= | - | - 1 [Hat [Tristate Output (True, input (Trvel Buffer | 0 |---| - | - | - | -_| [Haw [Power Tristate Output (True, Input (True) Buffer | 0 | _- | - | - | _- |=] [Her [Tristate Output and Input Buffer Tue) «| ~~ | 0 | o | 0 [0 | 9] Sr a a [Horo | “Her with imutPuiidonn | | of | Yo [Hew | “Power Tistote Output and Input Buffer True) | - | - | 0 | = | ~~ | 0] [“Hewo [“HewwithingutPutue | | = | of = | | od [Hew | HewwithinputPultdowe it | | of = | = to] a Buffer (True! a NL Power Tri-state Output and CMOS Interface | vee | figutauirtrecnonsouostnwriee TT |e | - | - |e | a [_weeo [Hoe with Input Puiidonn Sid | = Po = fd 19 .
2613 E~04
FUJITSU MICROELECTRONICS 78C D MM 37497?b2 OOO35LS 7 ma T-42-i-04 . FUJITSU CMOS Gate Array jie (16) 1/0 Cell Family (Cont’d) ° | et pn Pa [ie | inputButterimered ———SSCSC~sSCi CST CTC id A [1280 | laa with input Pulte = dT dd [280 [ia withinmutPurtdown ————S*dP SP | [12 |eMos tntertace inpur Butter True@inverte | —- | o {0 | © | 6 | 0 | [aco |“ racwith input Purp SP [aco [2c with input Pultdown iP (| | Od dT | [1668 | “input Butter (Complementary Ouwmu ~~ | _- | - |= |_- | -_] | 1a8 | Finodtocation 1k overt) iY PP [eB | Fikediocaton tLe (uel —SSSSC*d SP [ike] Clock input autferinwerte) ———SSSSSC«S TOTO of || [tke | ike withinputPutup | = | P| Td [ep [1KB with inputPulrdown i | | dT | [ke [Goce input eutter (Tue) ———SSSSCSCSC~iS | RE [tao | We with input Puitdown SCS dT dT Od [Fit | input eutter for SehmitTriegerinoat___—=—s| ~~~ Pf eT | | [AO [IT with inpue Pune Td | [citio [itt with inputPuedown —SSC*d SY (17) 1/0 Buffer Family for Testing RAM co [onniM [aviavM[ ave | VH [a [HE _| [oam | Outpursutter ue TK TH dR rd [_oam | “Tristate Output outfer inverted SSP S| YY d= dT [oan | Power Tristate Output Buffer Inverted +f 0 | - | -f- |=} =~] [oom | Trisate Output autterTue S| | | Pd dd | oan | Power Tristewe Ouwpur Butter (Tue | 0 | «| = | | = | | [Hawt “Tristate Output (True), Input (True) Buffer {0 |= | - | ~- |= |=] [Ha | Power Tristate Output True), Input (True) Buffer 0 | — | - | - | - | _-_] A a a [13M | tapue Butter (inverter dP dT rd , [a [input Bufterttive) 0 Note: [I C47 is not available for C-350AVB, C-540AVB, C-440H, C-770H, C-440HB, and C-770HB. Mi and SM2 must not be used together in one chip, * under development — not available : . 20
2614 E-05
8 OOOO eEO~Ow
FUJITSU MICROELECTRONICS 78C D MM 37497b2 OOOR%bb FMM TY 2~7)-09 CCE FUJITSU ~ . iin CMOS Gate Array F-MACRO FAMILY F-MACRO Family [Name [Function Equivaent [No.of Gs] [Name | Function Equlvlent [No.of 80s | [Foo atsog a ag [roa | vasoz eo sat | ZS [ros matsog [| Fio0 [toot TT A a DZS [remus] rt attt08 A OT), [rea mats et asia AZ ZS [ras [raga eta asia 7 ZT A TZ | 1, | [res [masse |S dt [aso dCi , [88 [gasses tg [at sige 28 , a QT | Oe . ZZ | [risotto te | a | ZT ZT [eras a) ts ast oe TT A 7 A A A ZT A A I = ZT [Fes [ates a) et sisi [Fas | acsas ete asian A | A | [ror [rats es estes [Foz vatsoz ee | [tee | atsies 0 a [ee asa i si , [roe [ates ce] ee ats dC | 21 : . 2615 E-06 .
EE V~EI—V~VOC=_vO_OOeeeeeeeeeeeeeeeeeeeeeeeee eee ee FUJITSU MICROELECTRONICS 76C D BM 3749762 0003947 O Wy T- 42-11-09 leant . FUJITSU CMOS Gate Array temic [Name [ Funetion Equivaiont [No.of 66] [ri [musts | a | [Figo [ares [rier [asia a [ries atsias a8 [Fico | 7aisieo ——*4t Sito [ries [masini [ries [yatsieg [ries | masioaa | 7a [ries | austesa | [F108 [gag [F260 [98260 ee | , [Fas [raisers [Fae |_aisze itd [F203 | vatszas_— od [F200 | 7aisz00 a [F203 | 7atszos dd [F208 | ats298 [6 [Faso atsssz sd [F976 [asa ta [ra76 [asses ‘ [ro [tsa dT , [Fae | yatsoe 8 | [F962 [vase aot | [rss [vaso id [Faso | _7atsseo da [Fees | 7ausses se [Fes | 7atssos | a | Note: » under development | El not available for C-350AVB, C-540AVB, C-440H, | C-770H, C-440HB, and C-770HB. | : § : 22 |