MB603XXX

MB60XXXX FUJITSU | Alldatasheet

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| Taz soa | UHB SERIES 1.5 MB62XXXX | FUJITSU Bea eeaeus MB ZK September 1906 Editon 1.1

DESCRIPTION

‘The UHB series of 1.6-micron CMOS gate arrays is a hight Integrated low-power, Ultra High-speed product famiy that derives ite enhanced performance and inareased user tlexiilty from the use of a systam-proven, duat-column gate struoture and 2-layer Metal interconnect technology. The unique dusi-ccturnn gate structure Increases density and speed performance, as wall as gato Internal Nigh-drive clock buffers miniviine clock skew across the ctip while internal bus performance and integrity is agsured by (roorporating S-state tranamistion gate logic undernesth the rovting channials. The high-drive output buffers provide highly Symmetrical output waveforms.

FEATURES

© High-deratty stloan gate CMOS technology © Automatic test pattern generation for 6K gates and up = 390 to 12,000 unable gates — complete faenty of scan design macros avaliable: = 00% maximum utitzation futy autorouted © 2-celumn gate structure erhances macro porformance 1 # Ultra tigh spood © High-perfermanoe interna! 3-atate bua - 0.9 = buried ostis within the channeta : two 0.800 gat diay b at tran the rout ‘ensure high . igh ch exrrene eapabinny © Proven 1.5-micron 2-layer metal technotogy = 3.2.mA, 8 MA, 12 MA, and 24 MA options © Highest pin-to-gate count commercially eralable avaiable = 00 logic 1/0 for 936 gates = selectable edge rate control ~ 222 logie I/O for 1200 gates © Low-ehew clock signal dutribution (© ingen buffers Incorporating pul-up/put-down resistence ~ High-performance clock drivere @ But-in feedback resistors for exctiators ~ Hierarchical clock distribution @ User-defined Nerarcty-driven placement = Prequency-dependent clock reuting 1. Gates avelable for logio (exctusive of WO usage). Love SNe teten ache the tes We PB be Jeg 2. Maxdmum signal pin numbers depend on the output Binet Shak Then CA HER eitheg OAL = , ttt

MB62: FusiTsv XXXK MB6Oxxxx <a T=42.-11-OR PRODUCT FAMILY DESCRIPTIONS ee ees tame | peng Jo ane Complexity Basic Cells on Chip ee ee eT ee ee | ee ee es ee ee ee ee RS ee 1 | ee ee ee |_c-srooune | wasoanx [aren cate | ts arava ae Notes: J. |, with F/Ox2, for a 2nput NAND gate, Is 0.9 m8. | | eaprmeneye me 4. The meinem pin numbers depend on the output drive requirements and the package selection. | AC CHARACTERISTICS BEST/WORST CASE MULTIPLIERS FOR PROPAGATION DELAYS Lit sgrelbeny wendy eee A gedit lrt dimer wmigg marge ti—g Rehr ti gator nag . ; ‘voltage, tanout |, Fterconnection routing metal, process variation. input traraition time, and input signal polarity. Tarperatare eo eunety vokage tactere aitectog crepagation delays Inthe UNE OMICS tantly af outa arrays are Gham in Sie | rretayout simustion [| Peat-Layout simulation __ | a i ke [Beat Cane[Worst Cave] Best Case|iorst Cave] Boat Case] Woret Case] Beat Case] Worst Cone | 1, 0-700} 0.96 0.90 1.70 | 2, -20 - Toc 0.38 0.25 1.70 4 40 - ac 0.28 0.20 1.80 1. = commercial temperature range 4, = Industrlal temperature range Constante for catcalating the delays due to process variation, famout loading, Interconnection routing metal, transition time, and signet polarty ere given fer each unit ooll In the UHB Unit Cel Liorary. Delays using these factors are oaiculated for a represeetative salection of unit cota and are shown in the Propagation Delays table on te folowng pago. 1-12

MB6Oxxxx =a REPRESENTATIVE PROPAGATION DELAYS T 4a-ll-0F Caloviations are representative of una oes ih the C12000UHB (UHE 12000-Gate CMOS Gate Array). Tegiagt wetane exe betectnn. Weret cove wlipiete cow mppliod ts typleal wating. Scadter arrays O6n CORRE greeny Grecia [——Fropagaiion Belaya inna) Ve Se = Ve ee ee [Perwrsimen wow [mm Tt [ime [oes oe | ist | iss | a | sat | [renee seroanwno | noe [ime [as [as |e | te | st | ea | actmeweon | ™ | * [iat [iz listististislss| gy AND-OR Inverter atl [imac | ™ | [ise [ts [te | te |e | | se Muttipbescer (A—+X) prewceneer Pe ie Ts a is [en [as [on ‘Sean 8-bit D FF with 7 a OD ii ddd (CK, IH-+Q) Nem-Soan 0 FF a ied Ee Ee Non-Scan Power D FF . el eld BE EB Eel ele ‘Synohronous Up Counter (Cl++CO) Nonm-Soan 4-it Brary Syrchroncus Up Ee ee Note: Delays for Inter-tieck wiring are not included 1-13

T- #2 - 11-69 REPRESENTATIVE PROPAGATION DELAYS (Continued) fold vahue tre ufosted, Worn cave masiouere re eppaed to ype! valeee. nny SS [NDI (Faneousy ee Non-Soan 4-bit Binary Ea ee Counter (DU-+CO) [ereommercorvo [mm Ts [ine [ve [as teal sal cs) smenmer [re | [ime [as [is [ie] te] ie] ea | 1 | Ee De ed sory | ™ | at Le | ie] ia | [emnsowwovo or [os [ine [as Les [em] os] [est ee a ee ee ee ee el SEE ee ee ee ee et [___ Output Butter oad in pr | eee a a ieee ee ee Ee eee ele Note: Delays for imer-bleck wiring are mot included 1-14

. —_ MB62xxxx Fustrsu MB60xxxx Sal T- ~ ee eS eee ee ABSOLUTE MAXIMUM RATINGS! [ating | Symmbot | Minimum [ataxia [unt [rout veuge | Legs [ws |v [ouputvenwge || Mstes | tows |v ee [tou=2ena re eee ee ee Notes: 1. occur # maxim excesded. Functions! eperation shoud ' Lae 3. Only one output at a time may be shorted for more than one sascnd, RECOMMENDED OPERATING CONDITIONS | [Parameter | ymbat | Minimum | ypteat | naaximam | unit | | _swowveme | tL are | so | ees |v [revere wef [eur Heh Votiage for GMOs wet [Vin | Mbox [= P= Tv | [owt Low Vetiaae trcmosireut [vm | - | | Moxos] [erent torwerare dT um TUT eT CAPACITANCE (TA «25°C. Voo = Vi= OV, f= 1 MHE) : [Parameter | vmbot_ | nanimum | Tyoteat [ wastmum | unn | | a [ ememenmy | or | we |r carer | ot TT |e Fc Oe 1-15

EO eeeeeeEOe§Ewe~ooeoO EEEEE— FUJITSU MICROELECTRONICS 23€ D MM 3749762 OO10258 &b mm MB62xxxx Fusirsu MB60xxxx Sal | DC CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted) [renner | trmont | covaien [wom [ea [vino [om] [fewer cwrer [one _[ omer eT | Output High Voltage aa — PP ) for Normal Output (IOL =3.2mA) Vou Yoo v ‘Output High Voltage ) for Driver Output OL =¢mA) Vou Yop v ‘Output High Voltage: . for Driver Output (IOL =12mA) Vou lon = -4mA 4.0 Yoo v Output High Voltage | eben Ronin | von | tous-tma | 40 | = | veo |v | ‘Output Low Voltage? ° for Normal Output (IOL= 3.2mA) Vou. lo, = 3.2mA Vgs Vv ‘Output Low Voltage* | ferbrier cupueticuamay | You | tones | ves | - | oa | ov ‘Output Low Voltage? for Driver Output (IOL= 12mA) Vou O Ve ov ‘Qutput Low Voltage® v, for Driver Output (IOL= 24mA) foL lo = 24mA ss ov Input High Voltage Input Low Voltage EO Input High Voltage | erensevewe | vw | eon | - | - | vd Taput Low Voltage for CMOS Input Vie = Vppx 0.3 v ‘Schmitt Trigger CMOS Input? Vv - Positive-going Threshold yt = 28 4.0 yv Negative-golng Threshold vee Ty. Mi to Vid 97 20 M Hysteresie t+ ~ VT- Min to MIL . . . Schmitt Trigger TTL Input? Vte =~ Positive-going Threshold Vr. _ 2.6 v Negative-going Threshold Ve, ov; Mi to Min 1.8 v Hysterasis Te - Vee Min_to Vit 07 Vv MH=Vop Input Pull-up/Pull-down Resistor Vit =Vss [pit teiage Curent ‘| ty PM r0-Wop | 9 | — | | ml Notes: 1.Viq = Voo, Ve = Ves 2With certain restrictions on pin assignment 3, These values for reference only . 1-16 sa Be

FUJITSU MICROELECTRONICS 23E D M@ 37497b2 0010259 56 MB62xxxx Fusirsu MB6Oxxxx Sam : ARRAY ARCHITECTURE | 4 ‘The typloal UHB chip is composed of double columns of CMOS gates (basic celis) separated by dedicated wiring channels. A basle cell consists of a pair of N-channel and a pair of P-channel transistors Interconnected by polysilicon gate control terminals. Groups of baslo calls are interconnected by custom motalization Into unit cells, Fujiteu unit celle provide a wide range of standard loglo functions such as exclusive OR gates, filp-flops, buffers, and counters. The UHB Series CMOS Gate Array family includes over 250 different unit celle, These unit cells are the buliding blocks from which complex designs are constructed. The spaces between the double columns of basic cells are ocoupled by channels for custom metallization. Nearly half of those wiring channels contain transmission gates that implement internal 3-state buses. Bus terminators located at the ende of the double columns of osila maintain the last value to be sent through the bus to ensure proper operation under all conditions. ‘The I/O cells around the perimeter of the matrix of cells are composed of Internal calls with Input protection networks and the potentlal to be configured as input buffers, clock input buffers, output buffers, power output butters, or bidirectional buffers, GED ETD ewe vecccccccccsccrerecucsssececesececess Cad Gal = Reereereerennterere ree LL ' PSS Sie Slee ee o 126 2 S86 & BlSlieeP ‘ (RIBS BSB BS BlBlIB EH: 6

3 EBS 6S BSE] BS BSS

PP ———— pose [ocas ae PE eee = Typleal Chip Layout, Double Column Structure hw Dedicated Clook Network - for high frequency clocks a 3-state Bus Logie - located In wirlng channels a Bus Terminators - prevent floating state on buses a Driver Transistors and I/O Protection Networks - provide high 1/0 count

5 Double Columns ~ for optional macro utilization and speed

6 Wiring Channel Area - for metalization between unit cells . 117 j

FUJITSU MICROELECTRONICS 23£ D M@ 3749762 0010260 4 mm | en | MB62xxxx 9 FusiTrsu MB6Oxxxx =a DESIGN COMPONENTS DESIGNING WITH THE UHB PRODUCT FAMILY To Implement logic functions, the designer builds up the elements of the oircult from unit cells, Simple unit celle are used hierarchically to bulid higher level functions until the logic Is completely defined. Fujiteu offers a complete tine of standard logio funotione in the unit cell brary, ‘Soft macros are used to Implement large euper-cell functions such ae expandable ALU's and multipliers. VO BUFFERS Each UHS I/O butfer around the perimeter of the array consists of an input proteotion network and large N-channel and P-channel transistors capable of supplying the standard 3.2-mA, 8-mA, and 12-mA output currents, Two of these large transistor pairs may be connected In parallel, using high-output-current macros, to obtain 24-mA drive, One of the /O pads whose output transistors have been used for the 24-mA high-ourrent option may still be used as an Input, Input /O buffers convert external TTL levels to Internal CMOS levels or may receive CMOS level signals directly. Output 1/0 buffers are totem pole and may drive elther CMOS and TTL levels, depending on their AC and DC loads. Any of the pins except the dedicated power and ground pads can be designed to be an Input buffer, an input buffer with pull-up/pull-down resistance, a clock Input buffer, an output buffer, a high-drive output buffer, an output buffer with noise limiting resistance, a 2-state output buffer, a bi-directional buffer, or a Schmitt trigger input buffer. There are some restrictions on the location of 24-mA buffers, INPUT CLOCK DRIVERS ‘The large output I/O transistor pair Is used In a high-drive input clock driver for high fanout applications within the array. This allows the designer to fully utilize the high speed capabilities of the UHB technology. TESTING UHB DEVICES Two options are available for testing UHB designs: (1) the standard designer-supplled test patterns and test vectors (in Fujiteu's: FTDL format) and (2) the use of scan cells combined with Automatic Test Generation (ATG) performed by Fujitsu computers for additional diagnostic test patterns. If the designer has designed with scan celis and other scan loglo elements, Fujitsu wil complete the scan test program generation. Roegardiese of the selected test option, it Is the responsibility of the designer to furnish Fujitsu with enough test patterns to guarantee that the submitted design completely performs Its Intended logic functions. These patterns Include the designer's test function of each I/O pin. : a SS | § 2 = | COMBINATIONAL LOGIC Ea? Dm sel Ye pel = AS A Le | SOUT. Diagramatle Representation of Design Structure for Scan Testing 1-18

FUJITSU MICROELECTRONICS 236 D MM 37497b2 OO102b1 b mm T4Q-II-09 MB62: Us XXXX FUJITSU MB6Oxxxx am VDD and VSS REQUIREMENTS ee Each UHB Series gate array device has two options for each package type, both supporting a different number of power and ground ping, The number of power and ground pins required depends on the number of simultaneously switching outputs used in the design. Simultaneously switching outputs (SSOs) are output signals that change from H to L or L to H of from Z to H or Z to L within @ 20-ns window (Including possible skew). ‘Multiple outpute that switch at the same time oan cause noise on Voo and Vas lines and affect the performance of a device. ‘Therefore, to achieve maxknum reliability, Fujiteu mite the number of SSO per Voo pin according to the table below. The ‘maximum number of SSOs per pin is determined by a representative value specified for the driving capablity of each type of ‘output. The total representative value of all SSOs used in a design must not exceed 80 per Vss pin, For example, 11 normal 3.2-mA outputs with edge rate control, four 12-mA outputs, or three 24-mA outputs per Ves pin may be SSOs. | yer Output ee ee n a Normal (3,2 mA) with Edge Rate Control Ee eee with Edge Rate Control pwerce. | | with Edge Rate Control 1-19

FUJITSU MICROELECTRONICS 23— D MM 37497b2 OOl0eb2 6 mm MB62xxxx FusiTsu MB6Oxxxx Saal ESTIMATION OF POWER DISSIPATION In order to select a suitable ASIC package and determine system cooling requirements and eystem power supply requirements, the designer needs to estimate the power dissipation of the circult. Power dlasipation calculation in CMOS technologies Is compiloated by the fact that translent currents Involved in charging and dlacharging capacitances dominate the total power dissipation, Fujteu has simplified the oalculation of power dissipation by etudying a long history of designs to determine what typical olroult acthity constitutes, and by ebsarving the power dlasipation characteristics of individual gates as they operate. Those parameters are summarized below and are Incorporated Into the worksheet that folows. Pain) = 0,07¢mW/MHz palout) = 0.026mW/pF paleeg) = 0.20mW/MHz pdicomb) 9 ,03¢mW/MHz OV 5%) = 11 ‘The example below aseumes a system clock frequency (f) of 25 MHz for a clroult of 2700 gates with 90 inpute and 60 outputs, all outputs loaded at 20 pF. The clroult activity, that Is, the maximum number of Internal gates, inputs, and outputs that are simultaneously active, Is 20%. The mix of sequential to combinational gates fa 1:5 (20%). Note: P le in units of mW/MHz, except Pa(out), which Is In mW/MHz/pF. 1.0/0 AC POWER CALCULATION 1.1 Number of inpute 90 x freq _26/2 x Potin) x 20% » 16.49 mW 1.2 Number of outpute 60 x freq! 25/4 x load _20F x Po(out) x 20% = 91.25 mW

1.8 Total /0 AC (transient) Power eeeeeeenectcesneeccecensenseessss sf PACS AEE oan T

2,0 WO DC POWER CALCULATION 2.2 Number of 8 mA outpute _16 x (0,15 (lo. + IoH))= = 24 mW

2.8 Number of 12 mA outputs 0x (0,15 (lL + [0#)) = 2 mw

2.4 Number of 24 mA outputs Ox (0.15 (0.16 x (lo. + oH) = _9_ mW

2.8 Total 1/0 DG (steady state) Power sessesneecssnetesnseeessseeesseerss [P00 = B02 mW]

3.0 INTERNAL GATE POWER CALCULATION. 3.1 Number of used gates _2700_x % sq, 20% x freq 26/8 X Po(seq) = 237.8 mW 9.2 Number of used gates _2700_x % comb. _80% _ x freq? 26/20. X Poteomb) = _89.1_ mW

3.3 Total Internal Gate Transient Power Seeceeesteseeesnnnecsesssseese [PRES abe OW]

4.0 TOTAL CHIP ESTIMATED POWER DISSIPATION

ay Pr (typloal) = Pac _47,68 mW +Poo _80.62 mW + PNT 426.6 mW =_524.8 mW 42 Po(woret case) = Pt = 624.8 mW xCv 111 = 682.5 mW=_.6W W Notes: 1. itis assumed that outputs wil toggle at one fourth the frequency of the eystem clock on the average. : ion) term assumes ou w 5: itis Ssaumed ast any 20% of the combinational gates are ‘simultaneously active, and at a frequency of one fourth the clock frequency. 1-20

FUJITSU MICROELECTRONICS 23— D mm 3749762 0010263 T T42.-11-04 MB62xxxx Fusirsu MB6Oxxxx ill WORKSTATION DESIGN FLOW ——— SSSSSSSSSSSSSSSSSSSSSSSSSFSSSsSsSsSssSssssssssssssSe Fujitsu ASICe customers have a choloe of four popular CAE design packages (Dalsy, Mentor, Valid, and HP 9000) plus Fujiteu's own new Sun-based workstation software (ViewCAD) for schematic capture and design Implementation, The design flow process Ie summarized In the diagram below. The boxes outlined In bold indicate Fulltsu-supplied software that Integrates with standard CAE software to produce the data files necessary to implement a design. The design process flowchart Is somewhat simpler for ‘the Fujitsu (ViewCAD) software because ViewCAD was written specifically for Fujitsu's high-rellabllity design process. A design logic file and a test data file, known as Fujitsu Loglo Design Language (FTOL) and Fujitsu Test Design Language (FTOL), are the ultimate result of the workstation design process, Schematic ) Report, Checker | 1 | Logle Design LORC { : Rule check Head File | { Component Loy itt, Le [ae] Library/Models | {<= | Data Base File el 1 : pe ee ! _ = ! FOL | ee ease] Bess cma tede eee Desoription Lar Language Generator Hond Fie File Workstation Design Process . | 4-21

FUJITSU MICROELECTRONICS 236 D MM 3749762 OOl02b4 1 a MB62xxxx FusiTsu | MB6Oxxxx Sail | DESIGN IMPLEMENTATION FLOW T- 4a- | \\- o% eee After the workstation design process is complete, the FLOL. and FTOL files are transferred to the mainframe environment at one of Fujitsu's Technioa! Resource Centers. ‘There, the FLDL file Is checked by the Loglo Design Rule ‘Check (LORC) and a pre-layout simulation is ‘made using the test data generated In FTOL. Then, after automated layout takes place, simulation terun to validate the LSI funotlon. ‘When the design data Is validated, the design files are sent to the prototype manufacturing area where mask sete are fabricated and engineering sample devices are manufactured for test and approval. After the engineering samples are fully tested and ‘signed off, full produotion can begin. Customer Interface Fults Workstation Environment | Teale Beslan | 1 | | Ce) Mainframe Environment LDAC / SDRC. J r— | Eres rention [vy __t {or Correetons oo [rere —_] : Post-Layout Soan Test ‘Simulation Validation Manutacturing Environment | [—samoios ‘Approval and P.O. Post-Design Process 1-22

— nn FUJITSU MICROELECTRONICS 23— D M™@ 3749762 0010265 3 mm ‘T-42.-]|-09 MB62: FUJITSU XXXX MB6Oxxxx Sa FUNCTIONAL INDEX OF UNIT CELL LIBRARY eee Note: The load unit (¢y) Ie @ normalized loading unit of capacitance representing the input load of an inverter without metal interconnection, oe nen es ee [VIN verter es [vag Power inverter a eg [Vit Double Power Inverter Ts eg eS CT a eT [__ppg | True Delay Suffer > ns) | st dP CS [B04 Delay Cot ang) as Pos [aps Delay Coe tons) et Pos | Staak Buller Ramliyscs ee eee eee So ee mca [kt True Clock Butter Pos [Kap [Power Clock Butters Po [Kaa [ated tack (ANDY Batter 28 os [8 ator Crock (0) Buffer a8 Po [Kea -Gated Clock (WAND) gutter [3 | ——s8 | eg] [Kaa Block Crock (OR) Butter Pos | ‘Nie’ | __ometpen | oasercate | omeren| | , [Nan einput NAN pn Ne Power 2-input NANO [Nak Fast Power 2-input NAND [NaN Sinput NANO [Nae Power S-input NANO a [Nag | Power ainput NANO [Neg | Power é-input NANO 86 [Neg ower @-input WAND [Nog | Power $input NANO [Nog [Power 2-input NAND to se [Nag | Power 16-input NAN [Nak | Fast Power S-input WAND [8 [hart Power top NANO 8 1-23

oO ——E—EOEOEOEOEoOEOEOO FUJITSU MICROELECTRONICS 2@3£ D MM 37497b2 OOLO2bL S mm | a MB62xxxx Fusirsu MB6Oxxxx aaa | FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) T 42-11-09 ahr sien i in [ates | cansten [emote | omer] | [men | @inptNoR TTT [8 For pt ORs [Ra Power einput oR [RN inp WOR [8 ewer apa ORs [aK Foner Sng NOR a Al A | ae a ST a | A [R98 Povo ent Rts [8 Por aint NOR [va [ower s-nput NOR 1 | [Ros [oar ta-nput NOR 0 Miran 26 ee ee ee ee [Mites | __omroton——[ eaccate | omen] | | [eer input AND | [a oat AND | [| teece | onsrston | saavents | omen] | a AS | eT, . [aie [Power input OR se Ean MONO my EOE ae ae ee [atc | cnsanten | sasrents | ore can] romrr | [xin eater eg [xt | Power exatustve NOR 8 ea | a SK A [van srinpit exotuave NOR og a OLE a [xa rout Excuse OR es [oe [Power Sinput Exel ORE E88 roe 1-24

FUJITSU MICROELECTRONICS 236 D MM 37497?b2 0010267 7 mm T4Q-11-O% a MB62xxxx FuurTsu MB60xxxx Samm FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) AND-ORsinvertée Family (AQ) [0232 AND Into 2 NOR AO! a | [034 BAND nto BOR AO a [834 AND into SOR AOE 0 | bs 2 AND Into 3 NOR ACT [0442 OR Into 2 AND Into @ NOR AOT a a Note: AND-OR-Invert unit cells are useful in implementing sum-of-produots (SOP) expressions. LOR-AND=Invettet Fanlly OA) Se ee a ee er [S25 | one a WAND OA | S14 to 2 NAND OAT [e422 OR into 2 AND AT 0 : [as [2 oR nto @NAND OAL [oe [AND nto 7 OF nto NAND OA Note: OR-AND-invert unit cells are useful in implementing product-of-sums (POS) expressions. /Mulliplese Family ee os ee ee [rae [at | Powers, 2 ANOotnio 4NORMutplowr «| «|S *dYC [126* | 6:t_| Power 6, ANDs into 6 NOR Muttplexer [10 | 38 sor | [-~r25* [ait [Power 8, 2 ANDs into @ NOR Multpiexer [| 11_| #8 | _sor__| [a2 [ait [Power 2, S'ANDs into @ NOR Multiplexer [|| 8OP | . [154 |i [ Power 4, 3 ANDa ito 4 NOR Multiplexer [8 | _38 | sor} [42 | ait [Power 2, 4 ANDs into 2 NOR Multiplexer a [tag [Power 3, 4 ANDs Into 9 NOR Multiplexer | 08 [T4441 | Power 4, 4 ANOs Into 4 NOR Multiplexer [1 | a8 | sor [te | “ait [Power 2, 2-8-4 ANDe into 4 NOR Muttiplaxer [10 | s0 “sor | [vee [4st | Power 4. 2 OR into @ NAND Multploxer [6 [a8 Pos [__U26s [eit [Power 6, 2 OR into 6 NAND Multiplexer [ga Pos | [039 | ait [Power 8,3, OR into S NAND Muliplexer [7 [96 Pos [var | ait [Power 4,3 OR Into 4 NAND Multiplexer | | 38 «POs | [045 |“: | Power 5, 4 OR Into" NAND Multiplexer | 3 [a8 | Fos [vet [et [Power 4, 4 OF Into 4 NAND Multiplexer [at aa Pos | * Convenient for typical multiplexer applications 1-25

FUJITSU MICROELECTRONICS 23— D M™ 3749762 0010268 9 mm a MB62xxxx Fuurrsu MB6Oxxxx Sl } TH4Q.-11-A | FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) | Sn eS Eo es [rze | 2:1 | Soleotor | 6 | 18 | s | xg [2 [ter | 2:1 | Selector | 8 | @ | s_ [xq [4 [teat [2st [ Selector | 2 | 8 [sx [xa [reer [-ait_| Selector [4 | 18 SxS xa ed Type | Desoription Outputs Enable [bee [24 | Desower | 5 | te | tow [| — fT [oes | 3:8 | Decoder | 16 | 14 {tw | ~— fT [pes | 2:4 | Decoder | 8 | t4 | tow [| tow Ri [255° non meron | 2 | wi [ ewe | ome | | [en | sokeus omer | 6 | 98 | aote [tow Notes: 1 The number of B41e used Is imited by the chosen array series, a8 shown In the table below. 2, On-chip buses (managing more than one bus source and/or a bi-directional bus) my, be Implemented with - either multfplexer-type unit celle or bus drivers. While bus drivers impose certain design restrictions, the optimum choice Is dlotated by the specific design. ae | essouns [es a a [erreurs [| [_e-zz0una [se ‘ | c-acoouns ft | Lesvoouns | ae [ceswos [=| 1-26

FUJITSU MICROELECTRONICS 236 D M@ 37497b2 0010269 0 mm T-42.-11-09 a MB62xxxx 9 FuuiTsu MB60xxxx <a FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) —___ enn eee [ Dalatalch nly ee ee ee | Basio Desoription Cells: Drive (¢u) Clear [ver | ata caten wat [88 a a [via] Bata Cater wn tM [988 gt | a {urk | Datatateh te tow a xa Asyne | | ttt | Data Latoh with Gear [6 te tow a. XQ syne | [tr] bata Latch with Glear | _4e |__| tow [4 [axa | — | [tri —T's-nateh wth Giear_ [4 | 1] tow] 1a. xa | anno] |_tra | Bata tatoh ae 8 tow [sa xa | Sean Filp-Flop Family (Posilive-Edge thlegered) = | | commen | att | aye | onl oan | cm | nn $6 Description Calls |__Sou*_|"Soan 0 FF with 4:1 Multiplex [YS [as Pt, XQ | Asyno | = Yes | [“SOK*_[ Sean DFR with 8 Mutsiex [te | 86 | 1 | a. xa|_Asyno | =| You] [sun [sean cK EF fe a8 a xa] Ayn |= | You —| | _sbb* ‘Scan DFF with 2:1 Mutinlex [16 [a6 ta. XQ | Asyno | Aeyno | Yes _| [SoA [sean tanput OFF [a 88 axa f= vos | | soe [Scan t-inout DFR ae a xa = = von | |_SHA['Soan t-input DFR | ea te 8 [axa [= = ves | | [st | sean input 0 Fe ir | ) | SHO | Scan i-input DFR ete fe xa = Vos | | [sti] Sean 0 FF wih 271 matbion | 7a—[ tae [ a, xa =| =| vor] | [SH | Sean D FF with S:¥ Muttplex [ate [8 [axa [=| =| ves _| | | 1-27

SS aa SSS... eaE“(€&:-aaxz FUJITSU MICROELECTRONICS 23E D MM 3749762 0010270 7 me T-4Q-} \\ - MB62xxxx 9 FUusITSU MB6GOxxxx Sl FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) et Min i ee eee eee Basico Drive Clock Description Cells (du ) Edge Non-Soan D FF with Set [7 | wif axa | — | asm | pos | [rom | CNon-soanDF dt | te | ct | xg | = [= [Pos | [Foo | Non-Soan D FF wihfewt | _7 | 18 | 1 axa | “Awnol — | Pos | [Crop | Non-Sean D FF with sot andRest | 6 | 18 | 1 | axa | Asyno| Aayno | Pos _| [roa [-Non-scnDFF | tT te | 4 | QP = Neg [FOR | Non-SoanDFFwthciar | 26 | 18 | «| a [| Agno| = | Pos | [Fos~[ Non-SoanDFF SSCS | te fT a | TP = Pos [FD2~[-Non-Sean Power OFF —+| 7 | 3s | 1 | axq | — | — | Neg | | [3 ~[ Non-Soan Power D FF with Presst | 68 | as | 1 | axa | =| Asyno | Neg | Non-Sean Power D FF with Clear and Preset Asyno Le5s—[Non-sean Power O FF wih Gear—[e [ss | 1[ axa | Asyno| — | Neo | Non-Sean Positive Edge Clocked : Power J-K FF with Clear Note: Synchronous filp-flops my be constructed by adding a ‘simple AND gate (such as N2P) to the Input of a flip-flop to create @ synchronous clear. [Eray Conner tn en someway fala [ [2a lanl [ela fa Up Counter with Parallel Load co (Ss) Io! Down Counter with Parallel Load E} a [eri —[ Non-Sean Fip-Fop for comter | 11 [ 18 | —[ axa [— |- | ~ |- [= | Nan-Sean 4-bit Binary ~ [oT ero Lawl wl alow [= fowl — |- [wo | ‘Non-Sean 4-bit Binary Synchronous Counter Up syrereoun Up Cau [ve | «{ a.cote| sme [anne oun | aon | ve | Synchronous Up Counter Asyno| High ea La femal mmo p Counter 9 Up/Down Counter, Q, co. Low Notes: 1. (8), (A) indicate the counter Is (S)ynchronous or (A) synchronous. 2. Scan counters Include clock inhibit and high drive (CoA = 36 £u). For non-Sean counters Con = 16 £u, 3, C11 may by used for purposes other than counters. . 1-28

—— ee FUJITSU MICROELECTRONICS 23£ D MM 3749762 0010271 9 | | T4.2-11-9 | sere MB62xxxx 9 FuurTsu MB60xxxx = FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) $$ ee ; Drive Clock Deseription (tu) Polarity Serlal-in Parallel-out Shift | crea | Register Serial-in only ‘Shift Register with ‘Shift Register with: Asynohronous Load Asyne-Low. Serlal-In Parallel-out Shift Datapath Operators (Adder, ALU, Parity) = = Bit Ed ee ee [AIA | i-btHaitAdder CdS | 6 | 1 | S,co. | ~*+Y | “Ain [abit Ful Adder te cor [Aan | 2-ait Ful Adder te | a ff s.co id id | pos | Odd Party Generator/Checker__ | _i@ | @6 | s | ooo, VEN [ | | Pos | Odd Party Generator/Cheoker | 18 | 18 _| 8 | obo, even | — _| [|_Po8 | Odd Parity Generator/Checker “| 22 [te |e | ono, even [| Miscellaneous Celle = ee a ee [200 ig ees [zor ip tet Yoo 1-29 i i

FUJITSU MICROELECTRONICS 23— D M™ 3749762 OO10e72 O mm T-4.Q -11-09 MB62xxxx 9 FusiTsu MB6Oxxxx EE FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) ee Mien ae ee [BL] owe ar Lage | tes |_| Cell Desoription Drive Output Name (éu) Type Polarity ne Input Buffer TTL Slonal BU 118 with Pull-up Resistance TT ‘Signal 180 118 with Pull-down Resistance Tre Signal : RB Input Buffer TTL Signal True . i2aU | 128 with Put-up Resistance TTL Signal True : 18D 128 with Pull-down Resletance Tm Signal True, ) 1KB ‘Clock Input Butfer 72 TTL Clock IKBU Ikb With Pull-up Resistance 72 TT Clock 1ka0_| Ike with Pull-down Resistance z_| orm look 18 ‘Clock Input Buffer 72 [TT Clock True ILBU ILB with Pull-up Resistance ced TTL Clock ‘True

80 ILB with Pull-down Resistance 72 TT Clock, True

1 | "CMOS Interface Input Buffer 36 [GMOS | Signal ies | 11C with Pull-up Resistance 36 Signal 11C with Pull-down Resistance 36__| cmos | signal ‘CMOS Interface Input Buffer 36 CMOS Signal True 12¢ with Pull-up Resistance 36 | cmos | Signal True : 126 with Puil-down Resistance 36 CMOS | Signal True "Ws ‘Schmitt Trigger Input Buffer ‘CMOS ‘Schmitt Invert su 11S with Pull-up Resistance ‘CMOS ‘Schmitt Invert 1iso_|__ 11S with Pul-down Resistance cmos | schmitt | tnvert as ‘Schmitt Trigger Input Buffer ‘CMOS ‘Schmitt ‘True (28u 12S with Pull-up Resistance Mos ‘Schmitt ‘True sb 128 with Pull-down Resistance CMOS Schmitt True HR ‘Schmitt Trigger Input Buffer TTL ‘Schmitt iiAU | ITA with Pul-up Resistance TL ‘Schmitt HWRO IR with Pull-down Resistance TTL Sohmitt . aR ‘Schmitt Trigger Input Butfer TTL ‘Schmitt True WRU | 12R With Pulkup Resistance TL Schmitt | True 12n0_| _12R with Pull-down Resistance Tm Schmitt | True Indicates a pull-down resistance of the equivalent value. 1-30

ee e&e§'\\|eeerrr | FUJITSU MICROELECTRONICS 23—E D M@@ 37497?b2 00102073 2 | | ee eel MB62xxxx FuurTsu MB6Oxxxx mm FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) [Ouipit Butter Family ce ee eee Edge Input? Loglet Rate ‘Output Deseription Level Type__| Control | Polarity | [ore | Output Butter __ a a.ama[rrLicMos | “Standard [No [invert | [Power Output Buffer [3 [rama | TTt/oMos | Standard |" No | invert | [ots |" Power Output Buffer "|S i2mA | TTL/CMOS [Standard |" Yes | invert | [028 [Output Buffer sama rrticMos | standard [No [True Power Qutput Buffer | 2 fama | Trtomos [standard [No "| True | [osrs [Output Buffer 32m Trtvemos | s-atate [No [True] | o4st_ | __Power S-state Output Buffer | 6 | 12mA | [oi [Output Butters | TrLcmos [standard [Yee “| invert | [o2R [Output Buffer a sama Trucmos | standard [ves [True | [_OsRt [Output Buffers Sama TTLCMOS | Setate [Yes | True | | o2s2 | High Power Qutput Buffer [7 6 | ama | TrLcMos [Standard | Yee | True | |_o4s2' | High Power Output Buffer [7 24ma | truvcmos | a-state__| Yes [| True | | ofer [Output Buffer sama rrtcwos [standard [No | invert | [oine [Output Buffer Sema | TTLcMos | Standard | Yes |" invert | | o26F [Output Buffer 2 ama | TYLicMos | Standard | No__| True | | oanF | S-state Output Buffor ee ee | o4Tr [___S-state Output Butter [4 [ama Trtcwos | Sstate_[ No__[ True | Note: 1. While all outpute are totem-pole type, Open Drain and Open Souroe types can easlly be defined for all 3-state type outputs, EXAMPLE OF OPEN DRAIN OUTPUT 1 :

1 R pulp (min) = Vop (max) IN x OUT

Zot oat ft | oy (rated) ° L L PROVIDES our 1 z 4 WIRE AND VIN eT t IN ; INTERNAL EXTERNAL EXAMPLE OF OPEN SOURCE OUTPUT ' R pulldn (min) = Vop(max) IN xX OUT PROVIDES vin pot Vor (rated) WIRE OR 0 4 H our 1 2 L 200 \\ INTERNAL 1 exTERNAL Note: 2, Totem pole outpute, suich as these buffers have, can drive both TTL and CMOS levels. Voltage margins depend on actual source or'sink current (ee DC specifications). 1-31

FUJITSU MICROELECTRONICS 23E D mm 37497b2 010274 4 mm | T43Q-11-09 — | MB62xxxx Fusrrsu | MB6Oxxxx maa | FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) ; ae tea a acca a iS = Le Ef ele fe |e Drive Loglo Rate Output ; Desoription OL) Level Control Polarit) HeT 3-state Output and Input Buffer TT True HeTU H6T with Pull-up Resistance TTL True H6TD HET with Pull-down Resistance TTL True HEW ‘Power 3-state Output and Input Buffer 12mA TT True HewU HW with Pull-up Resistance 12mA TT ‘True HEWD HEW with Pull-down Resistance 12mA TTL True ‘HEC ‘B-state Output and CMOS Interface input Buffer 3.2mA Mos: ‘True HECU H6C with Pull-up Resistance 3.2mA cmos True 1 | HéCD H6C with Pull-down Resistance 3.2mA. cmos True ‘HEE ‘Power 3-state Output and CMOS Interface Input Buffer 12mA ‘CMOS ‘True HEU H6E with Pull-up Resistance 12mA ‘CMOS True H6ED H6E with Pull-down Resistance 12mA cmos True Hes: ‘G-state Output and Schmitt ‘Trigger Input Buffer 12 3,.2mA CMOS ‘True ‘HESU HGS with Pull-up Resistance 12 3.2mA CMOS: True HésO H6S with Pull-down Resistance 12 3.2mA CMOS True : oR 3-state Output and Schmitt . | | wan iele ls [sl HERU HER with Pull-up Resistance 3.2mA TTL True H6AD HER with Pull-down Resistance 3.2mA_ TTL. True H8T ‘3-state Output and Input Buffer 9 3,.2mA TTL Yes True : H8TU H8T with Pull-up Resistance 9 3.2mA TTL Yes True . H8TO. H@T with Pull-down Resistance 9 3.2mA. TTL Yes True Hew ‘Power 3-state Output and Input Buffer 12mA TTL Yes True HeWU HW with Pull-up Resistance 12mA Tm Yes ‘True H8WD H8W with Pull-down Resistance 12mA Th Yes True H8W2 High Power 3-state Output and Input Buffer Ww 24mA ‘TTL Yes: ‘True ‘HeWt HeW2 with Pull-up Resistance W 24mA TTL Yes True H8WO H8W2 with Pull-down Resistance Ww 24mA. TTL Yeo ‘True HEC ‘F-atate Output Buffer and CMOS Interface Input Buffer 3.2mA CMOS Yes True HE8CU H8C with Pull-up Resistance 3.2mA cMOS Yes ‘True . H8cD HC with Pull-down Resistance 3.2mA CMOS Yeo True ‘a *D" Indioates a pull-down resistance of the equivalent value. 1-32

FUJITSU MICROELECTRONICS 236 D M@™ 37497b2 0010275 b . THQ -1-04 | a MB62xxxx Fuurrsu MB6Oxxxx i FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued) -Bldlrectignal 10 eulfare. (Buses) continued = 2 LE | eswinn est | sus [ |B |B | Drive Logie Rave Output Description (ol) Level Control Polarity : HOE Power 3-state Output Buffer and Interface Input Buffer 12mA CMOS Yes ‘True HEEU H8E with Pull-up Resistance 12mA CMOS Yes True H8ED H8E with Pull-down Resistance 12mA CMOS Yes True ' H8E2 High Power 3-state Output and Input Buffer 24mA MOS: Yes True HeE1 H8E2 with Pull-up Resistance 24mA ‘CMOS Yes True H8EO HGE2 with Pull-down Resistance 24mA, cmos Yes True iS ‘$-state Output and Schmitt ‘Trigger Input Buffer 3.2mA MOS: Yes True H8sU H&S with Pull-up Resistance 3.2mA Mos Yes True H8SD H6S with Pull-down Resistance 3.2mA MOS Yes True ‘Trigger Input Buffer 3.2mA TTL Yes True H8RU H8R with Pull-up Resistance 3.2mA TTL Yes True HERD H6R with Pull-down Resistance 3.2mA_ TT Yes True HOTF 8-state Output and Schmitt Trigger Input Buffer TTL True H6TFU | HSTF with Pull-up Resistance TT True HSTFD | HSTF with Pull-down Resistance TTL True HECF 3-state Output and Input Buffer MOS True H6CFU | H6CF with Pull-up Resistance H cmos H6CFO | HSCF with Pull-down Resistance MOS True HET ‘3-state Output and Input Buffer TTL Yes: True H8TFU | H8TF with Pull-up Resistance TTL Yes True H@TFO | H8TF with Pull-down Resistance TTL Yes True . HSCF ‘3-state Output and Input Buffer CMOS Yes True H@CFU | H&CF with Pull-up Resistance cmos Yes H8CFD | _H8CF with Pull-down Resistance CMOS Yes True aera ie | [ie| sow [ose | Basic} Loglo Description Cells | Level | Foe | ‘Output Buffer for Osollator and | + | cmos _| Input Buffer Output Buffer for Oscillator and Schmitt Trigger Input Buffer TTL ‘Output Buffer for Oscillator with [| esetreamce |e | ows | [io [ et eter fr Oseier ef = 1-33

OOOO EEE EEEEEEEEEEEEEEOEOEEEEEEEE— FUJITSU MICROELECTRONICS e3— D M@ 37497?be 0010276 6 mm T-42Q.-1-09% MB62xxxx FusiTsu | MB60xxxx Sama Avallabllity Characteristics of UHB Gate Array Packages | Laere | oe-ter-won[ oe-tec-oos[ 1 [2 [ss a LS a a [oexe | o-tep-wor__|_oee-cor | ea A a Lowao | oir-aap mon peeoo-cos |e ae a a A A Pe LE ee Ss A ce a NT a a a a a Low-2e | pie-aap-we_——|_o-aec-coa [ee rE orserwos fT as a a A ee as ae oe a a a a ee A ec ee a a a a a a bora | oraeor [orca |e fe Te es a a a a [oT Fiastlo—_[Ceramio | of Vde_} of Vee. Signal Pins a a a Ss a a a a en a A a a a a a a ae a Se Se a Se A ' ee a a | a a a ee a A Subject to Change i 134

FUJITSU MICROELECTRONICS 23£ D m@ 37497?be2 0010277 T | T-4Q-1-A MB62xx: XX FUJITSU | MB60xxxx Avallability Characteristics of UHB Gate Array Packages —— SSS [ Dual: In-line. Packages. (Skinny DIP, 300mil Body Width). = : ‘Available . Pinout Code Package Code Number] Number | Number of [——Fastio—[Cearammi-| ot vad | ot ves_| signal Fine a OS LS | bip-2esk eee | a | | Elatpack Packages (Dual-leaded) = : Available | Pinout Code Numbor [~~ Flestie[~cararnte| of vad | of Vae_| signal Pins a 1 | CS rr I OO [-ret-20 | Fer-2op-Mon— [tr [eer-200 eee A A a A | rpt-2g | pr-2ep-mot [a Flatpack Packages (Guad-Leaded Available Pinout Code Number] Number | Aumigorot | Fiastio [Ceramic “| of Vaa_| of Ves_| Signal Pins LL ON DO LS a eC : A | aL a cc Se i A SO | Fet-46 = eee a PS A EC A [Fpr-e4u | FpT-7op-moi fae |-Fereo | Fet-soe-mor [a re [ret-eou Pee eee |-eBr=i00 [Fer=to0p-Mon [ae LS a ee Oe SO OO En Se OC S a eS A TO | CC OE TS | PL OS | : * Small body size, ‘Subject to Change 1-35 j

FUJITSU MICROELECTRONICS 23E D MM 3749762 0010275 1 mm T2108 MB62xxxx FusITSU MB6Oxxxx Saal Availability Characteristics of UHB Gate Array Packages Sli ae nc [ bin Grid Acre POA TIMlooOMILPIN PCR) | Package Code Number | Number | Number of #Vadd" | ¥Vae | Signal Pina rane SSCSSSCSC~* CsA] se [rae SSCS Cd [Paa-ee [ranma 8 a a A A | Sc OG A a AS LA [paasiva—— fp TC oT LL a CS A PC cP 1 | Eaate Panay Guo ee Avallabl [-——Fiasilo_[-Geramio—| of vad_| ofves_| Signal Pins [ieezeSSS~*d Catone oe a [OO [tco-as [i reac | a ae a LV ON SO [teow | SSCSCSC~w Cee] eT [tec a a LS SN a a SN A a a eS SZ i piacile Landed Chis Giulels @lece Sumi pich == ee . ' Avaliable [—TFisatio —__[_Geramio | of vaa_| of Ves_| Signal Pins Ee Se ce ce La a A | a Sc A a ‘Subject to Change 1-36

. FUJITSU MICROELECTRONICS @3€ D MM 3749762 0010279 3 mm T4.2.-{1~0% | eee MB62xxxx Fusrrsu MB6Oxxxx = PACKAGE AVAILABILITY ———— PACKAGE OPTIO UHB UHB UHB | UHB UHB UHB UHB UHB UHB UHB UHB {sitet etefe{ecfe[ofeleteleyvelolelolTeloTrlolr [cl e| SDIP 28 fee BETTE TT EET EEE EE (SKINNY) 24 with leads on 20 two sides of = 24 the package 28. with leads on 48. four sides of | 48* ithe package = 64 100 120 160 135 179 208 258 © = Coramio ‘: avalable now P = Plastic 0: under development * = 48-pin FPT, smaller than the other 48 FPT 1-37 i

NICS 23 D MM 3749762 0010280 T mm MB62xxxx FusITSU MB6Oxxxx il PACKAGE DEMENSIONS Sada 286-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE (CASE No.: PGA-258C-A03 1.008 ‘c,04011,02)TYP 018-003 pig .050(1.27)D1A TYP. (aPC) (06'3.13) HPLCS) $o05500900090099009 . $$$$9000090000909989 ©0909O0O0O900000008 ) f 8999009090900009999 $880 °9°8 8 © 9990 @000 Q009 80000 090098 Q000 @000 1,800(45.72) geese gees REF 30080 09099 9999 299 @0000 00000 8528. 9.2.8 .8088ee8 99.999090909900009 INDEX AREA | a) Sees seesacsesseness $990000099990908099 A Q9099O9090999900098 1008.010, 760,042055 Tai 9980285 ol 2806.38) 1130010 wax (9.s0193e) Dimension in

1988 FUJITSU LIMITED A2660038-1C inches {rniimeters)

| 1-38

FUJITSU MICROELECTRONICS 23E D MM 3749762 001026) 1 mm T-4Q-(\\-o4 a MB62xxxx Fusirsu MB60xxxx Sma PACKAGE DEMENSIONS (continued) platen his ri A a Wp, <3 ee ott | DN as Rex ett! Tet 208-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE (CASE No.: PGA-208C-A02 100,010 050(1.27)DIA TYP (2.642028) (aPLcs) . ESOOOO 8889988998 © ©9099 90990900000) a IOOOQQOO0GOGO900008) 29900090090 000009 — 000 QO00) =) loooo 9000) | B3es 38 1.600140,64) ; 900 ( ) js099 4 9000 ns O00 \\10096) Ted 120000900009990000) INDEX AREA. OO OO9O99090 000000 4 ———— DODOOO HO O9ODOOOOOO +008 ©09099009000909090909 143.002051°° 1} ssatcre Gr 27028)" Tg 9h, .240(6.10) Dimension in MAX inches (millimeters) ©1987 FUJITSU LIMITED Az080025-16 1-39

FUJITSU MICROELECTRONICS 236 D MM 37497be 0010262 3 mm T-E2 09 MB62xxxx Fuurrsu MB6Oxxxx ll PACKAGE DEMENSIONS (Continued) ii ace sc

160 LEAD PLASTIC FLAT PACKAGE

(CASE No.: FPT-160P-M01) a 1102028.) iva, i ; sy Eliane |B ‘ear a I taczae.0 | iS Bt HB] wwoex O BE | E Bl of F aah 1 | _ Fe .0101min . NTU ate aD a Wen esl ath “ V"STAND OFF ae | {sats 28 (© 1988 FUJITSU LIMITED F1600018.26 inches (millimeters) 40-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No,: DIP-40P-M01) 8 Max . ena ae woexl retry Rite fare Sines 9012. 200ax ce ce WUNSRURENURDSURUNURUAUSURORDSUNGEUAUADEEE: nie FRE soonsairve, | Lata || ose siesta tees runtau unsrreD oaoess.16 | 1-40