MB40D001

MB40D001 FUJITSU | Alldatasheet

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DS04-13514-2EFUJITSU SEMICONDUCTOR DATA SHEET Linear IC Converter CMOS D/A Converter for Digital Tuning MB40D001 n DESCRIPTION The MB40D001 is an 8-bit D/A converter with 12 built-in channels. The 12 sets of analog outputs have built-in OP amps to enable use with large current drive applications. CS (chip select) data input/output format is used to enable connection to a serial bus. A built-in 12-bit I/O expander provides serial <=> parallel conversion (8 of the 12 bits are also used with analog output). The MB40D001 can be adapted for microcontroller port expansion, or replacement of electronic volume control or semi-fixed calibration resistance. Also, the MB40D001 is function- and pin-compatible with the MB88146A, for easy replacement when reducing sysytem operating voltage. n FEATURES

• Supply voltage 2.7 V to 3.6 V (Power consumption 0.7 mW/ch typ.)
• Compact package: SSOP-24
• R-2R type 8-bit D/A converter with 12 built-in channels
• Built-in 12-bit I/O expander (8 of 12 bits also used with analog output)
• Built-in analog amplifier (sink current max. 0.4 mA, source current max. 1.0 mA)
• Built-in power-on detector circuit (detects VccD power-on, and performs initialization)
• Separate MCU interface power supply (VccD), OP amp supply (VccA), D/A converter supply V DD
• Analog output range 0 V to VccA.
• Serial data input/output operation to maximum of 2.5 MHz (1.5 MHz in cascade operation)
• CMOS process n PACKAGES 24-pin plastic SSOP (FPT-24P-M03)

V CC A CS SO SI CLK D D 1 D 2 D 3 VCC D VDD AO AO 2 AO 3 AO 4 D 11/AO 5 D 10/AO 6 D 9/AO 7 D 8/AO 8 D 7/AO 9 D 6/AO 10 D 5/AO 11 D 4/AO 12 (TOP VIEW) SSOP-24 (FPT-24P-M03)

*1: Be sure that VCC A ‡ VCC D, and that VCC A ‡ VDD . *2: Do not leave this pin in floating state. Pin no. Symbol Description 1 to 4 AO 1 to AO4 D/A converter analog output pins (VDD -GND output). (Default state: #00 setting level output) 5 to 12 D 11/AO5 to D 4/AO12 I/O expander parallel I/O pins (VccA/GND output 0.5 VccA/0.2 VccA input), also used as D/A converter analog output pins (V DD - GND output). Pin state is controlled by input data. See “Data Configuration”. (Default state: Input mode, high-impedance state.) 13 VDD *1 D/A converter reference power supply pin. 14 VCC D*1 MCU interface power supply (Power supply for I/O expander). 15 to 18 D 3 to D0 I/O expander parallel I/O pins (VccD/GND output 0.5 VccD/0.2VccD input). Pin state is controlled by input data. See “Data Configuration”. (Default state: Input mode, high-impedance state.) 19 CLK*2 Shift clock input pin. When CS = “L”, SI data is loaded into the shift register at the rise of the shift clock signal. 20 SI*2 Data input pin (serial input pin). Used for 16-bit serial data input. 21 SO Data output pin (serial output pin). First-bit (LSB) data from the 16-bit shift register is output in synchronization with the fall of the shift clock signal. When CS = “H”, this pin is in high impedance state. 22 CS *2 Chip select signal input pin. Input to shift registers is enabled when the CS signal falling edges. Shift register contents can be executed when the CS signal rising edges. 23 VCC A*1 Analog unit power supply pin (Power supply for the OP amp.). 24 GND Common GND pin.

-+ + + +-- - CS SO D 0 D 1 D 2 D 3 GND SI CLK VCC D VDD VCC A DF DE DD DC DB BA D9 D8 D7 D6 D5 D4 DF DE DD DC DB BA D9 D8 D7 D6 D5 D4 DF DE D5 D4 CNTL DF D8 DF D8 DF D8 DF D8 DF D8 DF D8 DF D8 DF D8 AO 1 AO 4 D 11/AO 5 D 4/AO 12 16-bit shift resister & controller Data bus I/O expander 8-bit latch 8-bit latch 8-bit latch 8-bit latch Ladder circuit Ladder circuit Ladder circuit Ladder circuit R - 2R R - 2R R - 2R R - 2R

1. Data Configuration 2. Channel Select D3 D2 D1 D0 Function

0000 D o n ’ t C a r e / s p e c i a l f u n c t i o n

0001 A O 1 selected

0010 A O 2 selected

1011 A O 11 selected

1100 A O 12 selected

1101 I / O e x p a nder (serial fi parallel)

1110 I / O e x p a nder (parallel fi serial)

1111 E x p a n d e r s t a t u s r e g i s t e r ( E S R )

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB (last) LSB (first) Setting data Channel select

1. Setting Data

• Don’t Care/special function (Channel select = “0000”)
• : Don’t care *: Hi-Z output on all channels of AO5 through AO12
• D/A Converter (Channel select = “0001” to “1100”)
• : Don’t care *: Only AO5 through AO12 output is valid DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 Analog output voltage level to to to to to to to to to to to to Don’t Care

000000001100 G N D ( a l l c h a nnels)

000000011100 V DD /256 · 1 (all channels)

000000101100 V DD /256 · 2 (all channels)

to to to to to to to to to to to to to

111111101100 V DD /256 · 254 (all channels)

111111111100 V DD /256 · 255 (all channels)

• ······· 1101 H i g h i m p e dance (I/O expander state)*
• ······· 1110 R e s e t ( s t a t e w h e n p o w e r i s O N ) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 Analog output voltage level

000000000000 G N D

000000010000 V DD /256 · 1

000000100000 V DD /256 · 2

000000110000 V DD /256 · 3

to to to to to to to to to to to to to

111111010000 V DD /256 · 253

111111100000 V DD /256 · 254

111111110000 V DD /256 · 255

• ······· 0001 H i g h i m p e dance (I/O expander state)* to to to to to to to to to to to to Don’t Care

• I/O Expander [Channel select = “1101”]: Serial fi Parallel Conversion Performs parallel conversion of data bits D4 to DF for output on pins D0 to D11. Note that only those pins designated for output in the ESR (expander status register) are output.
• I/O Expander [Channel select = “1110”]: Parallel fi Serial Conversion Writes data from D0 to D11 pins to bits D4 to DF in the shift register. Data is output to the SO pin on the shift clock (CLK) signal (The first 4 bits output data D0 to D3, so the converted output should be read as data bits 5 through 16.). Note that the data value is “0” for pins designated for output in the ESR (expander status register) as well as analog output pins.
• Expander Status Register [Channel select = “1111”] Setting Pin status “0” • Input standby status (Hi-Z output) 11 to D4 pins used for analog output should be set to “0”. “1” • Output state DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 flflflflflflflflflflflfl D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Shift register Parallel I/O pins (output state) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Shift register Parallel I/O pins (output state) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 flflflflflflflflflflflfl D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Shift register This register sets the status of each pin. ESR

Note: After power VCC D is turned ON (or after a reset), the state of pins and registers is as follows.

• ESR settings have priority in determining pin states. Switching between input standby state and analog output state is enabled even when the ESR value is “1”. When the ESR value returns to “0”, the pin returns to its previously defined state. In input standby state with AO set for Hi-Z output, the AO output setting can be used for transition to AO output state. Pin State AO 1 to AO4 “L” output D 11/AO5 to D4/AO12 Hi-Z state (input state) D 3 to D0 Hi-Z state (input state) Register State Shift register Bits DF to D8 are “0,” and D7 to D0 are not defined (retain prior state). D/A register All reset to “0”. Parallel output register Not defined (retain prior state). Expander status register (ESR) All reset to “0”.

n ABSOLUTE MAXIMUM RATINGS * : VCC A ‡ VDD WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. n RECOMMENDED OPERATING CONDITIONS Note: Data in registers is retained in standby mode (digital supply: VccD voltage, analog supply: GND). WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Conditions Rating Unit Min. Max. Power supply voltage VCC A Based on GND (T a = +25°C) –0.3 +7.0 V V CC D –0.3 +7.0 V VDD –0.3 V CC A* V Input voltage 1 V in1 SI, CLK, CS, SO, D0 to D3 –0.3 V CC D + 0.3 V Output voltage 1 V out1– 0 . 3 V CC D + 0.3 V Input voltage 2 V in2 D4 to D11 –0.3 V CC A + 0.3 V Output voltage 2 V out2– 0 . 3 V CC A + 0.3 V Power consumption P D — — 250 mW Operating temperature Ta — –20 +85 °C Storage temperature T stg — –55 +150 °C Parameter Symbol Conditions Value Unit Min. Typ. Max. Power supply voltage VCC A— 2 . 7 3 . 0 3 . 6 V VCC D— 2 . 7 — 3 . 6 V VDD VCC A ‡ VDD 2.0 — V CC AV GND — — 0 — V Analog output current IAL Source current — — 1.0 mA IAH Sink current — — 0.4 mA Oscillation limit output capacity C OL —— — 1 . 0 mF Operation temperature Ta — –20 — +85 °C

n ELECTRICAL CHARACTERISTIC 1. DC Characteristics (1) Digital section (2) D/A converter section Parameter Symbol Pin name Conditions Value UnitMin. Typ. Max. Power supply voltage V CC D VCC D — 2.7 3.0 3.6 V Power supply current ICC D CLK =1 MHz, (Unloaded) — 0.1 0.35 mA Standby current I CC S CLK, SI, CS Stop Vin = VCC D or GND –10 — +10 mA Input leak current I ILK1 CLK, SI, CS , D 0 to D3 Vin = 0 to VCC D –10 — +10 mA “H” level input voltage VIH1 —0 . 5 · VCC D— — V “L” level input voltage VIL1 —— — 0 . 2 · VCC DV Output high-impedance leakage current IOLK SO V in = 0 to VCC D –10 — +10 mA “H” level output voltage VOH1 SO, D 0 to D3 IOH = –0.4 mA V CC D - 0.4 — — V “L” level output voltage VOL1 IOL = 2.5 mA — — 0.4 V Parameter Symbol Pin name Conditions Value UnitMin. Typ. Max. Power supply voltage V DD VDD VDD £ VCC A 2.0 3.0 3.6 V Power supply current I DD VDD £ VCC A— 0 . 7 1 . 9 m A Resolution Res AO 1 to AO12 Unloaded —8— b i t Monotonic increase Rem — 8 — bit Nonlinearity error LE –1.5 — +1.5 LSB Differential linearity error DLE –1.0 — +1.0 LSB VAOH VAOL #05 #FA Nonlinearity error: Deviation (error) in input/output curves with respect to an ideal straight line connecting output voltage at “05” and output voltage at “FA”. Deviation (error) in amplification with respect to theoretical increase in amplification per 1-bit increase in digital value. Differential linearity error: Note:The value of V AOH and VDD , and the value of VAOL and GND are not necessarily equivalent. Digital setting Ideal line Nonlinearity error Analog output

(3) Operational Amplifier/Analog output section Note: IAH : Analog output sink current IAL: Analog output source current Parameter Symbol Pin name Conditions Value UnitMin. Typ. Max. Power supply voltage V CCA VCCA — 2.7 3.0 3.6 V Power supply current I CCA #80 setting (Unloaded) —1 . 0 4 . 8 m A Input leakage current IILK2 D 4 to D11 Vin = 0 to VCC A –10 — +10 mA “H” level digital input voltage VIH2 —0 . 5 · VCC A— — V “L” level digital input voltage VIL2 —— — 0 . 2 · VCC AV “H” level digital output voltage VOH2 IOH = –0.4 mA V CC A - 0.4 — — V “L” level digital output voltage VOL2 IOL = 2.5 mA — — 0.4 V Analog output minimum voltage 1 VAOL1 AO 1 to AO12 IAL = 0 A #00 setting GND — 0.1 V Analog output minimum voltage 2 VAOL2 IAL = 0.5 mA #00 setting –0.2 GND 0.2 V Analog output minimum voltage 3 VAOL3 IAH = 0.4 mA #00 setting GND — 0.15 V Analog output minimum voltage 4 VAOL4 IAL = 1.0 mA #00 setting –0.3 GND 0.3 V Analog output maximum voltage 1 VAOH1 AO 1 to AO12 IAL = 0 A #FF setting VCC A - 0.1 — V CC AV Analog output maximum voltage 2 VAOH2 IAL = 0.5 mA #FF setting VCC A - 0.2 — V CC AV Analog output maximum voltage 3 VAOH3 IAH = 0.4 mA #FF setting VCC A - 0.15 V CC AV CC A + 0.15 V Analog output maximum voltage 4 VAOH4 IAL = 1.0 mA #FF setting VCC A - 0.3 — V CC AV

1. AC Characteristics * : Cascade connection enabled at 1.5 MHz. Parameter Symbol Conditions Value UnitMin. Typ. Max. Clock “L” level pulse width t CKL — 200 — — ns Clock “H” level pulse width t CKH — 200 — — ns Clock rise time t Cr — — — 200 ns Clock fall time t Cf — — — 200 ns Serial input setup time t SSU —3 0 — — n s Serial input hold time t SHD —6 0 — — n s Serial output delay time t SOD See “Load condition 1”* 0 120 300 ns CS input setup time t CSU — 100 — — ns CS hold time t CCH — 200 — — ns CS “H” level hold time t CSH — 100 — — ns Data output enable time t SO — — — 200 ns Data output float time t SOZ — — — 200 ns Parallel input setup time t PSU —3 0 — — n s Parallel input hold time t PHD —6 0 — — n s Parallel output delay time t POD See “Load condition 1” — 120 300 ns Analog output delay time t AOD See “Load condition 2” — 30 100 ms Power supply rise time t R —— — 5 0 m s Power-on reset non-startup power supply variation DVR — –10 — 10 V/ ms C L = 20 pF to 100 pF R AL = 10 kW C AL = 50 pF Measurement pointMeasurement point

• Load condition 1 • Load condition 2 Load Conditions

• Input/Output Timing (CS method) CLK SI CS SO D 0 ~ D11 (at input) D 0 ~ D11 (at output) AO 1 ~ AO12 90 % 10 % tCr tCKH tSSU tCKL tCSU tSO tSOD tSOD tSOZ tCCH tPSU tPOD tAOD tPHD tCSHtSHD tCf CLK, SI, CS, SO D0 to D3 decision level is 80% and 20% of VccD. D4 to D11 decision level is 80% and 20% of VccA. AO1 to AO12 decision level is 90% and 10% of VccA.

n DATA INPUT/OUTPUT TIMING (Serial Bus Format)

• Timing of D/A Converter Operation, I/O Expander Operation (serial to parallel conversion), and ESR Write Operation. Data input is enabled at the fall of the CS signal. 16-bit data is input, and executed by shift register command at the rise of CS. In D/A converter operation, analog output selected at the rise of CS is converted. In serial to parallel conversion, digital output selected at the rise of CS is converted. In ESR write operation, data is set in the ESR at the rise of [CS] and used to change pin states.
• I/O Expander Operation (parallel to serial conversion) Data input is enabled at the fall of the CS signal. 16-bit data (parallel to serial conversion command) is input, and commands received at the rise of CS. At the fall of CS the data from parallel input is loaded in the shift register from D4 to DF , and output from the SO pin timed to the fall of the CLK signal. D0 D1 D2 DE DF 123 1 5 1 6 SI CLK CS SO AO · D ·· 11 2 16 16 D0 DF D0 DF SI CLK CS SO D ·· (Parallel to serial conversion command entered) (Parallel to serial conversion result output) Parallel data loaded

1. Preventing Latch-Up A condition known as “latch-up” may occur when the input or output pins of a CMOS IC device are exposed to voltages higher then VCC D or VCC A or lower than GND voltage, or when voltages are applied to the device in excess of rated values for VCC D, VccA, or VDD to GND voltages. Latchup produces a rapid increase in power supply current, and may result in thermal destruction of elements. Users should take sufficient precautions to ensure that absolute maximum ratings are not exceeded at any time during use. 2. Power Supply Pins The power supply should be connected to the VCC D, VCC A, VDD , and GND terminals of the IC with as low an impedance as possible. In addition, it is recommended that ceramic capacitors of approximately 0.1 mF be connected as bypass capacitors between the V CC D, VCC A, and VDD terminals and the GND terminals. n ORDERING INFORMATION Part number Package Remarks MB40D001PFV 24-pin Plastic SSOP (FPT-24P-M03)

C 1994 FUJITSU LIMITED F24018S-2C-2 0.50±0.20 (.020±.008) (STAND OFF) 0 10° Details of "A" part 7.15(.281)REF NOM 7.60±0.20 "A" .006–.001 +.002 –0.02 +0.05 0.15 .049–.004 +.008 –0.10 +0.20 1.25 .009–.002 +.004 –0.05 +0.10 0.22 0.10(.004) INDEX (Mounting height) Dimension in mm (inches) 24-pi plastic SSOP (FPT-24P-M03) *: These dimensions do not include resin protrusion.

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3545 North First Street

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