MB40C348 FUJITSU | Alldatasheet
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DS04-28219-1EFUJITSU SEMICONDUCTOR DATA SHEET ASSP For Video Applications CMOS 3 ch 8-bit 100 MSPS A/D Converter MB40C348 nnnn DESCRIPTION MB40C348 is a high-speed 3ch A/D converter using a fast CMOS technology. nnnn FEATURES
- Resolution : 8 bit
- No. of AD channels : 3 ch
- Linearity error : ±0.40% (typical)
- Maximum conversion rate : 100 MSPS (minimum)
- Power supply voltage : 3.3 V (typical: internal circuit)
- Digital input voltage range : TTL level
- Digital output voltage range : 3.3 V CMOS level
- Amp. input voltage range : 0.7 V P-P (typical)
- Amp. gain : 1.9 double fixed
- Power dissipation : 880 mW (typical)
- Additional features : PLL circuit Video Amp. circuit (1.9 double fixed gain) CLAMP circuit V RT Amp. circuit (RGB 3 ch common) VRB Amp. circuit (RGB 3 ch common) Overflow output High impedance output, power down function
- Package : LQFP120 (16 mm ·16mm, lead pitch : 0.5 mm) nnnn PACKAGE 120-pin plastic LQFP (FPT-120P-M21)
(TOP VIEW) (FPT-120P-M21) RV IN VR2 GV IN CE BV IN VR1 VREF PCLP AV DD AV SS RADIN DSEL GADIN VESD BADIN VRBM VRB VREFB RV CLP GV CLP BV CLP AV SS AV DD CS CK DATA DV SS DV DD (MSB) BDB7 BD B6 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 PV SS PV DD HSYNC HHOLD PV DD LPF PV SS R REF VREFT VRT VRTM VR3 AV SS AV DD DV DD DV SS OF DSYNC DSYNCB COUT EXPCLK EXPCLKB EXCLK ADCLKA ADCLKB CLK CLKB DV DD DV SS AV SS BD BD B4 BD B3 BD B2 BD B1 (LSB) BDB0 DV SS DV DD (MSB) BDA7 BD A6 BD A5 BD A4 BD A3 BD A2 BD A1 (LSB) BDA0 AV DD AV SS DV SS DV DD (MSB) GD B7 GD B6 GD B5 GD B4 GD B3 GD B2 GD B1 (LSB) GDB0 DV DD DV SS RD A0 (LSB) RD A1 RD A2 RD A3 RD A4 RD A5 RD A6 RD A7 (MSB) DV DD DV SS AV SS AV DD RD B0 (LSB) RD B1 RD B2 RD B3 RD B4 RD B5 RD B6 RD B7 (MSB) DV DD DV SS GD A0 (LSB) GD A1 GD A2 GD A3 GD A4 GD A5 GD A6 GD A7 (MSB)
Note: The values in parentheses are standard. (Continued) Pin No. Symbol Description 9, 23, 47, 79, 107 AV DD Analog power supply (+3.3 V) 28, 38, 50, 59, 70, 82, 93, 106 DV DD Digital power supply (+3.3 V) 116, 119 PV DD PLL power supply (+3.3 V) 14 V ESD Digital input power supply for protect device (+3.3 V or +5 V) 10, 22, 48, 80, 91, 108 AV SS Analog power supply ground pin (0 V) 27, 37, 49, 60, 69, 81, 92, 105 DV SS Digital power supply ground pin (0 V) 114, 120 PV SS PLL power supply ground pin (0 V) RV IN GV IN BV IN 1.9 double Amp. input pin RADIN GADIN BADIN A/D converter input pin Please set these pins to open usually. RV CLP GV CLP BV CLP Clamp voltage setting input pin
110 V RTM Reference voltage output pin on top side
111 V RT Reference voltage input pin on top side
112 V REFT Reference voltage generator output pin on top side
16 V RBM Reference voltage output pin on bottom side
17 V RB Reference voltage input pin on bottom side
18 V REFB Reference voltage generator output pin on bottom side
Reference 1/4 voltage output pin (Add 0.1 mF for AVSS ) Reference 1/2 voltage output pin (Add 0.1 mF for AVSS ) Reference 3/4 voltage output pin (Add 0.1 mF for AVSS )
12 DSEL Mode of operation setting input pin (Refer to n MODE SETTING)
25 CK Serial data transfer clock input pin
26 DATA Serial data input pin
Chip select signal input pin It is possible to input to the shift register at CS falling The content of the shift register is executed at CS rising
98 EXCLK Clock input pin for A/D converter (CMOS level)
Fix to “L” level when unused.
(Continued) Note: The values in parentheses are standard. Pin No. Symbol Description
99 EXPCLKB Differential clock (positive-phase) input pin for A/D converter
Fix to “H” level when unused. PECL level
100 EXPCLK Differential clock (negative-phase) input pin for A/D converter
Fix to “L” level when unused.
8 PCLP Clamp pulse input pin
4C E Power down at CE input “H” level (internal pull-up resistor)
113 R REF Internal current setting pin (Add 12kW for AVss)
103 DSYNC Delay sync signal output pin
102 DSYNCB Inverted delay sync signal output pin
95 CLK
Clock output pin (See “ n TIMING DIAGRAM ”.)
94 CLKB
97 ADCLKA
96 ADCLKB
Digital output pin (Port A) RD A7, GDA7, BDA7 : MSB RD A0, GDA0, BDA0 : LSB 71 to 78 51 to 58 29 to 36 RD B7 to RDB0 GD B7 to GDB0 BD B7 to BDB0 Digital output pin (Port B) RD B7, GDB7, BDB7 : MSB RD B0, GDB0, BDB0 : LSB
101 COUT PLL counter output pin
115 LPF External capacitor / resistor connection pin
117 HHOLD Phase detector operation is hold by input “H” level
118 HSYNC Horizontal sync signal input pin
REF Internal voltage output pin (Add 3.3 µF for AVss)
104 OF Overflow output pin (“H” level output at overflow)
EXPCLKB EXCLK PV SS PV DD CK CS CLKB CLK DSYNCB DSYNC DV SS AV SS ADCLKB ADCLKA OF VR3VR2VR1VRBMVRBVRTVRTMDV DDAV DDVREFBVREFTVESD RD B0 ~ RDB7 RD A0 ~ RDA7 DATA RR AMP + CLAMP + A/D
- 1.9 A ch B ch 8 bit A/D 8 bit A/D 8 8 8 8 Buffer Buffer Buffer Buffer Buffer Buffer Buffer Buffer 11 bit ShiftCounter (12 bit) Filter
- 3 ch (1 bit) 2 bit (1 ~ 1/8) DIVMUXVCO Delay RESET CPPDPOL 2 bit (0 ~ 3 CLK) CLK Delay VREF Amp. Block PLL Block 6 bit (32 divide, 2CLK)
nnnn ABSOLUTE MAXIMUM RATINGS *1 : Do not exceed +4.0 V . *2 : Do not exceed +7.0 V . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Rating Unit Min. Max. Power supply voltage AV DD , DVDD , PVDD -0.3 +4.0 V VESD -0.3 +7.0 V Input/output voltage RV IN, GVIN, BVIN, RADIN, GADIN, BADIN, RV CLP , GVCLP , BVCLP , VRT , VRTM , VREFT , VRB , VRBM , VREFB , VR1 , VR2 , VR3 VREF , RREF -0.3 AV DD +0.3*1 V RD A0 to RDA7, RDB0 to RDB7, GD A0 to GDA7, GDB0 to GDB7, BD A0 to BDA7, BDB0 to BDB7, DSYNC, DSYNCB, OF, COUT, CLK, CLKB, ADCLKA, ADCLKB -0.3 DV DD +0.3*1 V LPF -0.3 PV DD +0.3*1 V DSEL, CK, DATA, CS, EXPCLKB, EXPCLK, PCLP, CE, EXCLK, HHOLD, HSYNC -0.3 V ESD +0.3*2 V Storage temperature T STG -55 +125 °C
nnnn RECOMMENDED OPERATING CONDITIONS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Min. Typ. Max. Power supply voltage AV DD , DVDD 3.00 3.30 3.60 V PV DD 3.00 3.30 3.60 V VESD 3.00 ¾ 5.25 V A/D converter input voltage V ADIN VRB ¾ VRT V Analog reference voltage : T V RT ¾ 2.2 AV DD - 0.6 V Analog reference voltage : B V RB 0.6 0.7 ¾ V Analog reference voltage range V RT - VRB 1.0 1.5 1.8 V Video Amp. input voltage V IN (P-P) 0.5 ¾ 0.9 V P-P Clamp input voltage V CLP 0.6 V RB 1.7 V Digital “H” level input voltage V IHD 2.5 ¾ VESD V Digital “L” level input voltage V ILD 0 ¾ 0.5 V Digital “H” level output current I OHD -400 ¾¾m A Digital “L” level output current I OLD ¾¾ 1.6 mA PLL counter P C 100 ¾ 4095 ¾ HSYNC input frequency range f HSYNC 10 ¾ 100 kHz HHOLD set up time t sHHOLD 20 ¾¾ ns HHOLD hold time t hHHOLD 20 ¾¾ ns Clamp pulse width t WCLP 0.5 ¾¾m s CK clock pulse width t WCKL , tWCKH 100 ¾¾ ns DATA set up time t sDATA 30 ¾¾ ns DATA hold time t hDATA 30 ¾¾ ns CS set up time t sCS 50 ¾¾ ns CS hold time t hCS 50 ¾¾ ns CS “H” level hold time t WCSH 100 ¾¾ ns Operating temperature range Ta -20 ¾ 70 °C
nnnn ELECTRICAL CHARACTERISTICS 1. DC Characteristics in Analog Section
- Power supply current (AVDD = DVDD = PVDD = 3.0 V to 3.6 V , VESD = 3.0 V to 5.25 V , T a = -20 °C to +70 °C)
- Block A/D (AV DD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, T a = -20 °C to +70 °C)
- CLAMP Block (AV DD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, T a = -20 °C to +70 °C)
- PLL Block (AV DD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, T a = -20 °C to +70 °C) Parameter Symbol Value Unit Min. Typ. Max. Analog power supply current AI DD ¾ 170 290 mA Digital power supply current DI DD ¾ 80 90 mA Power supply current PLL section (@ fVCOH = 162 MHz, Icp = 0.5 mA, DIV = 1/1) PIDD ¾ 16 20 mA Standby current I SB ¾ 10 ¾ mA Parameter Symbol Value Unit Min. Typ. Value Resolution ¾¾ 8 ¾ bit Linearity error (DC Accuracy) LE -0.8 –0.4 +0.8 % Differential linearity error (DC Accuracy) DLE-0.36 –0.2 +0.65 % Reference voltage : T V REFT 0.63 ·AV DD 0.67 ·AV DD 0.70 ·AV DD V Reference voltage : B V REFB 0.18 ·AV DD 0.21 ·AV DD 0.24 ·AV DD V Analog reference voltage input current IRT , IRB ¾ 52 0 mA Parameter Symbol Value Unit Min. Typ. Value Video Amp. gain G AMP 1.8 1.9 2.0 ¾ Video Amp. output voltage range V AMPOUT 0.5 ¾ AV DD - 0.6 V Video Amp. frequency width BW ¾ 170 ¾ MHz Video Amp. input capacity C VIN ¾ 5 ¾ pF Parameter Symbol Value Unit Min. Typ. Value VCLP input current I CLP ¾ 52 0 mA Clamp voltage V CLAMP VCLP - 0.1 V CLP VCLP + 0.1 V Parameter Symbol Value Unit Min. Typ. Value CLK jitter (@ fHSYNC = 68.68 kHz, fCLK = 94.5 MHz) P tj ¾ 1.0 1.5 ns
- DC Characteristics in Digital Section (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, T a = -20 °C to +70 °C) 3. Switching Characteristics (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, T a = -20 °C to +70 °C) nnnn DIGITAL OUTPUT BUFFER LOAD CIRCUIT nnnn MODE SETTING Parameter Symbol Value Unit Min. Typ. Max. Digital input current I ID -20 ¾ 5 mA Digital “H” level output voltage VOHD DV DD - 0.4 ¾¾ V Digital “L” level output voltage VOLD ¾¾ 0.4 V Parameter Symbol Value Unit Min. Typ. Max. A/D maximum conversion rate f S 100 ¾¾ MSPS Aperture time t AD ¾ 1.5 ¾ ns VCO oscillation frequency VCOL f VCOL 75 ¾ 140 MHz VCOH f VCOH 85 ¾ 162 MHz CLK output delay time t pd (HSYNC -CLK ) 1.0 2.0 4.0 ns Digital output delay time Timing diagram 1 tpd (CLK -ADCLK1 ) 0.0 1.0 2.0 ns tpd (CLK -DATA1 ) 2.5 4.0 6.0 ns Timing diagram 2 tpd (CLK -ADCLK2 ) 0.0 1.0 2.0 ns tpd (CLK -DATA2 ) 2.5 4.0 6.0 ns DSYNC output delay time t pd (CLK -DSYNC ) 0.5 1.5 2.0 ns Pin Setting Mode Timing Diagram DSEL H Straight output mode Timing diagram 1 L Demultiplex output (in-phase) mode Timing diagram 2 CE H All function power OFF L Operation mode C L = 15 pF DV SS To the measurement point Measurement point Note: C L includes a stray capacitance of a probe and a fixture.
nnnn SERIAL DATA SETTING (MSB Fast) *1 : Setting at 6bit, Resolution: 1/32 ·CLK, Setting range: 0 to 63/32 ·CLK *2, *3, *4 : See under table Example: input at 16 bit DSYNC Delay *2 0 CLK 1 CLK 2 CLK 3 CLK Charge pump current*3 0.1 mA 0.5 mA 1.0 mA ¾ Divider setting*4 1/1 1/2 1/4 1/8 (Address) (Data) LSB MSB R E S D 0D 1D 2D 3D 4D 5D 6D 7D 8D 9 D 1 0 F u n c t i o n 1100 0 0 0 0 0 0 1 0 Counter low ranking 8 bit 2010 0 0 0 0 X X X X Counter high ranking 4 bit 110 0 0 0 0 0 0 1 0 CLK delay adjust *1 : td = N/ (32 ·fCLK ) 110000000 1 0 HSYNC polarity : 0 = through, 1 = inversion 1100000001 0 A/D converter output : 0 = operation, 1 = high impedance 001 00000010 C L K o u t p u t : 0 = on, 1 = “L” 0010 0000010 C L K B o u t p u t : 0 = on, 1 = “L” 00100 000010 D S Y N C o u t p u t : 0 = on, 1 = “L” 001000 00010 D S Y N C B o u t p u t : 0 = on, 1 = “L” 0010000 0010 A D C L K A o u t p u t : 0 = on, 1 = “L” 00100000 0 1 0 ADCLKB output : 0 = on, 1 = “L” 001000000 1 0 DSYNC delay *2 : 0, 1, 2, 3 101 00000010 C L K c h a nge : 0 = VCO, 1 = External clock 1010 0000010 E x t e r n a l c l o c k i n p u t : 0 = CMOS, 1 = PECL 10100 000010 C ounter operation : 0 = on, 1 = off 101000 0 0010 Charge pump current*3 : 0.1 mA, 0.5 mA, 1 mA 10100000 0 1 0 VCO select : 0 = VCOL, 1 = VCOH 101000000 1 0 Divider setting*4 : 1, 1/2, 1/4, 1/8 MSB (5 bit) (8 bit) DATA (3 bit) LSB DATA input CS input AddressThe invalid data
nnnn RECOMMEND VALUE OF SERIAL DATA SETTING VCO select : VCOH (fVCO = 85 MHz to 162 MHz) VCOL (fVCO = 75 MHz to 140 MHz) fCLK = fHSYNC ·Counter fVCO = fHSYNC ·Counter/Divider fCLK (MHz) f HSYNC (kHz) Counter Icp (mA) VCO select Divider f VCO (MHz) XGA 94.500 68.677 1376 0.5 VCOH or VCOL 1/1 94.500 78.750 60.023 1312 0.5 VCOL 1/1 78.750 75.000 56.476 1328 0.5 VCOH 1/2 150.000 65.000 48.363 1344 0.5 VCOH or VCOL 1/2 130.000 SVGA 56.250 53.674 1048 0.5 VCOH or VCOL 1/2 112.500 50.000 48.077 1040 0.5 VCOH or VCOL 1/2 100.000 49.500 46.875 1056 0.5 VCOH or VCOL 1/2 99.000 40.000 37.879 1056 0.5 VCOL 1/2 80.000 VGA 36.000 43.269 832 0.5 VCOH 1/4 144.000 31.500 37.861 832 0.5 VCOH or VCOL 1/4 126.000 25.175 31.469 800 0.5 VCOH or VCOL 1/4 100.700 25.149 31.436 800 0.5 VCOH or VCOL 1/4 100.596 PAL 29.375 15.625 1880 0.5 VCOH or VCOL 1/4 117.500 22.031 15.625 1410 0.5 VCOH or VCOL 1/4 88.125 14.688 15.625 940 0.5 VCOH or VCOL 1/8 117.500 NTSC 24.545 15.734 1560 0.5 VCOH or VCOL 1/4 98.180 18.409 15.734 1170 0.5 VCOH 1/8 147.270 12.273 15.734 780 0.5 VCOH or VCOL 1/8 98.180
- Straight Output Mode (Timing Diagram 1)
- ADIN input : Sampling at CLK rising (at CLKB falling)
- D A0 to DA7 : Output (after 5CLK + tpd(CLK-DATA1) from sampling) at CLK rising (at CLKB falling) tpd (HSYNC-CLK) tpd (CLK-DSYNC) tAD tpd (CLK-ADCLK1) tpd (CLK-DATA1) N VOHD VOLD VOHD VOLD VOHD VOLD N + 3N + 2N + 1NXXXXXXXX N + 1N + 2N + 3N + 4N + 5N + 6N + 7N + 8N + 9 N + 3N + 2N + 1NXXXXXXXX HSYNC input CLK output CLKB output DSYNC output ADCLKA output ADCLKB output ADIN input D A0 to DA7 output D B0 to DB7 output OF output ALL “L” fix VIHD VILD VOHD VOLD VOHD VOLD VOHD VOLD VOLD VOHD
- Demultiplex Output (in-phase) Mode (Timing Diagram 2)
- ADIN input : Sampling at CLK rising (at CLKB falling)
- D A0 to DA7 : Output (after 6CLK + tpd(CLK-DATA2) from sampling) at CLK rising (at CLKB falling)
- D B0 to DB7 : Output (after 5CLK + tpd(CLK-DATA2) from sampling) at CLK rising (at CLKB falling) tpd (HSYNC-CLK) tpd (CLK-DSYNC) tAD tpd (CLK-ADCLK2) tpd (CLK-DATA2) N X X X X X X X X X X X X X X X N N + 1 N N + 2 N + 3 N + 2 N + 1N + 2N + 3N + 4N + 5N + 6N + 7N + 8N + 9 HSYNC input CLKB output CLK output DSYNC output ADCLKA output ADCLKB output ADIN input D A0 to DA7 output D B0 to DB7 output OF output VIHD VILD VOHD VOLD VOHD VOLD VOHD VOLD VOHD VOLD VOLD VOLD VOLD VOHD VOHD VOHD
nnnn CLAMP and Amp. OPERATION RV IN 10 mF
- 1.9 GV IN PCLP GADIN VRT GV CLP VRB
0.7 Vp-p
Amp./CLAMP circuit Image signal Clamp pulse Internal BIAS (0.6 ·AV DD ) Example: Sync on G signal input >
1.33 VP-P (fixed)
Contrast adjust : controlling the voltage difference between VRT and VRB (typ : VRT - VRB = 1.33 V) Brightness adjust : controlling the voltage difference between VCLP and VRB . (typ : VCLP = VRB )
nnnn CLAMP SIGNAL and HOLD SIGNAL nnnn SERIAL DATA TRANSFER TIMING thHHOLD tsHHOLD thHHOLD tsHHOLD tWCLP HSYNC input HHOLD input PCLP input CLK output tWCKL tWCKH tsDATA thDATA thCStsCS tWCSH D10 D9 D8 D7 D1 D0DATA input CK input CS input
(LSB) RDA0 90 RD A1 89 RD A2 88 RD A3 87 RD A4 86 RD A5 85 RD A6 84 (MSB) RDA7 83 DV DD 82 DV SS 81 AV SS 80 AV DD 79 (LSB) RDB0 78 RD B1 77 RD B2 76 RD B3 75 RD B4 74 RD B5 73 RD B6 72 (MSB) RDB7 71 DV DD 70 DVSS 69 (LSB) GDA0 68 GD A1 67 GD A2 66 GD A3 65 GD A4 64 GD A5 63 GD A6 62 (MSB) GD A7 61 PVSS 120 PVDD 119 HSYNC 118 HHOLD 117 PV DD 116 LPF 115 PVSS 114 RREF 113 VREFT 112 VRT 111 VRTM 110 VR3 109 AVSS 108 AVDD 107 DVDD 106 DVSS 105 OF 104 DSYNC 103 DSYNCB 102 COUT 101 EXPCLK 100 EXPCLKB 99 EXCLK 98 ADCLKA 97 ADCLKB 96 CLK 95 CLKB 94 DV DD 93 DVSS 92 AVSS 91
31 BDB5
32 BDB4
33 BDB3
34 BDB2
35 BDB1
36 BDB0 (LSB)
37 DVSS
38 DVDD
39 BDA7 (MSB)
40 BDA6
41 BDA5
42 BDA4
43 BDA3
44 BDA2
45 BDA1
46 BDA0 (LSB)
47 AVDD
48 AVSS
49 DVSS
50 DVDD
51 GDB7 (MSB)
52 GDB6
53 GDB5
54 GDB4
55 GDB3
56 GDB2
57 GDB1
58 GDB0 (LSB)
59 DVDD
60 DVSS
1 RVIN
2 VR2
3 GVIN
6 VR1
7 VREF
8 PCLP
10 AVSS
11 RADIN
12 DSEL
13 GADIN
15 BADIN
17 VRB
18 VREFB
19 RVCLP
20 GVCLP
21 BVCLP
22 AVSS
23 AVDD
26 DATA
28 DVDD
29 BDB7 (MSB)
30 BDB6
+ + + DV SS (0 V) DV DD (+3.3 V) Note : Unexpresstion capacitance values are all 1 mF EXPCLK EXPCLKB EXCLK VRT 12 kW 0.001 mF 0.1 mF 1.6 kWHHOLD HSYNC +PV DD (+3.3 V) PV SS (0 V) AV SS (0 V) AV DD (+3.3 V) RV IN CE GV IN BV IN PCLP DSEL VRB /VCLP Serial Data +3.3 V or +5 V 75 W 75 W 100 mF 10 mF 10 mF 10 mF (MB40C348) 100 mF 100 mF 75 W
Be sure to ground the pins of AVDD , DVDD , PVDD , VESD , VRTM , VRBM , VR1 ,VR2 , VR3 , and VREF via high-frequency capacitor. Place the high-frequency capacitor as close as possible to the pin. nnnn ORDERING INFORMATION Part number Package Remark MB40C348PFV 120-pin plastic LQFP (FPT-120P-M21)
(FPT-120P-M21) C 1998 FUJITSU LIMITED F120033S-2C-2 1 30 90 61 120 (.009±.002) M0.08(.003) INDEX .006–.001 +.002 –0.03 +0.05 0.145 "A" 0.08(.003) LEAD No. .059–.004 +.008 –0.10 +0.20 1.50 Details of "A" part 0~8° (Mounting height) 0.45/0.75 (.018/.030) 0.25(.010) (.004±.002) 0.10±0.05 (Stand off) Dimensions in mm (inches) .
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, T okyo 163-0721, Japan T el: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A. T el: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) T el: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany T el: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New T ech Park, Singapore 556741 T el: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280 Korea T el: +82-2-3484-7100 Fax: +82-2-3484-7111 F0009 ª FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.