MB40950 FUJITSU | Alldatasheet

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DS04-28314-2EFUJITSU SEMICONDUCTOR DATA SHEET ASSP 3-Channel 10-Bit D/A Converter MB40950 n DESCRIPTION The MB40950 is a 10-bit resolution high-speed digital-to-analog converter, designed for video processing applications such as TVsets and VCRS. The MB40950 has 10-bit resolution 3 channels D/A converters. Digital data are input to the 10-bit digital input ports, and the input digital data are converted into the analog data in minimum 60 Mega sample per seconds (MSPS). The analog output voltage is provided in a range of DC +3V to +5V (2Vp-p level) . The MB40950 is fabricated by the Fujitsu’s advanced bipolar process and housed in a 48-pin plastic QFP . The MB40950 is designed for video signal processing, and it is suitable for TV S and VCRS applications. n FEATURES

  • 10-bit x 3 channels D/A converters
  • Max. 60 MHz input clock frequency providing 60 MSPS data conversion rate
  • Linearity error : Max. +/-0.07%
  • Analog output voltage range : 3V to 5V (2Vp-p level)
  • Digital input voltage level : TTL level
  • On-chip reference voltage generator (Continued) n PACKAGE (FPT -48P-M15) 48 pin, Plastic QFP This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.

(Continued)

  • Low power consumption : – T ypical 460mW at 2Vp-p analog output voltage – T ypical 350mW at 1Vp-p analog output voltage
  • Single +5V power supply
  • Operating temperature range : -20°C to +70°C
  • Fujitsu’s advanced bipolar process
  • Package : 48-pin plastic QFP (Suffix : -PF) n PIN ASSIGNMENT CLKR CLKG CLKB R 1 R 2 R 3 R 4 R 5 R 6 R 7 R 8 R 9 (FPT -48P-M15) (TOP-VIEW) VROUT1 COMP V CCD B10 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 R 10 G 1 G 2 G 3 G 4 G 5 G 6 G 7 G 8 G 9 G 10 B1 D.GND VCCA R OUT A.GND VCCA G OUT A.GND VCCA BOUT A.GND VROUT2 VRIN INDEX

(Continued) Symbol Pin No. Type Name & Function Power Supply VCCD 34 — +5V DC power supply pins for digital block. D. GND 48 — Ground pin for digital block. VCCA 41, 44, 47 — DC power supply pins for analog block. A. GND 39, 42, 45 — Ground pins for analog block. Clock CLKR 1 I Clock input pin for R channel. CLKG 2 I Clock input pin for G channel. CLKB 3 I Clock input pin for B channel. Digital Input R 1 R 2 R 4 R 5 R 6 R 7 R 8 R 9 R 10 I Digital data input pins for R channel. 10-bit data is input to the pins. The R1 pin is the MSB and the R10 pin is the LSB. G 1 G 2 G 3 G 4 G 5 G 6 G 7 G 8 G 9 G 10 I Digital data input pins for G channel. 10-bit data is input to the pins. The G 1 pin is the MSB and the G10 pin is the LSB. B10 I Digital data input pins for B channel. 10-bit data is input to the pins. The B 1 pin is the MSB and the B10 pin is the LSB.

(Continued) Symbol Pin No. Type Name & Function Analog Output R OUT 46 O Analog signal output pin for R channel. G OUT 43 O Analog signal output pin for G channel. BOUT 40 O Analog signal output pin for B channel. Reference Voltage VRIN 37 I Reference voltage input pin. This pin is used to set the analog output dynamic range. When the internal reference voltage is used, this pin is connected with V ROUT1 pin (36 pin) or VROUT2 pin (38 pin). When the reference voltage is supplied from the external generator, 2.65V to 4.3V or VCCA - VRIN = 0.7V to 2.2V is input to this pin. VROUT1 36 O Reference voltage output #1 pin. The output voltage is set to 0.6 x V CCA by the resistor divided method. When this pin is connected with VRIN pin (37 pin), an analog voltage is output from this pin in a range of 0.6 x VCCA to VCCA . VROUT2 38 O Reference voltage output #2 pin. The output voltage is set to VCCA - 2V by the band-gap reference method. When this pin is connected with VRIN pin (37 pin), an analog voltage is output from this pin in a range of VCCA - 2V to VCCA . Compesation Capacitor COMP 35 - Phase compesation capacitor pin. A phase compesation capacitor of 0.1mF or greater is connected between this pin and A. GND pin.

(MSB) (LSB) 101010 CLKG Input buffer Master slave Flip-Flop Buffer Current switch VCCA G OUTG 1 G 2 G 3 G 4 G 5 G 6 G 7 G 8 G 9 G 10 (MSB) 101010 CLKB Input buffer Master slave Flip-Flop Buffer Current switch VCCA BOUTB1 B10 (MSB) (LSB) Amp. Reference resistor Reference voltage #2 VCCA - 2V VCCAVCCDCOMPVRINVROUT2VROUT1A. GNDD. GND (LSB) Reference voltage #1 0.6 x VCCA

n ABSOLUTE MAXIMUM RATINGS n RECOMMENDED OPERATING CONDITIONS (A. GND = D. GND = 0V) Parameter Symbol Rating Unit Power supply voltage VCCA , VCCD –0.5 to +7.0 V Power supply voltage difference VCCD – VCCA 1.5 V Analog reference voltage VRIN –0.5 to VCCA +7.0 V Digital input voltage VID –0.5 to +7.0 V Storage temperature Tstg –55 to +125 °C Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (A. GND = D. GND = 0V) Parameter Symbol Value Unit Min. Typ. Max. Power supply voltage VCCA , VCCD 4.75 5.00 5.25 V Power supply voltage difference VCCA – VCCD –0.2 — 0.2 V Analog reference voltage VCCA – VRIN 0.70 2.00 2.20 V VRIN 2.65 3.00 4.30 V Digital "H" level input voltage VIHD 2.0 — — V Digital "L" level input voltage VILD — — 0.8 V Clock frequency fCLK — — 60 MHz Setup time tSU 8.0 — — ns Hold time th 2.0 — — ns Minimum clock "H" level pulse width twH 6.5 — — ns Minimum clock "L" level pulse width twL 6.5 — — ns Phase compesation capacitance C COMP 0.1 — — mF Operating ambient temperature TOP –20 — 70 °C

n ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions Otherwise Noted) 1. DC Characteristics 2. AC Characteristics Parameter Symbol Value Unit RemarkMin. Typ. Max. Resolution — — — 10 bit — Linearity error LE — — –0.07 % DC Accuracy Differential linearity error DLE — — –0.07 % DC Accuracy Digital "H" level input current IIHD — — 20 mA VIHD = 2.7 (V) Digital "L" level input current IILD –100 — — mA VILD = 0.4 (V) Reference input current IRIN — — 10 mA VRIN = 3.000 (V) Reference voltage (Resister divided)VROUT1 2.900 3.000 3.100 V VCCA = VCCD = 5.00 (V) Reference voltage (BGR) VROUT2 VCCA –2.100 VCCA –2.000 VCCA –1.900 V — Reference voltage (BGR) — — 100 — ppm/°C — RGB output voltage ratio FSR 0 — 6 % VCCA = VCCD = 5.00 (V) Full-scale output voltage VOFS VCCA –20 VCCA — mV — Zero-scale output voltage VOZS 2.932 3.002 3.072 V VCCA = VCCD = 5.00 (V) VRIN = 3.000 (V) Output resistance R O 192 240 288 W Ta = 2 5°C Supply current ICC — 92* 152 mA VCCA = VCCD = 5.25 (V) VRIN = VROUT1 * : VCCA = VCCD = 5.00V Parameter Symbol Value Unit Remark Min. Typ. Max. Maximum conversion rate FS 60 — — MSPS T erminated A. OUT pin with 240W , C L = 15pF Output propagation delay time tpd — 7 — ns Output rising time tr — 5 — ns Output falling time tf — 5 — ns Setting time tset — 17.5 — ns

1.5V tsetHL tWL Data Input tsu th 1.5V VOZS VOFS –1/2 LSB –1/2 LSB tsetLH tpdLH tpdHL tftr 90% 50% 10% Clock Input Analog Output Input R 1 ~ 10 G 1 ~ 10 B1 ~ 10 1023 Output R OUT G OUT BOUT 5.000V 3.002V 5.000V 3.000V (VCCA ) VOFS VOZS (VRIN) n DAC OUTPUT VOLTAGE RANGE 1LSB 2mV

n CALCULATION OF DAC OUTPUT VOLTAGE AT IDEAL CONVERSION n NOTES ON USE 1. Power Supply Patterns of the PCB The power supply wire patterns (VCC and GND patterns) of the PCB should be designed as wide as possible in order to reduce parasitic impedance. 2. Switching Noise In order to reduce switching noise as much as possible, noise limit capacitor must be connected between VCCD and D. GND pins and VCCA and A. GND pins. In this case, the capacitor should be connected to the GND pins side as near as possible. R OUT (GOUT , BOUT ) = VCCA – X ( VCCA – VRIN ) 1024 1023 – N [ N : Digital Input Code (0 to 1023) ] VOFS = VCCA VOZS = VCCA – X ( VCCA – VRIN ) 1024 1023 VCCD 0.01mF 47mF 47mF 0.01mF 2.2mH2.2mH VCCA R 1 to 10 G 1 to 10 B1 to 10 D. GND A. GND ROUT G OUT BOUT VROUT2 VRIN VROUT1 COMP 0.1mF Data Input CLK Input Connect to VROUT1 , VROUT2 , or external reference voltage source. CLKR CLKG CLKB n TYPICAL CONNECTION EXAMPLE

(FPT -48P-M15) 48 pin, Plastic QFP +0.05 –0.01 +.002 –.0004 +0.30 –0.10 +.012 –.004 0.15 .006 12.00 .472 0.05(.002)MIN (STAND OFF) "B" (.033±.012) 0.85±0.30 0~10° 0.15(.006)MAX 0.50(.020)MAX 0.20(.008) 0.15(.006) "A" SQ SQ (.602±.016) LEAD No. 0.80(.0315)TYP 48 13 2437 36 25 11 2 Details of "B" part INDEX 0.10(.004) REF (.346) (.535±.016) 8.80 13.60±0.40 2.70(.106)MAX 0.30±0.06 15.30±0.40 Details of "A" part

1994 FUJITSU LIMITED F48025S-1C-1C

Dimensions in mm (inches).

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan T el: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A. T el: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10

63303 Dreieich-Buchschlag

T el: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New T ech Park Singapore 556741 T el: (65) 281 0770 Fax: (65) 281 0220 F9703 ª FUJITSU LIMITED Printed in Japan