MB4051 FUJITSU | Alldatasheet
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8-CHANNEL 10-BIT A/D CONVERTER Eation 1.0 ‘The Fujitsu MB4051 is a general purpose analog-to-digital converter (ADC) which features eight channels of analog inputs, 10-bit parallel data 1/0 port and programmable control register. Analog input signal on a selected input G channel is converted to 10-bit digital data by the successive-approximation L s technique which provides high-speed conversion. The MB4051 is packaged AE in a standard 42-pin dual in-line packages. © Multiplex S-channel Analog In- © Input Impedance: over 500k CERAMIC PACKAGE puts {for 6.5V Input) DIP-42c-A01 ‘© Resolution: 10 bits © Builtin High Stabilized Reference © Relative Accuracy: 8 bits Min. Voltage Source © Linearity: #1/2 LSB © Directly Connectable to OMA Controller as well as Micro: : © Successive-Approximation Tech- processor nique: 50 us/ch Max. at foux = - 260KH2 © TTL Compatible Digital 1/0 Port © Analog Input Voltage Range: ® Standard 42-pin DIP PLASTIC PACKAGE OV 0 6.6V © Power Supplies: +5V and +8V © Analog Input Bies Current: 144 © Power Consumption: 400mW Typ. Max. PIN ASSIGNMENT 7 ABSOLUTE MAXIMUM RATINGS {All Voltage referenced to A.G/D.G) (ror VIEW) qi 42b Reset B03 0B RAW eds sop en STARTS UP IRS co * ape CLK 7 3609 ¥ cevids 3402 Ref OUT 11 22b04 and ap Digital Input Voltage -05 10455 reads dope pac out 14 2bo, ~ * SUM NODE 15 2a Dy ve (av) g17 26p cb Aedia aba 5 7 sq20 nba Te ste ice Grouitry to provect the NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM — | [hit deuce conains cotta oe RATINGS are exceeded. Functional operation should be restricted to. | ages or slectric fields. However. it is advised the conditions as detailed in the operational sections of this data | Shet_normal Parcaion Om Peet max. sheet. Exposure to absolute maximum rating conditions for extended | frum rated voltages 10. this high impedance periods may affect device reliability. Sireuit! 7-3
Fig. 1— MB4051 BLOCK DIAGRAM ADC CLK Z AC COMP ro} a E tHe 05s ull Hi Data Outputs DAC OUT — — vo erf-H 0p t0 Oy. nly HH Anaiog Inputs Ss E> - = Ag to Az = FAfaz- 99 «488 ~ IA 8 2 oF e é]| > [-« ka ; - | citar cs [740 Oy OE + cn ae 7 Ce Vv Vee vt Parameter Symbol [me Te [me NOTE: The negative value means “flow of current” from IC to out side of IC. 7-4
i MPX Selects one channe! from 8-channel analog input signals. Channel assignment is done by the 2nd thru 4th bits of control register which are programmed by the external channel select inputs Bp thru B or by a data from MPU. Comparator Compares an unknown analog input signal with an output signal of built-in DA converter. The result of comparison is transferred to the successive- approximation register (SAR). 10-bit digital-to-analog converter. Generates analog signal corresponding to digital signal specified by the SAR. Successive- According to the result from the comparator, generates the next step digital Approximation output to be transferred to the DAC and compared in the comparator. Register Composed of 10-bit register and control logic. After completion of data: conversion, acts as the data register (DR). Status Register 10-bit register which indicates the status of operations. Indicates the as- signed channel by SR-2 to SR-4, status of the external control/MPU by ‘SR-5, operation of AD conversion by SR-6 and completion of AD conver- sion by SR-7. (See Table 1, 2 of page 14) cR Control Register 10-bit register which controls the operation of ADC. Assigns a channel by CR-2 to CR-4, switches MPU/external contro! each other by CR-5, initiates AD conversion by CR-6. (See Table 1, 2 of page 14) Data Register Stores a 10-bit data at the completion of AD conversion. Outputs the data at DE=1 during the external control mode (CR-5=5). If the OR is selected (CS=0, RA=0, and R/W=1) during the MPU control mode (CR-5=1), the contents can be read by MPU (EN=1). VO BF Input/Output Connected to the data-bus of MPU for sending or receiving the 10-bit data. Buffer The output is three-state TTL compatible. CTL Control Logic Controls sending and receiving of data between blocks and used for initial- izing. Reference Voltage Specifies the maximum analog input signal level of ADC. Regulator 7-5
(ESA FUJITSU AUNIEEIMELE MB4051 Ag to Ay Analog Input Analog input terminals of 8 channels, one of which is assigned by CR2 to cra, Do to Dy Data I/O Port Connected to 10-bit parallel data-bus for transferring 10-bit data between Do --. MSB internal registers and MPU. Da .... LSB [| Siesace | Capatoa emer Ade wes biecea no Register Address input for the internal registers. Selects the data register (DR) at Address RA=0 and the control register (CR) /status register (SR) at RA=1, Enable Signal Input for the enable signal of MPU system. EN is used as timing for data transfer between MPU and ADC. Bo to By | External Channet When ADC is controlled external (CR-5=0), the inputs from Bg to By are Select Input set in CR-2 to CR-4 at the falling edge of START. (See Table 3 of page 14) START AD conversion starts at the rising edge of START when the external 7 contro! mode (CR-5=0). cc/iRa Indicates the completion of data conversion. After completion of data (Open Conversion Complete/ | conversion, CC goes low at the external control mode (CR-50) or IRG Collector} Interrupt Request goes low at the MPU control mode (CR-5=1). In both cases, they go high after the content of the data register is read. Data Enable During DE=1 at the external control mode, the data in a register assigned by RA are output on Dg to Dg. ADC CLK ‘AD Conversion Clock for AD conversion which is input to the SAR and determines the Clock conversion speed of ADC. A data conversion is completed by 12 cycles of lock. Not required to synchronize with the EN (Enabie) signal from MPU. system. Minimum cycle time of this clock is 2us. Ref OUT/ Reference Output/ Terminals for output of reference voltage which specifies the full-scale Ref ADJ Reference Adjustment | value of analog input signal and for its adjustment. AMP COMP/ | Amplifier Terminals for frequency adjustment of the internal operational amplifier Compensation/ with connected capacitors having specified capacitances. DAC COMP/ | DAC Compensation’ | SUM NODE is also used for offset adjustment. DAC OUT/ DAC Output/ SUM NODE | Sum Node V'NcclN™ Terminals for To be supplied +8V, +5V and ~BV, respectively. (Note 1) Power Supply GA/GD Analog Ground/ Terminals for ground. Digital Ground NOTE 1: MB3758 DC-DC Converter is available, which generates +8V and ~BV from signal +5V power supply. 7-6
‘RE EEE FUJITSU MB4051 tii 1. ANALOG CIRCUIT CHARACTERISTICS (Vee = +8V, V* = +8V, V> = -8V, Ta = -30°C to +85°C) Unit [ me | re | me | ee ee ee ec “Tome [fae fer [ame | Differential ee Drift 7 Fes [fa | ewe | Full Scale Positive Power 10 mviv avi5% Power Supply ‘Supply Fluctuation ‘Suppressing Negative Power Ratio surely -05 mvv -BV15% Pec [ff fe [rane] Analog Input Peewee | | fe Reference Vol a Positive Power 2 Supply ‘Suppiy Current Negative Power “7 Supply ee eo 7-7
‘AL FUJITSU ine MB4051 2. DIGITAL CIRCUIT DC CHARACTERISTICS ‘Symbol Condition [se [ve | om | ” Voc = 4-75V. Vig = 2V, Output High Voltage Vou | Vi = 0.8V, fon = -2.6mA v Woon A 7ev. [iwcim |] [| Output Low Voltage Vor Vin = 2V, v ana ve Output Current vie ey (tf State) ce = 8 ua Vi. = 0.8V Vo =04V Input High Current Ag to Az, Reset = GND, Supply Current leo Veg = 5.25V 7-8
- DIGITAL CIRCUIT AC CHARACTERISTICS (Vcc = +8V25%, V* = +8V, V" = -BV, Ta = -30°C to +85°C) ADC CLK ‘Symbol Condition | me [ome | | ee ee oom ef fe | fe | Read Mode Condition Unit |» [ove [om | CS RAW. RA Setup Time p= | fet | fe +: See page 11 7-9
‘SACU FUJITSU (IMEI = -MB4051 Write Mode ‘Symbol Condition pe ee [aan fw | = |p Retin fe |p |p fee fe | [*, | [=| fame we | | | External Control AD Conversion: ‘Symbol Condition eT fam fe | [=| | |=] femme fe | ff External Control Read Mode ‘Symbol =e [| ee ee ee ee ee [ammrmenss fe [wr | [=f +: See page 11 7-10
‘ROM RI FUJITSU MB4057 HIIHBINENI ADC CLK w wer ow vv a wn = toy READ Timing Diagram ~ anna €N 1.3V 1.3V PWEN: ad CD 7 / » “ | | “ A 0 ra ve oa ee Se |_| a ‘EEN DEN Vou iRGe) 13 eo, +: TRGlis reset to "1" when DR is read or Fleset goes low, 7-11
-----H HH ow PWEN av he c| ov “ | “ av ov External Control AD Conversion Timing Diagram wv Le wv av ae ” tes, ‘BH Pwsi External Control Read Timing Diagram eee DE 13V w a von ao aaa ~ Vou e 1.3V | a TTT TT Von tEDE ‘ope PwoEH: 7-12
‘ANON FUJITSU MB4051 ‘HiT 4. SWITCHING CHARACTERISTICS TEST CONDITIONS Fig. 2—3-STATE OUTPUT LOAD CONDITION Fig. 3 - OPEN COLLECTOR OUTPUT LOAD CONDITION vee Test Pin frome Test Pin Veo Sy D9 10 Dp nema TRG, tans tzu: CL = 15pF oe tz. tz: CL = SpF CL = 159F 5. SWITCHING WAVEFORM Enable, Disable Time (3-State Output) av Tm av EN, DE 13 EN, DE 1av Hv a 7 TZ tz | S1,S2 Close ——— =45vV 18V w Gee 13 o ——Losy_ ov =P Vou Ze Hz =45v e—t— vo, @ 1.3V “ Tosv ——— <= OV Ss; Close ty 'S} Open Se Sz Close Note $1.52: See Fig. 2, above TRG of CC Recovery Time (Open Collector Output) wv EN, OE 13V eN-iRG (S28) TA con sv Oe 13V fA av, 7-13
TYPICAL CHARACTERISTICS CURVES Fig. 4— OUTPUT VOLTAGE Fig. 5 — OUTPUT HIGH VOLTAGE vs. INPUT VOLTAGE vs. OUTPUT HIGH CURRENT aaa 4 —_ T ——-se ee ee s + | TT : vay } [rte || ; is
3 Tan 2c 2 &
j L teed [[] | j ann a Ta = 88°C! 3 2 ‘ tt} NJ 335 a Vis Inns Vohape low Output High CventimAl Fig. 6 — OUTPUT LOW VOLTAGE Fig. 7 — INPUT CURRENT vs. ¥s.OUTPUT LOW CURRENT INPUT VOLTAGE (Bp INPUT) _ 38 Wee = ev | a 7 A r = § Ta = -30°C Tan 2c 4m SL 3 02] g-0 i i mmm COE oa a a Joy Ono Law Curent ima} Vn too Votage 1 Fig. 8 — DELAY TIME vs. AMBIENT TEMPERATURE mT TET TI 2.1) | Eb oT z “lS {rr ce ee a tL ETT a At TTT TTI as a5 2098500 Ta, Ambient Temperature (°C) 7-14
TYPICAL CHARACTERISTICS CURVES (continued) Fig. 9 — SUPPLY CURRENT Fig. 10 — SUPPLY CURRENT vs. vs. SUPPLY VOLTAGE POSITIVE SUPPLY VOLTAGE Tee | | “Forbin [| ere CCT TE = & | a) — 5d io OE ee Ve. Supply Voltage (v) \\V*, Positive Supply Voltage (V) Fig. 11 — SUPPLY CURRENT vs. Fe VAEPERENGE VOLTAGE “ NEGATIVE SUPPLY VOLTAGE SUPPLY VOLTAGE (V*, |V"I) wt tT Tere TT] : es ee a #2 || — 7 bee) yee aii aE LETT tot V", Negative Supply Voltage (V) V".IV"L Supply Voltage (V) Fig. 13 — OPERATION WAVEFORM béerininsashe rica aoc cx PRES PTT TTT TTT Tye Hea tt LN onc out ET TT cucu [aq] [ey fas] | | | Analog Input Voltage = 2.1646V_ 7-15
Table 1. BIT CONSTRUCTION OF DR AND S/C R Table 2. CHANNEL SELECT FOR MPU CONTROL Table 3. CHANNEL SELECT FOR EXTERNAL CONTROL
MB4O51 |IiBliBIIHIIN According to the status of 5th bit (CR-5) in the built-in control register, ADC has two operation modes: external control ‘mode and MPU control mode. Just after an initialization (Reset going from low to high}, ADC is in the external control mode (designation of channel, start of data conversion and data output are controlled through the external control input terminals). This mode is useful for ADC applications only or for DMA operation independent of MPU. When the MPU control mode is required, set CR-5 of the control register high through MPU. EXTERNAL CONTROL MODE (CR-5=0): This mode is used when ADC is controifed by the external hardware, An analog input signal channel is designated by By to Bp and the AD conversion starts at the second rising edging of ADC clock after START goes low. At the completion of 10-bit data conversion, CC (Convert Complete) goes low to notify it to external devices. The converted data is read after the low state of CC and DE goes high. ADC TIMING FOR EXTERNAL CONTROL MODE ascexk FLPLEFLEFLIFLISLILFL LU Li. START Bo to By SAR ‘Successive Data Read orernat Lateh oternal Reset ‘Approximation ve I \\ 7-17
MPU CONTROL MODE (CR-5=1): This mode is used when ADC is controlled by the MPU software. Because of CR-5=0 at initialization, CR-5 should be set high through MPU. After completion of the conversion, CR-7 (IRQ flag) is set high and TRO output goes tow to interrupt MPU ‘operation. After confirming (RO=0, MPU starts the interrupt routine to select the data register of ADC and reads it. After MPU reads the data register, IRQ is reset high. In this mode, all signals on START and By to Bz are ignored. When the ADC is required to return to the external control mode, CR-5 is set low through MPU or RESET is set low. ADC TIMING FOR MPU CONTROL MODE CR Set DR Read RW \\ w K Ya X Dp t0 D: —+ \\——— ° —T>- vel t « “LE LI “LIL Correspond Internat signal of START iF | Correspond C© 7-18
MB4051 _iilifihlnMlNl DEFINITION OF TERMS EXAMPLE OF RESOLUTION (3-BIT RESOLUTION) Resolution: ‘The minimum distinguishable analog deviation in AD con verter. Since MB4051 is 10-bit AD converter, it is possible to resolute an analog signal, from OV to 6.5V (FSR), into 210 = 1024 parts. 110 3 101 8 100] Bo : a : 001 oro : ‘00 i
0 FSA-LS
Relative Accuracy: Deviation between a straight line from the zero point of the device (all “O”) to the full-scale point (all ‘L’) and an actual conversion characteristic curve. ant vy Gain Error: . 3 Y; Difference between an ideal input voltage span and an 3 q actual input voltage span. In the MB4051, according to the é procedure described separately, it is possible to adjust the 3 Vi Actual gain error to zero. $ Wy co Offset Error: ao’ i Difference between an ideal cirtical input voltage which oO on input 1M makes all output bits zero and an actual critical input inalog Input voltage. In the MB4051, such offset error can be adjusted according to the procedure described separately. + Felative Accuracy = 9A sn Erg » V2= Vo) ~ (6) ~ Eo) Gain ‘= 100 (% of FSR) ~No-fo Otfeet Error = “OFS. 100 (% of FSA 7-19
DEFINITION OF TERMS (Continued) DIFFERENTIAL LINEARITY ERROR (AL: Differentia! Linearity Error: Matsa) Input voltage deviation from an ideal input voltage which is necessary to change the output code as large as 1LSB. The differential linearity error of #1/2LSB means that, when the input signal changes 1/2LS8 to 3/2LSB, digital code varies 1LSB. 8 : 2 -~Featse a 1188 Analog Input Example of Output Coding Input Voltage: Yoooovoont f12346678§ ee XE 08 [__om | eoooteoove [se] er Povo eee| 7-20
ADJUSTMENT OF OFFSET AND GAIN In the MB4051, Both gain-error and offset-error can be adjusted to zero by trimmers connected as shown below. In this case, potentiometers and resistors for trimmers should have temperature characteristics below 100 ppm/°C to ensure long-term stability and less temperature drift. The following external adjustment circuits should be located as near as possible to the package. GAIN ADJUSTMENT a Ref OUT Ry 12S 0K " 20T 2 Ref ADJ Po ag Offset Agiustment +8V ~ NK 39ma Fo lore 5] sum wove Vv Offset Adjustment By applying the voltage of 1/2LSB, i.e., 3.2mV to an analog input channel, continuously execute AD conversion of the applied input voltage. Then, adjust potentiometer Ry during the conversion so that the conversion results become “0000000000" ‘and "0000000001", alternatively. The range of adjustment is about +0.2% of FSR in the circuit shown below. ‘The Rg resistor for offset adjustment can be replaced with smoller resistors as follows. sev 190k2 180k ‘SUM NODE Ra 100k 1s 20T t0Ks2 7-21
(GENE ~ MB4O51 GAIN ADJUSTMENT After offset adjustment, by applying FSR-3/2LSB (6.4905V) to an analog input, execute AD conversion of the applied input voltage. Then, adjust potentiometer Ry during the conversion so that the conversion results become 1111111111" and 1111111110", alternatively. The range of adjustment is about -12% to +5% of FSR in the circuit shown, PRECAUTIONS FOR CIRCUIT STABILIZATION To stabilize the ADC operation and by-pass power supply line noise, connect the external Capacitors as shown. CAPACITORS FOR STABILIZATION AND POWER SUPPLY BYPASS. +51 8) Yeo BV —> 2 ive = 50pF: or 15) SUM NODE }000 |AMP COMP 26 Bypass capacitor for filtering line-noise should have good high-frequency characteristics and should be connected as near as possible to the package. If a printed circuit board is used, the ground-line should be made as wide as Possible and the pattern should be made in such 2 manner that the analog input signal fine does not pick up noise from the digital signal and so on. Unused digital input should be kept in an inactive state listed below and unused analog input should be connected to analog ground (GA). 7-22
MB4051_/Mii/NHIEHAN EXAMPLE OF INTERFACE TO 8-BIT MPU (PROVIDE A CHANGE CIRCUIT FOR UPPER 2-BITS) a = i 3 iRG ve] 17 0 +8V a toowa a ee bean ote AS " |, | ee Oe er out — Cl, = ea od ain === ig We ie [Az = 4 | oa to RA - C veel? osv 7 ase; tie [aha nof22——oche D7 iH D> H Analog input 2] — 38} 5, «sB) 7-23
A §~=MB4051 42-LEAD CERAMIC DUAL IN-LINE PACKAGE (CASE No.: DiP-42C-A01) Fs” yy 898" OF .600+.010 n88% Toman “| Jb |s774.so1max
100.010 LL ore*:908
eee 040.004 — 7,003 .050#.010 7-24
MB4O51 _ilft HN PACKAGE DIMENSIONS (continued) 40-LEAD PLASTIC DUAL IN-LINE PACKAGE {Case No.: DIP-40P-M01) pt 0888 — — 1 lannagnnanaaanaAnanaan ' pees max \\ 5434010 | li 800.25) INDEX 600(15.24) / WP eee UUUVUUUUUUUU UU 1 = 20 920 0101.002 - a 0252008 1.277355) CANOAURURIADAOAURDAQADADRURONUEGRORGRDSDD: 19514 96) MAX 8 b i 118(3.00) MIN: 09012 29) 1001254) 018+ .003 0200.51) MIN 7 max TP (0462008) Dimensions in