MB40166 FUJITSU | Alldatasheet

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DS04-28500-5EFUJITSU SEMICONDUCTOR DATA SHEET ASSP AD/DA CONVERTER MB40166/MB40176 1-CHANNEL 6-BIT AD/DA CONVERTER WITH CLAMP CIRCUIT The Fujitsu MB40166 and MB40176 are low power 6-bit AD/DA converter which is fabricated with Fujitsu Advanced Bipolar T echnology. MB40166 and MB40176 have the same basic circuits and functions, with the only difference being that MB40166 has an independent analog input terminal for the A/D section and a clamp voltage output terminal, while MB40176 has an analog input in the A/D section internally connected with the clamp circuit. Since both models contain a single-chip clamp circuit and a reference voltage circuit, they are ideal for video signal processing.

  • Resolution :6 bits
  • Linearity Error : –0.8% max.
  • Maximum Conversion Rate :20 MSPS min.
  • Analog Input Voltage Range :V REF to VCCA (MB40166) 0 to 1.0 V (MB40176)
  • Analog Output Voltage Range :VCC to VCC -1 V
  • Digital I/O Level :TTL Level
  • Power Supply Voltage :+5 V
  • Power Dissipation:300 mW typ.
  • Package 28pin Plastic FLA T Package (Suffix : -PF) 28pin Plastic DIP Package (Suffix : -P) NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (see NOTE) Rating Symbol Value Unit Power Supply Voltage V CCA , VCCD -0.5 to +7.0 V Digital Input Voltage V IND -0.5 to +7.0 V Analog Input Voltage V INA -0.5 to VCCA +0.5 V Storage T emperature T STG -55 to +125 °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. PLASTIC PACKAGE DIP-28P-M03 PLASTIC PACKAGE FPT -28P-M01

(MSB) D.GND V CCD A.GND V CCA VOUT COMP V REF VINA VCLMP (N.C.) V CCA A.GND V CCD D.GND MB40166 (FPT -28P-M01) (DIP-28P-M03) DACK D D1 D D2 D D3 D D4 D D5 D D6 DA6 DA5 DA4 DA3 DA2 DA1 ADCK D.GND VCCD A.GND V CCA VOUT COMP V REF C 2 C 1 VIN VCCA A.GND V CCD D.GND MB40176 (FPT -28P-M01) (DIP-28P-M03) (TOP VIEW) (TOP VIEW) Note : The functions of the terminals within the dotted lines above are different for MB40166 and MB40176. (MSB) (LSB) (LSB) (MSB) (LSB) (LSB) (MSB)

  • MB40166 Note : The circuits within the dotted lines above are different for MB40166 and MB40176. COMPA.GNDD.GND V CCD VCCA CLAMP 0.8VCCA 0.8VCCA DA1 DA2 DA3 DA4 DA5 DA6 R 1 R R R R 2 VCCA ADCK VREF MASTER VOUTSLAVE REGISTER BUFFER CURRENT SWITCH DACK D D1 (MSB) to D (LSB) 6 6 6 LA TCH BUFFER 63 to 6 ENCODER 20VCLMP REFERENCE VOLTAGE GENERA TOR 0.8VCCA VINA R-2R RESISTOR NETWORK 28 17 26 18 2516 27 23 (LSB) (MSB)

n BLOCK DIAGRAM (Continued)

  • MB40176 Note : The circuits within the dotted lines above are different for MB40166 and MB40176. CLAMP 0.8VCCA 0.8VCCA DA1 DA2 DA3 DA4 DA5 DA6 R 1 R R R R 2 VCCA ADCK VREF MASTER VOUTSLAVE REGISTER BUFFER CURRENT SWITCH DACK D D1 (MSB) to D (LSB) 6 6 6 COMPA.GNDD.GND V CCD VCCA LA TCH BUFFER 63 to 6 ENCODER 19VIN C 1 C 2 REFERENCE VOLTAGE GENERA TOR 0.8VCCA R-2R RESISTOR NETWORK 28 17 26 18 2516 27 23 (LSB) (MSB)

Pin No. Symbol I/O Function 40166 40176 A/D 21 – V INA I Analog signal input. –1 9 V IN I

22 V REF O

Reference voltage output. Reference voltage divided by the resistors, with the output voltage set to 0.8 x V CCA (V). 8 to 13 D A1 to DA6 O Digital signal outputs. (DA1: MSB, DA6: LSB) 20 – V CLMP O Clamp voltage output. –2 0 C 1 – Clamp capacitor is connected between these pins. –2 1 C 2 – 14 ADCK I A/D conversion clock input. D/A 24 V OUT O Analog signal output. 2 to 7 D D1 to DD6 I Digital signal input. (DD1 : MSB, DD6 : LSB)

23 COMP –

Phase compensation capacitor is connected. Insert a capacitor of 1 mF or more between this pin and A.GND. 1 DACK I D/A conversion clock input. Common 18, 25 V CCA – Power supply for analog circuit. (+5 V) 16, 27 V CCD – Power supply for digital circuit. (+5 V) 17, 26 A.GND – Ground for analog circuit. (0 V) 15, 28 D.GND – Ground for digital circuit. (0 V) Other 19 – (N.C.) – No connection.

n RECOMMENDED OPERATING CONDITIONS n ELECTRICAL CHARACTERISTICS Note : *VCCA =VCCD =5.0V Parameter Symbol Value Unit Remarks Min Typ Max Power Supply Voltage V CCA , VCCD 4.75 5.00 5.25 V Analog Input Voltage VINA VREF –V CCA V MB40166 VIN 0 – 1 V MB40176 Digital High-level Input Voltage V IHD 2.0 – V Digital Low-level Input Voltage V ILD –– 0 . 8 V Clock Frequency f CLK –– 2 0 M H z Clock Pulse Width at High Level tW + 20 – – ns Clock Pulse Width at Low Level tW - 20 – – ns Set-up Time t S 12.5 – – ns Hold Time t H 7.5 – – ns Phase Compensation Capacitance C COMP 1.0 – – mF Clamp Capacitance C CLAMP 1.0 – – mF Reference Voltage Capacitance C VREF 1.0 – – mF Operating T emperature Ta 0 – 70 °C ANALOG CIRCUIT DC CHARACTERISTICS (VCCA =VCCD =5V –5%, T a=0 to 70°C) Parameter Symbol Condition Value Unit Remarks Min Typ Max Resolution – – – 6 Bits Linearity Error LE DC – – –0.8 % Analog High Level Input Current I IHA VINA = VCCA –8 . 5 2 5 mA MB40166 Analog Low Level Input Current I ILA VINA = VREF –7 . 5 2 3 mA MB40166 Equivalent resistance for Analog Input RINA VCCA - VREF IIHA - IILA 400 – – k W MB40166 Analog Input Current I IN -400 – – mA MB40176 Reference Voltage V REF *3 . 9 4 . 0 4 . 1 V Clamp Voltage V CLMP –V REF –V Full-Scale Output Voltage V OFS –V CCA –V Zero-Scale Output Voltage V OZS –V REF –V Output Resistance R O –2 4 0– W Power Supply Current I CC – 60* 90 mA

n ELECTRICAL CHARACTERISTICS (Continued) DIGITAL CIRCUIT DC CHARACTERISTICS (VCCA =V CCD =5V –5%, T a=0°C to 70°C) Parameter Symbol Condition Value Unit Min Typ Max Digital High-level Output Voltage V OHD IOH =-400 mA2 . 7 – – V Digital Low-level Output Voltage V OLD IOL =1.6mA – – 0.4 V Digital High-level Input Voltage V IHD 2.0 – – V Digital Low-level Input Voltage V ILD –– 0 . 8 V Digital High-level Input Current I IHD –– 2 0 mA Digital Low-level Input Current I ILD -100 – – mA SWITCHING CHARACTERISTICS (VCCA =V CCD =5V –5%, T a=0°C to 70°C) Parameter Symbol Condition Value Unit Min Typ Max Maximum Conversion Rate F S 20 – – MSPS Digital Output Delay Time t PDD 81 5 3 0n s Analog Output Delay Time t PDA –1 3– n s Analog Output Rise Time t r –1 5– n s Analog Output Fall Time t f –1 5– n s

  1. Timing Chart for A/D Conversion 2. Timing Chart for D/A Conversion Sample N Sample N+1 Sample N+2 tW + tW - VOHD VOLD 3 V 0 V 1.5 V tpdD

1.5 V DATA N-1 DATA N DATA N+1

A/D conversion clock input (ADCK) Analog signal input (VIN) Digital signal output (DA1 to DA6) D/A conversion clock input (DACK) Analog signal output (VOUT ) Digital signal input (DD1 to DD6 ) tS th tW + tW - tr tf 10% 50% 90% 90% 50% 10% tPLHA tPHLA 3 V 0 V 1.5 V 3 V 0 V 1.5 V VOFS VOZS

n A/D CONVERSION CHARACTERISTICS n D/A CONVERSION CHARACTERISTICS 63 111111 62 111110 61 111101 33 100001 32 100000 31 011111 02 000010 01 000001 00 000000 4.000 V VINA, VIN 4.992 V Actual conversion characteristics 63 111111 62 111110 61 111101 33 100001 32 100000 31 011111 02 000010 01 000001 00 000000 VFTLEn max = Linearity Error LE61 LE33 LE32LE31 LE2 LE1 STEP , OUTPUT CODE STEP , OUTPUT CODE Ideal conversion characteristics (1LSB=16 mV) FS VINA, VIN VZT Ideal conversion characteristics (1LSB=16 mV) 5.000 V 4.984 V Actual conversion characteristics LSB MSB 0 000000 1 000001 2 000010 33 100001 32 100000 31 011111 63 111111 62 111110 Input Code Step A.OUT A.OUT 4.520 V 4.504 V 4.488 V 4.024 V 4.008 V 3.992 V LE62 LE33 LE32 LE31 LE2 LE1 VOFS VOZS 0 000000 1 000001 2 000010 33 100001 32 100000 31 011111 63 111111 62 111110 Input Code Step

n FUNCTIONAL DESCRIPTIONS CLAMP CIRCUIT The clamp circuit contained in MB40166/MB40176 is a peak detector type, in which the top of the sync of the composite sync signal is clamped. Clamp voltage is common to the reference voltage (0.8 x V CC ) of A/D and D/A circuits.

  • MB40166 (1) Providing a clamp circuit (2) Directly feeding the signal at the VINA pin Clamp VCLMP A/D VINA (DA6 to DA1)( D D1 to DD6 ) D/A VOUT - + A 1 V VCCA VREF VCCA VREF Given voltage Input level at A Input level at V INA pin Output level of V out 78 213 A/D D/A VOUT VCCA VREF VCCA VREF Input level at VINA pin Output level of V out 78 213 24VINA (DA6 to DA1)( D D1 to DD6 )
  • MB40176 A/D VIN (DA6 to DA1)( D D1 to DD6 ) D/A VOUT - +

1 V VCCA

Input level of C2Input level at VIN pin Output level of V out 78 213 C 1 C 2 CLAMP A. GND

n ANALOG INPUT EQUIVALENT CIRCUIT

  • MB40166
  • MB40176 VCCA A.GND VINA Equivalent circuit of clamp circuit block VCLMP 100 W ADC analog input equivalent circuit 20 21 400 kW 0.8 x VCC + VBE x 63 Circuits 20 21 VCCA A.GND Equivalent circuit of clamp circuit block ADC analog input equivalent circuit - + C 1 C2 VIN 400 kW 0.8 x VCC + VBE 4 kW 100 W x 63 Circuits

n DIGITAL INPUT EQUIVALENT CIRCUITS

  • MB40166/MB40176 VCCD D.GND 50 kW 3.2 kW 50 kW 1.6 kW 1.6 kW ADCK VT 1.4 V~ Digital input equivalent circuit of A/D converter block VCCD D.GND 50 kW 50 kW Digital input equivalent circuit of D/A converter block D A1 to D A6 DACK VT 1.4 V~

n TYPICAL CONNECTION EXAMPLE

  • MB40166 Note : If the clamp circuit is used, connect VINA with VCLMP . If the clamp circuit is not used, do not connect VINA with VCLMP . VCC VCCA VCCD VCLMP VINA VOUT DA ADCK DACK D D CONTROLLER MB87045 MEMORY MB81464 MB40166 COMP D.GNDA.GND 18 2725 16 17 2826 15 VCLMP VINA N.C. VOUT VREF COMP MB40166 VCCA VCCDVCCDVCCA D.GNDA.GND D.GNDA.GND (MSB) (LSB) (LSB) (MSB) ADCK D DA6 D D6 D D1 DACK 10 mH 10 mH 3.3 mF 1 mF 1 mF 3.3 mF0.33 mF ADC clock ADC digital outputs (to controller) DAC digital inputs (from controller) DAC clock Clamp voltage output Video signal ADC input Video signal DAC output 0.33 mF

n TYPICAL CONNECTION EXAMPLE (continued) (1) Internal clamp circuit is used. (2)Internal clamp circuit is not used. *: Input voltage range for the analog input pin is VREF up to VCCA . VCCD 2.2 kW 2SA933 VCCA D.GNDA.GND Analog input pin +9 V +5 V +5 V VCLMP VINA MB401661 mF - + External component VCCD VCCA D.GNDA.GND Analog input pin * +5 V +5 V VCLMP VINA MB40166 OPEN

n TYPICAL CONNECTION EXAMPLE (continued)

  • MB40176 0.33 mF0.33 mF VCC VCCA VCCD VIN C 1 DA ADCK DACK D D CONTROLLER MB87045 MEMORY MB81464 MB40176 COMP D.GNDA.GND 18 2725 16 17 2826 15 VIN C 1 C 2 VOUT VREF COMP MB40176 VCCA VCCDVCCDVCCA D.GNDA.GND D.GNDA.GND (MSB) (LSB) (LSB) (MSB) ADCK D DA6 D D6 D D1 DACK 10 mF 10 mF 3.3 mF 1 mF 1 mF 3.3 mF ADC clock ADC digital outputs (to controller) DAC digital inputs (from controller) DAC clock Video signal ADC input Video signal DAC output C 2 VOUT 1 mF

n TYPICAL CONNECTION EXAMPLE (continued) 1.ON-CHIP Input PNP Transistor is utilized. Note :Input impedance of VIN input pin (19) is about 20 kW , please pay attention to output impedance of signal source. 2. Input PNP Transistor of Clamp Circuit is put externally. Note : Both VIN (19) and C (20) are connected with VCCA . VCCD VCCA D.GNDA.GND Video signal input +5 V +5 V 1 mF

19 VIN

2.2 kW 2SA933 VCCA D.GNDA.GND Video signal input +9 V +5 V +5 V C 2 1 mF External circuit

inches (millimeters) 28-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT -28P-M01) ª 1994 FUJITSU LIMITED F28005S-5C .004(0.10) ˘ .005(0.13) M .402–.016 (10.20–0.40) .299–.012 (7.60–0.30) .050(1.27) TYP “A” .018–.004 (0.45–0.10) .110(2.80) MAX (MOUNTING HEIGHT) .002(0.05) MIN (ST AND OFF HEIGHT) .362–.012 (9.20–0.30) .020–.008 (0.50–0.20) +.002 -.001 +0.05 -0.02.006 (0.15 ) Details of “A” part .008(0.20) .024(0.60) .007(0.18) MAX.027(0.68) MAX .699 INDEX .650(16.51) REF (17.75 ) +.010 -.008 +0.25 -0.20

inches (millimeters) 28-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-28P-M03) ª 1994 FUJITSU LIMITED D28012S-3C 1.024+.008 -.012(26.00 )+0.20 -0.30 .358–.010 (9.10–0.25) INDEX-1 .020(0.51)MIN .191(4.85)MAX .118(3.00)MIN .400(10.16) TYP 15°MAX .039+.020 (1.00 )+0.50 INDEX-2 .070(1.778)MAX .010–.002 (0.25–0.05) .018–.004 (0.45–0.10) .910(23.114)REF .070–.007 (1.778–0.18)

For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT , 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211, Japan T el: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A. T el: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10

63303 Dreieich-Buchschlag

T el: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 T el: 336-1600 Fax: 336-1609 F9601 ª FUJITSU LIMITED Printed in Japan All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Com- plete information sufficient for construction purposes is not nec- essarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu as- sumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.