MB2821 PHILIPS | Alldatasheet

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Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) 1August 24, 1993 853-1670 10620

FEATURES

  • 20-bit positive-edge triggered register
  • Multiple VCC and GND pins minimize switching noise
  • Live insertion/extraction permitted
  • Power-up reset
  • Power-up 3-State
  • Output capability: +64mA/–32mA
  • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
  • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

DESCRIPTION

The MB2821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The MB2821 has two 10-bit, edge triggered registers, with each register coupled to ten 3-State output buffers. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay nCP to nQx C L = 50pF; VCC = 5V 4.6 ns C IN Input capacitance VI = 0V or VCC 4 pF C OUT Output capacitance VO = 0V or VCC ; 3-State 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 120 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 52-pin plastic Quad Flat Pack -40°C to +85°C MB2821BB 1418B PIN CONFIGURATION LOGIC SYMBOL È È È È È È Vcc 1Q3 1Q2 1Q1 1Q0 1OE 1CP 1D0 1D1 GND 1D2 1D3 Vcc Vcc 2Q6 2Q7 GND 2Q8 2Q9 2OE 2CP 2D9 2D8 2D7 2D6 Vcc 19 2220 231716 25 26 241514 21 18 188 2Q1 1Q9 2Q2 GND 1Q6 2Q4 2Q5 2Q3 1Q5 2Q0 1Q7 1Q4 1 47 4446 434950 41 40 425152 45 48 1D9 2D2 2D0 GND 1D7 1D6 2D4 2D5 2D3 1D5 2D1 1D8 1D439 MB2821 52–pin PQFP 45 44 42 41 39 38 37 36 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 48 49 50 51 1 2 3 5 1CP 1OE 35 34 1D8 1D9 1Q8 1Q9 6 7 33 32 31 29 28 27 25 24 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 8 9 10 11 12 13 15 16 2CP 2OE 23 22 2D8 2D9 2Q8 2Q9 18 19

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 2 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 33, 32, 31, 29, 28, 27, 25, 24, 23, 22 1D0 – 1D9 2D0 – 2D9 Data inputs 10, 11, 12, 13, 15, 16, 18, 19 1Q0 – 1Q9 2Q0 – 2Q9 Data outputs 47, 20 1OE , 2OE Output enable inputs (active-Low) 46, 21 1CP, 2CP Clock pulse inputs (active rising edge) 4, 17, 30, 43 GND Ground (0V) 14, 26, 40, 52 VCC Positive supply voltage LOGIC SYMBOL (IEEE/IEC) C2 C2 145 48 44 49 42 50 41 51 39 1 38 2 37 3 36 5 EN 35 6 34 7 133 8 32 9 31 10 29 11 28 12 27 13 25 15 24 16 EN 23 18 22 19 FUNCTION TABLE INPUTS INTERNAL OUTPUTS OPERATING MODE nOE nCP nDx REGISTER nQ0 – nQ9 L L l h L H L H Load and read register L ↑ X NC NC Hold H H X Dn NC Dn Z Z Disable outputs H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low to High clock transition ↑ = Not a Low-to-High clock transition

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 3 LOGIC DIAGRAM CP Q D nD0 nQ0 nCP nOE CP Q D nD1 nQ1 CP Q D nD2 nQ2 CP Q D nD3 nQ3 CP Q D nD4 nQ4 CP Q D nD5 nQ5 CP Q D nD6 nQ6 CP Q D nD7 nQ7 CP Q D nD8 nQ8 CP Q D nD9 nQ9 ABSOLUTE MAXIMUM RATINGS 1, 2 SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +7.0 V IIK DC input diode current VI < 0 –18 mA VI DC input voltage3 –1.2 to +7.0 V IOK DC output diode current VO < 0 –50 mA VOUT DC output voltage3 output in Off or High state –0.5 to +5.5 V IOUT DC output current output in Low state 128 mA Tstg Storage temperature range –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN MAX VCC DC supply voltage 4.5 5.5 V VI Input voltage 0 VCC V VIH High-level input voltage 2.0 V VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA Δt/Δv Input transition rise or fall rate 0 5 ns/V Tamb Operating free-air temperature range –40 +85 °C

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 4 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = –40°C to +85°C UNIT Min Typ Max Min Max VIK Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VOH High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output voltageNO TAG VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V IOFF Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA IPU/PD Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC ; VOE = Don’t care ±5.0 ±50 ±50 µA IOZH 3-State output High currentVCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low currentVCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage currentVCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA IO Output current1 VCC = 5.5V; VO = 2.5V –50 –70 –180 –50 –180 mA ICCH VCC = 5.5V; Outputs High, VI = GND or VCC 120 250 250 µA ICCL Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC 54 76 76 mA ICCZ VCC = 5.5V; Outputs 3-State; VI = GND or VCC 120 250 250 µA ΔICC Additional supply current per input pin2 VCC = 5.5V; one input at 3.4V , other inputs at VCC or GND 0.5 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency 1 160 250 160 MHz tPLH tPHL Propagation delay nCP to nQx 1 2.5 2.7 4.4 4.6 5.6 6.0 2.5 2.7 6.4 6.7 ns tPZH tPZL Output enable time to High and Low level 1.2 2.2 3.3 3.8 4.2 5.1 1.2 2.2 5.0 5.8 ns tPHZ tPLZ Output disable time from High and Low level 1.3 1.5 3.2 3.0 4.6 4.2 1.3 1.5 5.0 4.7 ns

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 5 AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MAX MIN MAX ts(H) ts(L) Setup time, High or Low nDx to nCP 2 1.5 1.0 0.6 –0.2 1.5 1.0 ns th(H) th(L) Hold time, High or Low nDx to nCP 2 1.0 1.0 0.3 –0.4 1.0 1.0 ns tw (H) tw (L) nCP pulse width High or Low 1 3.5 3.0 2.2 1.6 3.5 3.0 ns AC WAVEFORMS ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ VM VM Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM VM VM 1/fMAX tw (H) t w (L) tPHL tPLH nCP nQx VMnDx VM VM VM VM VM CP Waveform 2. Data Setup and Hold Times ts(H) th(H) ts(L) th(L) nOE VM tPZH tPHZ VOH –0.3V nQx Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level nOE tPZL tPLZ VOL +0.3V nQx Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level VM VM VM VM VM

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 6 TEST CIRCUIT AND WAVEFORM PULSE GENERATOR R T VIN D.U.T VOUT C L R L VCC R L 7.0V Test Circuit for 3-State Outputs VM VM tW AMP (V) NEGATIVE PULSE 10% 10% 90% 90% VM VM tW AMP (V) POSITIVE PULSE 90% 90% 10% 10% tTHL (tF) tTLH (tR ) t THL (tF) tTLH (tR ) VM = 1.5V Input Pulse Definition DEFINITIONS R L = Load resistor; see AC CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude Rep. Rate t W tR tF MB 3.0V 1MHz 500ns 2.5ns 2.5ns SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 7 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nCP to nQx tPLH vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nCP to nQx MAX 4.5VCC 5.5VCC MIN ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns Adjustment of tPLH for Load Capacitance and # of Outputs Switching nCP to nQx pF 20 switching 10 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPHL vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nCP to nQx MAX 4.5VCC 5.5VCC MIN pF 20 switching 10 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPZH vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx pF 20 switching 10 switching 1 switching

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 8 tPZL vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx pF 20 switching 10 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPHZ vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOE to nQx pF 20 switching 10 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPLZ vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx pF 20 switching 10 switching 1 switching

Philips Semiconductors Advanced BiCMOS Products Product specification MB2821Dual 10-bit D-type flip-flop; positive-edge trigger (3-State) August 24, 1993 9 tTLH vs Temperature (Tamb ) C L = 50pF, 1 Output Switching 4.5VCC 5.5VCC ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns Adjustment of tTLH for Load Capacitance/# of Outputs pF 20 switching 10 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tTHL vs Temperature (Tamb ) C L = 50pF, 1 Output Switching 4.5VCC 5.5VCC Adjustment of tTHL for Load Capacitance and # of Outputs Switching pF 20 switching 10 switching 1 switching Volts 0 50 100 150 200 Volts VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V pF 125°C 25°C –55°C VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V pF 125°C 25°C –55°C 125°C 25°C –55°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 50 100 150 200 125°C 25°C –55°C