MB2373 PHILIPS | Alldatasheet

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Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) 1August 23, 1993 853-1669 10587

FEATURES

  • 16-bit transparent latch
  • Multiple VCC and GND pins minimize switching noise
  • Power-up 3-State
  • Live insertion/extraction permitted
  • Power-up reset
  • 3-State output buffers
  • Output capability: +64mA/–32mA
  • Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17
  • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

DESCRIPTION

The MB2373 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The MB2373 device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates. The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is High. The latch remains transparent to the data inputs while nE is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls eight 3-State buffers independent of the latch operation. When nOE is Low, the latched or transparent data appears at the outputs. When nOE is High, the outputs are in the High–impedance “OFF” state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay Dn to Qn C L = 50pF; VCC = 5V 2.9 ns C IN Input capacitance VI = 0V or VCC 4 pF C OUT Output capacitance VO = 0V or VCC ; 3-State 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 500 nA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 52–pin plastic Quad Flat Pack –40°C to +85°C MB2373BB 1418B È È È È È È 1Q3 1Q2 GND 1Q1 1Q0 1OE GND 1D0 1D1 GND 1D2 1D3 2Q4 2Q5 GND 2Q6 2Q7 2OE GND 2D7 2D6 GND 2D5 2D4 19 2220 231716 25 26 241514 21 18 1Q7 2Q1 GND GND GND 1Q5 2Q3 VCC 2Q2 1Q4 2Q0 1Q6 VCC 1 47 4446 434950 41 40 425152 45 48 1D7 2D1 GND GND GND 1D5 2D3 VCC 2D2 1D4 2D0 1D6 VCC39 MB2373 52–pin PQFP 48 1Q0 1Q1 1Q2 1Q3 1D0 1D1 1D2 1D3 4547 2 1Q4 1Q5 1Q6 1Q7 1D4 1D5 1D6 1D7 1E1OE 8 2Q0 2Q1 2Q2 2Q3 2D0 2D21 2D2 2D3 2119 14 2Q4 2Q5 2Q6 2Q7 2D4 2D5 2D6 2D7 2E2OE LOGIC SYMBOLPIN CONFIGURATION

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 2 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 32, 31, 29, 28, 26, 25, 23, 22 1D0 – 1D7 2D0 – 2D7 Data inputs 8, 9, 11, 12, 14, 15, 17, 18 1Q0 – 1Q7 2Q0 – 2Q7 Data outputs 47, 19 1OE , 2OE Output enable inputs (active–Low) 45, 21 1E, 2E Enable inputs (active–High) 33, 36, 42, 46, 50 GND Ground (0V) 1, 13, 27, 39 VCC Positive supply voltage LOGIC SYMBOL (IEEE/IEC) 44 48 43 49 41 51 40 52 EN 38 2 37 3 35 5 34 6 32 8 31 9 29 11 28 12 EN 26 14 25 15 23 17 22 18 LOGIC DIAGRAM E Q D nD0 nQ0 E Q D nD1 E Q D nD2 E Q D nD3 E Q D nD4 E Q D nD5 E Q D nD6 E Q D nD7 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nE nOE

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 3 FUNCTION TABLE INPUTS INTERNAL OUTPUTS OPERATING MODE nOE nE nDx REGISTER nQ0 – nQ7 L L H H L H L H L H Enable and read register L L i h L H L H Latch and read register L L X NC NC Hold H H L H X Dn NC Dn Z Z Disable outputs H = High voltage level h = High voltage level one set-up time prior to the High-to-Low E transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low E transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low E transition ABSOLUTE MAXIMUM RATINGS 1, 2 SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +7.0 V IIK DC input diode current VI < 0 –18 mA VI DC input voltage3 –1.2 to +7.0 V IOK DC output diode current VO < 0 –50 mA VOUT DC output voltage3 output in Off or High state –0.5 to +5.5 V IOUT DC output current output in Low state 128 mA Tstg Storage temperature range –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 4 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN MAX VCC DC supply voltage 4.5 5.5 V VI Input voltage 0 VCC V VIH High-level input voltage 2.0 V VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA Δt/Δv Input transition rise or fall rate 0 10 ns/V Tamb Operating free-air temperature range –40 +85 °C DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = –40°C to +85°C UNIT MIN TYP MAX MIN MAX VIK Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VOH High-level output voltageVCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V IOFF Power-off leakage currentVCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA IPU/PD Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC ; VOE = GND ±5.0 ±50 ±50 µA IOZH 3-State output High currentVCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low currentVCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA IO Output current1 VCC = 5.5V; VO = 2.5V –50 –70 –180 –50 –180 mA ICEX Output High leakage currentVCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA ICCH VCC = 5.5V; Outputs High, VI = GND or VCC 120 250 250 µA ICCL Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC 44 60 60 mA ICCZ VCC = 5.5V; Outputs 3-State; VI = GND or VCC 120 250 250 µA ΔICC Additional supply current per input pin2 VCC = 5.5V; one input at 3.4V , other inputs at VCC or GND 0.5 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V/n636861723332000000000000± 10% a transition time of up to 100µsec is permitted.

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 5 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MAX MIN MAX tPLH tPHL Propagation delay nDx to nQx 2 1.3 1.3 2.8 2.9 4.1 4.1 1.3 1.3 4.8 4.8 ns tPLH tPHL Propagation delay nE to nQx 1 1.8 2.0 3.5 3.5 4.9 4.9 1.8 2.0 5.7 5.5 ns tPZH tPZL Output enable time to High and Low level 1.2 2.1 2.9 3.8 4.1 5.3 1.2 2.1 5.1 6.1 ns tPHZ tPLZ Output disable time from High and Low level 1.4 2.0 3.7 3.6 5.0 4.6 1.4 2.0 5.5 5.1 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MIN ts(H) ts(L) Setup time, High or Low nDx to nE 3 1.0 1.0 0.0 0.3 1.0 1.0 ns th(H) th(L) Hold time, High or Low nDx to nE 3 0.5 0.5 –0.2 0.0 0.5 0.5 ns tw (H) Enable pulse width High 1 2.5 1.0 2.5 ns

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 6 AC WAVEFORMS NOTE: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ VM VM VM VM VM tw (H) tPHL tPLH nE nQx VMnDx VM VM VM VM VM nE ts(H) th(H) ts(L) th(L) nOE VM tPZH tPHZ VOH –0.3V nQx nOE tPZL tPLZ VOL +0.3VnQxVM VM VM VM VM nDx VM tPLH tPHL nQx VM VM VM Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width W aveform 2. Propagation Delay for Data to Outputs Waveform 3. Data Setup and Hold Times Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 7 TEST CIRCUIT AND WAVEFORM PULSE GENERATOR R T VIN D.U.T VOUT C L R L VCC R L 7.0V Test Circuit for 3-State Outputs VM VM tW AMP (V) NEGATIVE PULSE 10% 10% 90% 90% VM VM tW AMP (V) POSITIVE PULSE 90% 90% 10% 10% tTHL (tF) tTLH (tR ) t THL (tF) tTLH (tR ) VM = 1.5V Input Pulse Definition DEFINITIONS R L = Load resistor; see AC CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude Rep. Rate t W tR tF MB 3.0V 1MHz 500ns 2.5ns 2.5ns SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 8 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nDx to nQx tPLH vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nDx to nQx MAX 4.5VCC 5.5VCC MIN ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns Adjustment of tPLH for Load Capacitance and # of Outputs Switching nDx to nQx pF 16 switching 8 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPHL vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nDx to nQx MAX 4.5VCC 5.5VCC MIN pF 16 switching 8 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPLH vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nE to nQx MAX 4.5VCC 5.5VCC MIN Adjustment of tPLH for Load Capacitance and # of Outputs Switching nE to nQx pF 16 switching 8 switching 1 switching

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 9 tPHL vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nE to nQx MAX 4.5VCC 5.5VCC MIN ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns Adjustment of tPHL for Load Capacitance and # of Outputs Switching nE to nQx pF 16 switching 8 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPZH vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx pF 16 switching 8 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPZL vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx pF 16 switching 8 switching 1 switching

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 10 tPHZ vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOE to nQx pF 16 switching 8 switching 1 switching ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tPLZ vs Temperature (Tamb ) C L = 50pF, 1 Output Switching nOE to nQx MAX 4.5VCC 5.5VCC MIN Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx pF 16 switching 8 switching 1 switching ns Offset in ns tTLH vs Temperature (Tamb ) C L = 50pF, 1 Output Switching 4.5VCC 5.5VCC Adjustment of tTLH for Load Capacitance and # of Outputs Switching pF 16 switching 8 switching 1 switching –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200

Philips Semiconductors Advanced BiCMOS Products Product specification MB2373Dual octal transparent latch (3-State) August 23, 1993 11 ns –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 Offset in ns tTHL vs Temperature (Tamb ) C L = 50pF, 1 Output Switching 4.5VCC 5.5VCC Adjustment of tTHL for Load Capacitance and # of Outputs Switching pF 16 switching 8 switching 1 switching Volts 0 50 100 150 200 Volts VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V pF 125°C 25°C –55°C VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V pF 125°C 25°C –55°C 125°C 25°C –55°C –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 50 100 150 200 125°C 25°C –55°C