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FUJLTSU 4-BIT MICROCOMPUTER MB88210 wa an — 'TM339-A872: February 1987 CMOS SINGLE-CHIP 4-—BIT MICROCOMPUTER WITH A/D CONVERTER The Fujitsu MB88210 series CMOS single-chip 4-bit MB88211-P microcomputer family is an economical low-end ver- sion of the conventional MB8850 series, as well as the MB88200 series. It is designed based on the MB88200 series architecture (that is a reduced ar- chitecture from the MB8850 series), and contains an A/D converter. The currently available member of the MB88210 series is the MB88211 only. Its on-chip resources are almost same as the MB88202: The MB88211 con- tains a 1K x 8-bit program memory (mask ROM), 32 x 4-bit data memory (static RAM), 10 I/O lines (ex- cluding analog input channel), 8-bit A/D converter, and a clock generator. 20-PIN PLASTIC DIP The MB88211 instruction set is a subset of the (DIP-20P-402) MB8850 series, and is a super set of the MB88200 2 | series. Its instruction execution time is 3.0us min. using a 4MHz clock (with a prescaler), as well as the MB8850/200 series. The device is fabricated by the silicon-gate CMOS process, and packaged in a 20-pin plastic DIP (suf- fix -P). It operates with a single +5V power supply and a 4MHz clock with a prescaler over the tempera— ture range of 0°C to 70°C. CMOS technology allows the device to operate with low power dissipation (1mA typ. at Vec=5V and fc= MHz). For user's development of the MB88210 series based system, Fujitsu provides the MB88200 cross- assemblers which run on the CP/M-86 AND PC-DOS machines (cross-assembler also run on the Intellec series III MDS). the MB2115 series evaluation board system. These development tools enable users to minimizes their development time and cost. This device contains circuitry to protect the inputs against: damage due to high static voltages or elec- tric fields. However, it is advised that normal precautions be taken to avoid application of any voltage: higher than maximus reted voltages to this hig impedance circuit. 2-201

888210 SERIES FUJITSU

FEATURES

CMOS Single-chip 4-bit Microcomputer * Program Memory: 1K x 8 bit mask ROM * Data Memory: 32 x 4 bit static RAM + 10 1/0 Lines: o R-Port: Two 4-bit and one 2-bit parallel, or 10 individual input/output ports + Three Selectable Output Port Types for R-Port with Mask Option: © Standard pull-up © Standard open-drain © Middle-current open-drain * 8-bit Successive Approximation A/D Converter with One Analog Input * On-chip Clock Generator: o Crystal/ceramic resonator or external clock drive * On-chip Divide-by-two Clock Prescaler for Expanding Clock Range + Nesting Level: 4 levels + Instruction Set: Super set of MB88200 series o Number of instructions : 39 o Instruction length/cycle: 1 byte/1 cycle or 2 byte/2 cycle © Execution time : 3.0us min, using 4MHz clock with prescaler * On-chip Power-on Reset Circuit + Low-voltage Reset Function with Mask Option * Output Port Level During Reset with Mask Option: o High level o Low level (RO-R3, RS-R8, R10) + Low Power Dissipation: lmA typ. at Vec=5.0V and fc=1MHz * Single +5V Power Supply: 4.5V to 5.5V + Operating Temperature Range: T4=0°C to +70°C * Silicon-gate CMOS Process * Package Type: 20-pin plastic DIP (Suffix: -P) * Powerful Development Aupport: o CP/M-86, PC-DOS, or Intellec series III MDS cross-assembler (SMO7420-A012/SMXXXXXX-A010/SM05220-A010) © CP/M-86 or PC-DOS host emulator software for monitoring evaluation board and symbolic debugging (SM07420-G022/SMXXXXX-G020) o MB2115 series evaluating boards(MB2115-01, -02, -04, and -39) for software debugging/hardware emulation 2-202

Fig. 1: PIN ASSIGNMENT MB88211-P (Top View) R7 CT] 1 20 [7] Voce re[] 2 19 |) RESET ro} 3 18 [7] TEST AVcc/AVR+ [] 4 17 [7] vss AVgs/AVR- L] 5 16 [_] R5 an(] 6 15 [J R4 re [| 7 14 [J R3 xT] 8 13 [7] rz 2 | ex] 9 12) R1 Vss (] 10 11 [J Ro 2-203

‘¥MB88210 SERIES FUJITSU in Fig. 2: LOGIC SYMBOL co Voc; Voc | 4 EX AYR. R3 -RO Clock 4 x MB88211 R7 -R4 1/o

2 Ports

pevice RESET RO, RB Control TEST AN AY; we Yss a Fig. 3: BLOCK DIAGRAM +> RO Inst- Boi [| RL Decode Io J cose (1024 x 8) HLS | ne

3 Saks

¥B88210 SERIES FUJITSU IANA PIN DESCRIPTION Fig. 1 and Table 1 show the pin assignment and pin description of the MB88210 series. Table 1: PIN DESCRIPTION « Power Supply [ve | * To] +5V DC power supply pin for the internal logic section, [vs | i> [| Ground pin for the internal logic section. AVcc/AVR+ 4 [=] +5V DC power supply pin for the internal A/D converter, AVss/AVR- 5 [| Ground pin for the internal A/D converter. « Clock Oscillator Input: Input to the inverting amplifier that] forms the on-chip oscillator. An crystal/ceramic reso- nator is connected between the EX and X pins. When an external oscillator is used, the EX pin receives the external oscillator signal. This pin is a non-hysteresis input. Oscillator Output: Output of the inverting amplifier that forms the on-chip oscillator, and input to the internal clock generator. An crystal/ceramic resonator is connected between the EX and X pins. When an exter- nal oscillator is used, the X pin should be left open. * Device Control RESET 19 [1/0] Reset: This pin functions as an external reset input o1 power-on/low-voltage reset output. External reset input: A reset input to the internal reset circuit. A low level on the RESET pin forcedly stops the MCU's operations, and initializes its int- ernal state. After the RESET pin returns high, the MCU restarts execution of program from address #0. The RESET pulse must be low for at least two instruction cycles (12 clock periodes: apploximately 6us using a 2MHz crystal without a prescaler) while the oscillator is stably running after power on. An external capacito: (and an internal pull-up resistor) or RC-network, whose time constant should be greater than the reset time required (12 clock periods), composes the external reset circuit. This pin is a hysteresis input with an internal pull- up resistor. 2-205

Table 1: PIN DESCRIPTION (Continued) * Device Control (Continued RESET 1/0 | Power-on/low-voltage reset output: A reset output from the on-chip reset control circuit. Normally this output] is high during the active operation, except power-on/ low-voltage reset. 1) Power-on reset output: The rising of the VCC voltage after power on outputs a negative pulse to the RESET] pin. With an external RC-network at the RESET pin, whose time constant should be greater than the reset time reuired (the oscillator stabilization time, plus 12 clock periods), the power-on reset circuit is composed. 2) Low-voltage reset output: The RESET pin outputs a low level when the VCC voltage lowers below a threshold voltage during the active operating mode, and returns high when the VCC voltage recovers abow the threshold voltage. With an external RC-network at the RESET pin, whose time constant should be greater than the reset time required (the oscillato: stabilization time, plus 12 clock periods), the lo’ voltage reset circuit is provided. (The low-voltage reset function is mask optional.) TEST 18 1 |Test: A high level on the TEST pin forces the MCU into the test mode (which is used for the shipping test at Fujitsu) when the RESET pin is low. This pin is non-hysteresis input, and should externally be pulled down directly to the Vgg pin in the normal operation because it has no internal pull-down resis- tor. « 1/0 Port R3 -RO, | 14-11 [1/0|R-Port: This port functions as two 4-bit and one 2-bit R7 -R4, | 15,16,7,1 parallel input (non-latched)/output (latched) ports, o: R1I-R8 | 3, 2 10 individual input (non-latched)/output (latched) lines, depending on instructions. Parallel 1/0: Each 4-bit/2-bit port is named R-Port #0 (R3-R0), R-Port #1 (R7-R4), and R-Port #2 (R9-R8), and is indirectly addressed by the Y-register (Port #). 4- bit/2-bit data in the accumulator is output to an add essed port of R-Ports #0 to #2 by OUT instruction. 4- bit/2-bit data the addressed port is input into the accumulator by IN instruction. (Before IN instruction, the port to be addressed must be set up to "1" (input mode). ) 2-206

Table 1: PIN DESCRIPTION (Continued) Syabot [Pin wo. [toed Wao & Function « 1/0 Port(Continued R3 -RO, 14-11 | 1/0] Individual I/0: Each line from R9 to RO is indirectly R7 -R4, | 15,16,7,1 addressed by the Y-register (Bit #). An addressed line R11-R8 3,2 is individually set/reset by SETR/RSTR instruction, and is individually testable using TSTR instruction. (Be- fore TSTR instruction, the line to be addressed must be set up to "1" (input mode).) R7, R8, and R9 have hysteresis inputs, while other lines have non-hysteresis inputs. For R-Port pins, one of the standard pull-up, standard open-drain, and middle-current open-drain output can be selected using mask option. The R-Port is set high (standard pull-up)/high-Z (standard or middle current drain), or low (except for RS and R9), depending on mask option. For details, see Table 4 in page 13. * R10 and R11 have no external pins, but internally their I/O lines are still alive, and are connected to the internal A/D converter control circuit. They are used to control/monitor the A/D converter opera- tion by software (SETR/RSTR and TSTR instructions). R10 and R11 are set high by reset. nalog Port: A dedicated analog input to the on-chip A/D converter. Analog signal on the AN pin is sampled and held at the falling edge of the first $1 signal after initiating the A/D converter. 2-207

¥B88210 SERIES FUJITSU DIFFERENCES BETWEEN MB88200 SERIES AND MB88210 SERIES Table 2: DIFFERENCES BETWEEN MBS8200 SERIES AND MB88210 SERIES lteea ee | §B88200 Series ¥B88210 Series . ROM Size > IK x 6 bit: MB88202 ~ ik x 6 bit + 512 x 8 bit: MB88201 RAH Size 732 x & bit: MB86202 + 16 x 4 bit: MB88201 Register > Total 3; AC, X, ¥: MB86202 |~ Total 3: AC, x, ¥ + Total 2: AC, Y : MB88201

170 Port ~ 12-10 Lines (R-Port) > 10 lines (R-Port)

(Depending on oscillator and standby function options Taput Port > Non-hysteresis input ~ Non-hysteresis input: R6-RO Type (R-Port) + Hysteresis input : R9-R7 Output Port 7 Standard open-drain output |~ Standard open-drain output Type (R-Port) + Standard pull-up output + Standard pull-up output + Middle-current open-drain | - Middle-current open-drain output] output (Planned) (task option) + 12V-Interface open-drain output (Mask option! Stack Depth | ~ 4 levels: MB88202 7% levels (Nesting Level)] + 2 levels: MB88201 37D Converter _~« ~ Yes (6 bits x 1 channel) Oscillator T Grystal/eeramic oscillator | ~ Crystal/ceramic oscillator or Type + RO-network oscillator external clock drive + Capacitor oscillator (Fixed) + External clock drive Mask option Clock ~ Yes > Yes (Fixed) Prescaler + No (Mask option) Standby 7 Yes (Software initiation) Function + No Mask option: Operating + 40°C to +85°C > 0% to F70°C Anbient without low-voltage reset regardless of low-voltage reset Temperature + -10°C to +70°C option with low-voltage reset Number of > 37: MBB8201 Instructions | - 38: MB88202 Package Type | 16-pin plastic standard DIP:| - 20-pin plastic standard DIP: MB88201-P/202-P ¥B88211-P + 16-pin plastic flat pack: MB88201-PF/202-PF 2-208

‘¥MB88210 SERIES FUJITSU i Table 2: DIFFERENCES BETWEEN MB88200 SERIES AND MB88210 SERIES (Continued) waa00 series iaaeai0 series Members + MB88201-P/PF + MB88211-P + MB88202-P/PF A-version are available 2-208

All input-only pins are internally pulled up, and R-Port can have push-pull (standard pull-up) or open-drain (standard and middle-current open-drain) buffer using mask option. Table 3: INPUT/OUTPUT CIRCUITS a + Crystal/Ceramic OSC > Non-hysteresis inverter Ex [ } )> ‘> | + Feedback resistor: Approx.| 2U2 typ. (at Voc=SV) P fj xO + Input-only pin > Hysteresis inverter + Output pull-up resistor RESET (P-ch. Tr.): Approx. 300k2 typ. (Vec=5V) P N i + Input/Output pin - Non-hysteresis inverter + Output port option R6-RO -R1, R2, R4, RS: : + 1. Standard puli-up: ! Le Output pull-up resisto: \\PqH: (P-ch. Tr.): Approx. 10kQ typ. (at VCC=SV) N R6: 1, Standard pull-up: Output pull-up resisto: (P-ch. Tr.): Approx. 1.5kQ typ. (at VCC=5V) *2, Standard/Middle-current open-drain: Without P-ch. pull-up resistor “RO, R3: * Standard/Middle-current| open-drain: Without P-ch. pull-up resistor 2-210

Table 3: INPUT/OUTPUT CIRCUITS(Continued) + Input/Output pin + Hysteresis inverter + Output port option R9-R7 1: Standard pull-up: Fa \\ Outtput pull-up resisto: i ik (P-ch. Tr.): Approx. LP ; 10k2 typ. (at Vog=5V) *2: Standard/Middle-current| N open-drain: Without P-ch. pull-up resistor « Input-only pin + In the normal operation, TEST should externally be Ch-——Ps.—_--p pulled down. | ~ Input-only pin ~ Analog input 2-211

‘MB88210 SERIES FUJITSU ‘SNTVEABH USER MASK OPTIONS The MB88210 series has the following mask options, which must be specified by the customer on the attached data release form when devices are ordered. Table 4: USER MASK OPTIONS Feature No. [plivap | [are teandaraopem-drains Output Port pull-up are standard open-drain. open-drain open-drain Output Port Level During Except R4 and R9: R4 and R9 Reset _** are fixed high. Notes: * Only one of the four options can be selected. Mixed options are not permitted. ‘ee Either "high level" or "low level" is applied to all R-Ports in a lump. Mixed options are not permitted. 2-212

Latch-up Prevention Latch-up may occur in CMOS devices when a voltage higher than Vcg or lower than Vgg is applied to input or output pin, or when a voltage exceeding the absolute maximum ratings is applied between Vgg and Vsg pins. If latch-up occurs, the supply current increases greatly, and the device may be ther— mally destroyed. Therefore, applied voltages should not exceed the maximum ratings. * Treatment of Unused Pins Unused input pins should be externally pulled up or down with resistors because such unused input pins may cause some malfunction if they are left open. * TEST Pin When the TEST pin is forced high while the RESET input is low, the MCU is plac- ed to the test mode. Therefore, when the MCU is in normal operation and the test mode operation is not required, the TEST pin should not be forced high, even by noise, while the RESET input is low. For this purpose, normally the TEST pin should be ext- ernally be pulled down directly to the Vsg pin. RESET a ' t TEST I ' ' + External Capacitance for Crystal Oscillation The external capacitors should be adjusted to individual crystal resonators when precise oscillation frequency is required. + Supply Voltage Malfunction may occur even within the recommended operating supply voltage if the supply voltage changes rapidly. Therefore, the supply voltage should be regulated as well as possible. The following conditions are recommended for the power supply: (1) Voc ripple (peak-to-peak value) at commercial frequency (50Hz to 60Hz): Less than 10% of typical Vgc value. (2) Voc transient change rate (such as at switching of power supply): Less than 0.1V/ms. 2-213

INSTRUCTION SET DESCRIPTION ‘The MB88210 series instruction set includes 39 instructions, 95% of which are single-byte and single-cycle, and 5% two-byte and two-cycle. The HB88210 series instruction set is a subset of the MB8850 series, and a super set of the MB88200 series. It is divided into nine functional groups: + Register-to-register transfer + Register-to-memory transfer * Constant transfer * Arithmetic and logical operations + Bit manipulation + Input/Output * Branch + Flag manipulation * Other Tables 5 and 6 summarize the MB88210 series instruction set. Table 5: INSTRUCTION SET SUMMARY Code Byte, [~_[cesonid ies farPery sr] oyeid —___Overation Register- [CLA [90 [+ |= [+ [1/1 Taceo (included by LT instruction) | to- TAY 06 T/1_| Ye(ac) Register | TYA 14 1/1 | ACe(Y) Transfer Register- [Lf op TT Tat [aCe fc yyp Teanster [aw p_|secsra ied |< [at [Gy’simcor0)]) bee to 9 Transfer_| X¥D_D_ | 54-574 t#2 1/1_| (x) #{M(0,D)}; D=4 to 7 Constant |LI im 90-9 1/1 | AC+inm; imm=0 to 15 Transfer |LXI imm 58-59 1/1 |X3 to X1+0, XOeimm; imm=0 or 1 LYI__imm 80-8F if. Yeimm ; imm=0 to 15 reat [ar nl ed (Cee Lene & Logical mol 70-7F4 40] 1/1 | AC+(AC)+imm; imm=0 to 15 CI imm BO-B 1/1 | imm-(AC); imm=0 to 15 CYI ima AO-AF? 1/1 | imm-(¥) ; imm=0 to 15 DCA TF ¥C | 1/1 | AC+(AC)+15 (Included by Al instruc pew 19 4] 1/1 | MCX, ¥)+{M(X,¥) }-1 tion) Dey 18 ye Lat | ye(yy-1 ICA 71 yo] 1/1 | AC+(AC)+1 (Included by AI instruc Ich 09 4c] 4/1 | MCX,Y)*{M(X,¥)}41 tion) Icy 08 4c} ayi_| ¥e(y)+1 [NEG [2p ez Pat | ace (ac) +1. [spc fae EE fac [isa [ace f(x, ¥) }-(Ac)=(CFy Bit RBIT bp | 34-37 1/1 | {M(X,¥)}bpeO; bp=0 to 3 Manipule- [err bel s0-a04- |< |: [aa | {wo}umeds opco tos | TBIT bp | 38-384 4] 1/1 | {M(X,¥)}bp-1; bp=0 to 3 Tnput/ 13 1/l_ {ACe(R)Y ; Y=0 to 2 (Port #) Output 12 1/1 | ACe(DH) if R10=H AC+(DL) if R10=L [our [os TT aT yy¥e(ac);_Y=0 to 2 (Port #) | [sem [ao [| | [ifs [ira! veo su Gi § 23 [str [24 TT [ee [isi | (Ryo; Y=o to 11 (Bit #) *3 | 2-214

‘MB88210 SERIES FUJITSU TTA Table 5: INSTRUCTION SET SUMMARY (Continued) | —~[rsesonsd Grex ferfartsr|oyeig eration Branch CALL addr 6000 2/2 |I£ ST=1, Subroutine Call for addr;| 63FF* addr=0 to 1023 ST=0, Not Subroutine Call. TMP addr] CO-FF4 T/_ [If ST=1, Branch to addr; addr=0 to 63 ST=0, Not Branch. JPL addr) 6800- 2/2 | If ST=1, Branch to addr; 6BFF* addr=0 to 1023 ST=0, Not Branch. [Rts [2c TT a/i [Return From Subroutine | wast EES Manipula- 21 1fi_| CFe1 tw lee | [iain [Gps TSTZ ZF 1/1 ZF)-1 [Other [Nop foo [TT + [i/i [No Operation Notes: * Code is variable depending on the operand. *1: ZF is set or reset depending on contents of AC after instruction execution. *2: ZF is set or reset depending on contents of Y after instruction execution. *3: When Y=10 and 11, A/D converter's control/status register bits (ADCO=R10 and ADC1=R11) are addressed. 2-215

+ Is transferred to = Is exchanged with + Arithmetic plus = Arithmetic minus (Overline) Negation ©) Contents of parenthesis + Set to "1" always ' Set to "0" always t Affected (set or reset) by operation results +c Set to "0" due to carry (not carry flag) ¥CF Set to "0" due to carry flag

42 Set to "0" due to zero (not zero flag)

+2F Set to "0" due to zero flag : Not affected Abbreviations Meaning AC Accumulator addr Jump address bp Bit pointer (that is part of the instruction code) c Carry CF Carry flag D Direct data memory address (that is part of the instruction code) DE A/D converter data register high nibble DL A/D converter data register low nibble im Immediate data LSB Least significant bit M(X,¥) Data memory (RAM) location indirectly addressed by data pointer (X- and Y-registers) M(O,D) Data memory (RAM) location directly addressed by "D" bits in the instruction code, in page #0 (X=0) MSB Most significant bit R R-Port (#0: R3-RO, #1: R7-R4, #2: R9 and R8) (R)Y; Yen Q B Port jin specified by Y-register (Y=0 to 2) R-Port bit n specified by Y-register (Y=0 to 11*) * 10 and 11 in Y-register address A/D converter's control/status bits. sT Status flag x X-register (that indicates page # in data memory RAM) Xn The n-th bit of X-register Y Y-register Zz Zero oF Zero flag 2-216

¥MB88210 SERIES FUJITSU VEIN PRODUCT LINEUP AND DEVELOPMENT TOOLS The MB88210 series consists of the MB88211 only. Table 7: MB88200 SERIES PRODUCT LINEUP & DEVELOPMENT TOOLS ee ROM Size 1024 x 8 bits On-chip mask ROM) RAM Size 32 x 4 bits (Directly addressed (0-7) locations: [Register Total 3: AC, X,Y 1/0 Port: -Input-Only Port 0 -Output-Only Port C) -1/0 Port 10 ~Control Port 0 Hysteresis 3_R9-R7 Output Port Type + Standard pull-up + Standard open-drain + Middle-current open-drain Mask option: A/D Converter: ~ Resoluation + B-bit - Channel -_1 channel [Stack Depth Clock Generator: Yes Oscillator Type + Crystal/External Clock Frequency + 1MH2-4MHz [Clock Prescaler (1/2) [Yes (Fixed) 0 CSCS~SY Reset Fuction: -External Reset * Yes -Power-on Reset Function - Yes -Low-volatge Reset + Yes/No Function (Mask option) Output Port Level + High/Low During Reset Mask option) | Standby Function: [No —*Y Instruction Set: Number of Instruction | 39 -Length/Cycle 1/1 or 2/2 Execution Time With Prescaler [Process CMOS OOCC—CSY [Package | 20-pin DIP Development Tools: Hardware MB2115-01 : CRT unit (Common) MB2115-02 : Monitor board with keyboard (Common) MB2115-04 : EPROM writer (Common) MB2115-39 : DUE board Software SM05220-A010: Intellec series III MDS cross-assemble: $M07420-A012: CP/M-86 cross-assembler SMXXXXX-AO10: PC-DOS cross-assembler $M07420-G022: CP/M-86 host emulator SMOXXXX-G020: PC-DOS host emulator 2-218

MB88210 SERIES — FUJITSU TTTHEIER

ELECTRICAL CHARACTERISTICS

© ABSOLUTE MAXIMUM RATINGST Analog Power ‘Bec! Vgs=AVg5 Supply Voltage AVRS Vss-0.3 Vsst7.0| Vv | Should not exceed AVss. VIN Vss=AVss Input Voltage Vsst7.0| V | Should not exceed four 'ss=AVgs Veo (=AVec)+0.3V. Temperature Storage [ tempessture | Pre | ss | [aso [ef | t Permanent device damage may occur if the above ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions 2 as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * RECOMMENDED OPERATING CONDITIONS reo pee Supply A Supply AVRe. AVR vokeeee | [Pe aided ll PP Voltage R6-RO reveo| [eer Le, maar, moar | EX, RESET, R9-R7 Voltage R6-RO Vits | Vss-0-3 0.2" Voc EX, RESET, R9-R7 Operating Ambient T! 70 °c Temperature 2-219

+ AC CHARACTERISTICS CLOCK TIMING (Recommended operating conditions unless otherwise noted.) Pin/ i ore [EST] eoatson Taam er|e | mc Clock Crystal/ceramic With Frequency OSC or external 4 prescaler clock drive: Fig. 4 and 5 Clock Cycle | teye Fig. 4 and 5 Time Tnput Clock | PycH> External clock With Pulse Width | Pycr drive (with X | 100 prescaler open) : Fig. 4 and 5 Input Clock] tor, External clock Rise/Fall tet drive (with X | 5 100 Time open) : Fig. 4 and 5 Fig. 4: CLOCK TIMING - 2 | ==---- 0.7¥¢g EX (With Prescaler) w----- 0.3Vg¢ PYCH PycL tet ter Fig. 5: CLOCK CIRCUIT CONFIGURATIONS (1) Crystal/Ceramic (2) External Clock Oscillation Drive Z a Open 2-221

© A/D CONVERTER CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter | Symbol] Pin Unit | Conditi [ Min. | Typ. [ Max. | afeons foes | ff | pe lef Linearity [iron en | | | [to [asa | Differential Ta=25°C Linearity ¥*3 LSB | AVcc/AVps=Voc=5.0 Error AVgs/AVp-=Vgg=0V Zero Transitio [isisage | Yor | 20 [uo [seo | av | Full-Scale Transition Vest +4910 | +4970 | +5030 | av Voltage Time ‘Analog Port | Tain r_| Input Current ‘Analog Input | VAIN Voltage Range Veo+0-} Supply r BWoc/ ‘Aveq=s-0V, AVgg=0 Current ‘A | AVRe £c=4MHz Notes: #1: Resolution The minimum variation in an analog signal that can be discriminated by the A/D converter. (An analog voltage can be divided into 2"=256 parts.) #2: Linearity Error The difference between the line connecting the device zero transition point "0000 0000" ++ "0000 0001") with the full scale transition point "1111 1111" ++ "1111 1110"), and the actual conversion characteristics. *3: Differential Linearity Error The difference from ideal input voltage required to change the output voltage code by 1LSB. Fig. 7: A/D TRANSFER CHARACTERISTICS ~ “est ~ Yor uss = Digital Output Vyr- (LSB x N + Vor) x 4212 1211 Tinearity = SS [LsB} 1111 1110 , (ILSB X N + Vor), Differential y -y ’ Linearity. = #7" ONT 1 (rsp) Nef 1LSB Error “ [ Linearity Error 0000 0010 ~" 0000 0001] ;; J 0000 0000 gnalog Yor Yr Ynei)T Vest Input 2-222

POWER-ON RESET (BUILT-IN) CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Condi- [rene [oma SE Fao] ted Power Supply ea ee ae Required for operation of Rise Time the power-on reset circuit Power Supply [ tore [Fe 8] ET |] Required for accurate circuit Shout-off Time operation repeatability Fig. 8: POWER-ON RESET TIMING 4.5V Yeo 0.2V 0.2v 0.2V ty tofft Note: Power supply should be raised smoothly. 2 | * LOW-VOLTAGE RESET (MASK OPTION) CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Condi- er a ee Detection Vr | Fig. 9 4.5 | V | Reset is operational Voltage at_less than Vy Supply Voltage | At/AV|Fig. 9 | 0.01 ms/V Rise/Fall Slope Fig. 9: LOW-VOLTAGE RESET TIMING Vy - -- Veo Time delay to restart is deter- Normal Operation mined by the time constant of external RC-network with RESET t pin. Low-Voltage Detection 2-223

Pi) ‘MB88210 SERIES FUJITSU esi ii] PACKAGE DIMENSIONS * MB88211-P: 20-PIN PLASTIC DIP (CASE No.: DIP-20P-02} we DOO oso IS MAX. ) 2D Bes Rtory LO (EXECTOR MARK) wo/ GLI Li Wht y Soe mae mae ; YVIOORUOOUREOUO 17214360MAX, ae na Circuit diagrams utilizing Fujitsu products are included as a means of illus- trating typical semiconductor applicatinos; consequently, complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to purchaser of the semiconductor devices described herein any license under the patent rights of Fujitsu Limited or others. Fujitsu Limited reserves the right to change device specifications. 2-224

Product Information

MB2115-01 specifications and overview.

Summary

CMOS SINGLE-CHIP 4-BIT MICROCOMPUTER WITH A/D CONVERTER

Description

CMOS SINGLE-CHIP 4-BIT MICROCOMPUTER WITH A/D CONVERTER

Source title MB2115-01 Datasheet(PDF) - fujitsu semiconductor

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