MB1519 FUJITSU | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 16

Technical content

DS04–21314–1E DATA SHEET Copyright 1994 by FUJITSU LIMIED MB1519 ASSP DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER Rating Symbol Value Unit NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN ASSIGNMENT This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. TOP ABSOLUTE MAXIMUM RATINGS (see NOTE) DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH 600MHz PRESCALER The Fujitsu MB1519 is a 600MHz dual serial input PLL (Phase Locked) frequency synthesizer designed for cellular telephone and cordless telephone applications. The MB1519 has two PLL circuits on a single chip: one for transmit and the other for reception. Separate power supply pins are provided for the transmit and reception PLL circuits. Transmit PLL contains a low sensitivity charge pump for ease of modulation and reception PLL contains a high sensitivity charge pump for faster lock up time. 600 MHz dual modulus prescalers are on chip and enables a pulse swallow function. It operates supply voltage of 3.0V typ. and dissipates 11mA typ. of current realized through the use of Fujitsu’s unique U-ESBIC Bi-CMOS technology.

  • High operating frequency: fin = 600MHz
  • Low power supply voltage: VCC = 2.7 to 5.5V
  • Low power supply current: ICC = 11mA typ, @3V.
  • Wide operating temperature: TA = –40 to 85°C
  • Two charge pumps Low sensitivity charge pump for transmit High sensitivity charge pump for reception
  • Plastic 20-pin dual in line package (Suffix: -P) Plastic 20-pin flat package (Suffix: -PF) PLASTIC PACKAGE DIP-20P-M02 GND VCC V PLASTIC PACKAGE FPT-20P-M01 Power Supply Voltage OSC OUT fin1 OSC IN VCC1 fr Data LE fin2 VCC2 fp –0.5 to 7.0 VP VCC to 10.0 VOUTOutput Voltage –0.5 to V CC +0.5 IOUT mAOutput Current ±10 TSTG °CStorage Temperature –55 to +125 LD 1 VP1 D O1 BS 1 LD 2 VP2 D O2 BS 2 VIEW Data V

(512, 1024) 4 2 3 15 14 12 11 17 18 Charge Pump Phase Detector Binary 11-bit Program- mable Counter Binary 7-bit Swallow Counter 20-bit latch Latch Selec- tor 23-bit shift register Schmitt Circuit Schmitt Circuit Schmitt Circuit Crystal Oscillator Prescaler CNT RECEP- TION SECTION TRANSMIT SECTION

  • 20-bit latch
  • Programmable divider consisting of: Binary 7-bit swallow counter (Divide ratio: 0 to 127) Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
  • Phase detector with phase polarity change function
  • 600MHz dual modulus prescaler (Divide ratio: 64/65)
  • Charge pump COMMON BLOCK
  • 23-bit shift register
  • Programmable divider consisting of: Reference counter (Divide ratio: 512, 1024) (Divide frequency = 25kHz, 12.5kHz (Crystal oscillator frequency = 12.8MHz)
  • Crystal oscillator
  • fp monitor output selector
  • Latch selector
  • Schmitt circuits
  • Analog switches BLOCK DESCRIPTIONS

Pin No. Pin Name PIN DESCRIPTIONS GND Descriptions Ground. I/O 2I OSC IN OSC- OUT Oscillator input pin. Oscillator output pin. A crystal is connected between OSCIN pin and OSCOUT pin. 4I fin1 Prescaler input pin of transmit section. The connection with VCO should be AC connection. O 5– VCC1 Power supply voltage input pin of transmit section. When power is OFF, latched data of transmit section is cancelled. 6O fr Monitor pin for programmable reference divider output. 7O LD1 Lock detect signal output pin of transmit section. Condition LD pin output level Lock H Unlock L 8– VP1 Power supply voltage input for charge pump and analog switch of transmit section. 9O D O1 Charge pump output pin of transmit section. Phase characteristics of the phase detector can be reversed depending upon FC-bit setting. 10 O BS1 Analog switch output pin of transmit section. Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is con- nected to this pin. 11 O BS2 Analog switch output pin of reception section. Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is con- nected to this pin. 12 O D O2 Charge pump output pin of reception section. Phase characteristics of the phase detector can be reversed depending upon FC-bit setting. 13 – VP2 Power supply voltage input for charge pump and analog switch of reception section. 14 O LD2 Lock detect signal output pin of reception section. Condition LD pin output level Lock H Unlock L 15 O fp Monitor pin for programmable divider output. This pin outputs divided frequency of transmit section or reception section depending upon FP bit set- ting. FP bit Output H Transmit section (fp1) L Reception section (fp2)

Pin No. Pin Name PIN DESCRIPTIONS (Continued) Descriptions I/O 16 – VCC2 Power supply voltage input pin for reception section, programmable reference divider, shift register, and crystal oscillator. When power is OFF, latched data of reception section and reference counter is cancelled. 19 I Data Serial data input pin of 23-bit shift register. This pin involves a schmitt trigger circuit. The stored data in the shift register is transferred to either transmit section or reception section depending upon a control data. Control bit data The destination of data H Latch of transmit section L Latch of reception section 17 I fin2 Prescaler input pin of reception section. The connection with VCO should be AC conneciton. 18 I LE Load enable input pin. This pin involves a schmitt trigger circuit. When this pin is high, the data stored in the shift register is transferred into the latch depending on a control data. At this moment, charge pump output signal is output from BS pin since internal analog swith becomes ON. 20 I Clock Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit. On rising edge of the clock shifts one bit of data into the shift register. FUNCTIONAL DESCRIPTIONS The divide ratio can be calculated using the following equation: fVCO = {(M x N) + A} x fOSC ÷ R (A < N) fVCO :Output frequency of external voltage controlled ocillator (VCO) M: Preset divide ratio of dual modulus prescaler (64) N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047) A: Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127) f OSC :Reference oscillator frequency R: Preset divide ratio of reference counter (512 or 1024)

Serial data is input using three pins, Data pin, Clock pin, and LE pin. Programmable divider of transmit section and programmable divider of recep- tion section are controlled individually. Serial data of binary data is input into Data pin. On rising edge of clock shifts one bit of serial data into the shift register. When load enable signal is high, the data stored in the shift register is transferred to either the latch of transmit section or the latch of reception section depending upon the control bit data setting. C N T SHIFT REGISTER CONFIGURATION SERIAL DATA INPUT TIMING N11 = MSB N10 N1 C: Control bitData Clock LE t2 t4

  • t1 , t2, t3, t4, t5 ≥ 1µs FUNCTIONAL DESCRIPTIONS Control data Destination of serial data H Latch of transmit section L Latch of reception section R E F F P D M Y F C A A A A A A A N N N N N N N N N N N Control bit LSB MSB N1 to N11 : Divide ratio of the programmable counter setting bit (16 to 2047) A1 to A7 : Divide ratio of the swallow counter setting bit (0 to 127) FC : Phase control bit of the phase detector DMY : Dummy bit (sets to low) FP : Output of the programmable divider control bit (fp1 or fp2) REF : Divide ratio of the reference counter setting bit (512 to 1024) CNT : Control bit On rising edge of the clock shifts one bit of the data into the shift register. A7 REF = LSB Data Flow

BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING DMY : DUMMY BIT INPUT This bit is set to low in operation. REF : DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETTING BIT H = 512 (fr = 25.0 kHz) L = 1024 (fr = 12.5 kHz) FP : OUTPUT OF THE PROGRAMMABLE DIVIDER SETTING BIT H = fp pin (15 pin) outputs programmable divider output frequency (fp1) of transmit section. L = fp pin (15 pin) outputs programmable divider output frequency (fp2) of reception section. FC : PHASE CONTROL BIT OF THE PHASE DETECTOR Output of charge pump is selected by FC pin. Divide Ratio (N) N 2047 N N N N N N N N N N Note:Divide ratio less than 16 is prohibited. Divide ratio (N) range = 16 to 2047 Divide Ratio (A) A 127 BINARY 7-BIT SWALLOW COUNTER DATA SETTING Note:Divide ratio (A) range = 0 to 127 A A A A A A FC = H FC = L fr > fp H L fr = fp Z Z fr < fp L H VCO Polarity (1) (2) Note:Z = High-impedance Depending upon the VCO poratity, FC bit should be set. VCO Input Voltage VCO Output Frequency (1) (2)

PHASE DETECTOR OUTPUT WAVEFORM Note: • Phase difference detection range = –2π to +2π

  • LD output becomes low when phase difference is tW or more. LD output becomes high when phase difference less than tW is reperated 3 times or more. (e. g. tW = 625 to 1250 ns, foscin = 12.8 MHz)
  • Spike apperance depends on the charge pump characteristics. The spike is output to diminish the dead band.
  • When fr > fp or fr < fp, spike might not generate depending up the VCO characteristics. fr fp tW LD (FC bit = High) D O Z L (FC bit = Low) D O Z H

3.0 Value VInput Voltage V IN 2.7 5.5 –40 +85Operating Temperature T A GND V CC ON/OFF of the analog switch is controlled by the combination of the control data and LE signal. When the analog switch is ON, BS1, BS2 pin output the charge pump output (D01, D02). When analog switch is OFF, BS pin is set to high impedance. Control data = H Divide ratio of transmit section is set Analog switch of transmit section Control data = L Divide ratio of reception section is set LE = H LE = L LE = H LE = L ON OFF OFF OFF Analog switch of reception section OFF OFF ON OFF When a analog switch is inserted between LP1 and LP2, faster lock up time is achieved to reduce LPF time constant during PLL channel switching. CHARGE PUMP LPF-1 ANALOG SW LPF-2 VCO (CONTROL SIGNALE) BISW D O RECOMMENDED OPERATING CONDITIONS V– 8.0VP VCC Note VCC1 = VCC2

  • This device should be transported and stored in anti-static containers.
  • This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover work- benches with grounded conductive mats.
  • Always turn the power supply off before inserting or removing the device from its socket.
  • Protect leads with a conductive sheet when handling or transporting PC boards with devices. HANDLING PRECAUTIONS

ELECTRICAL CHARACTERISTICS

Power Supply Current∗ Condition Operating Frequency∗∗ finfin MHz OSC IN Notes: ∗: fin = 600MHz, OSCIN = 12.8MHz, VCC1 = VCC2 = 3.0V. The remaining input pins are grounded and output pins are open. ∗∗: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected. Reception section is active. 5.5 8.0 – 11.0 16.0ICC2 Transmit/reception section are active. 10 – 600 fOSC – 12.8 20 –8 – 0 –4 – 4 0.5 – – Input Sensitivity fin dBm OSC IN VCC = 2.7 to 4.0V, 50Ω VOSC Vfin VCC = 4.0 to 5.5V, 50Ω VPP Low-level Input Voltage Except fin and OSC IN V High–level Input Voltage V IH VCC x0.7+0.4 ––VIL VCC x0.3–0.4 1.0 – –1.0–Low-level Input Current Data, Clock LE µA High–level Input Current I IH IIL ––OSC IN IOSCInput Current ±50 –Low-level Output Voltage Except DO and OSC OUT V High–level Output Voltage V OH VOL VCC = 3.0V 2.2 0.4 – 1.1–D O High–impedance Cutoff Current IOFF VP = VCC to 8.0V VOOP = GND to 8.0V µA –1.0 –1.0 Except DO and OSC OUT mAOutput Current IOH IOL –– 1– –1 2– D O1 VP = 6V VCC = 3V IOH IOL –– 3– –6– D VP = 6V VCC = 3V IOH IOL ––R ONAnalog Switch ON Resistance 25 Ω

50Ω TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST) 1235 48 VCC1 0.1µF VP1 0.1µF 20191816 1713 15 50Ω 1000pF 1000pF P.G P.G 0.1µF VCC2 0.1µF VP2 fp Oscilloscope MB1519 X’tal GND

0.1µF 1000pF Lock Detector Output 10987654321 BS 1D 01VP1LD 1frVCC1fin1OSC OUTOSC INGND 0.1µF Lock Detector 0.1µF LPFVCO Output 1000pF X’tal C1 C2 Note: VP1, VP2 : 8 V max. C1, C2 : depends on the crystal oscillator. Clock, Data, LE : involve the schmitt circuit. When input pins are open, please insert the pull down/up resistor individually to prevent the oscillation. X’tal : 12.8MHz From Controller 0.1µF

inches (millimeters) 20-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-20P-M02)  1991 FUJITSU LIMITED D20003S-3C .970+.008 –.012(24.64 )+0.20 –0.30 .034+.012 (0.86 )+0.30 .244±.010 INDEX-1 .100(2.54) TYP .050(1.27) MAX .018±.003 .172(4.36)MAX .118(3.00)MIN .010±.002 (0.25±0.05) .300(7.62) TYP 15°MAX .050+.012 (1.27 )+0.30 INDEX-2 (6.20±0.25) PACKAGE DIMENSIONS

inches (millimeters) 20-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-20P-M01)  1991 FUJITSU LIMITED F20003S-5C .004(0.10) Ø.005(0.13) M .050(1.27) TYP “A” .018±.004 (0.45±0.10) .089(2.25) MAX (MOUNTING HEIGHT) .002(0.05) MIN (STAND OFF HEIGHT) +.016 –.008 +0.40 –0.20.268 (6.80 ) .020±.008 (0.50±0.20) +.002 –.001 +0.05 –0.02.006 (0.15 ) Details of “A” part .008(0.20) .020(0.50) .007(0.18) MAX .027(0.68) MAX .500 INDEX .450(11.43) REF (12.70 )+0.25 –0.20 +.010 –.008 .209±.012 (5.30±0.30) .307±.016 (7.80±0.40) PACKAGE DIMENSIONS (Continued)

All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The Information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.

For further information please contact: Japan FUJITSU LIMITED Electronic Devices International Operations Department KAWASAKI PLANT, 1015 Kamikodanaka, Nakahara–ku, Kawasaki–shi, Kanagawa 211, Japan Tel: (044) 754–3753 FAX: (044) 754–3332 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA Tel: (408) 922–9000 FAX: (408) 432–9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10,

63303 Dreieich-Buchschlag,

Tel: (06103) 690-0 FAX: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LIMITED No.51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 0718 Tel: 336-1600 FAX: 336-1609  FUJITSU LIMITED 1994 Printed in Japan DS04–21314–1E