MB1507 FUJITSU | Alldatasheet

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Edition 4.0a DATA SHEET Copyright 1995 FUJITSU LIMITED and FUJITJU MICROELECTRONICS, INC. ABSOLUTE MAXIMUM RATINGS (see NOTE) Rating Power Supply Voltage Symbol Value Unit NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN ASSIGNMENT This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. How- ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated volt- ages to this high impedance circuit. SERIAL INPUT PLL FREQUENCY SYNTHESIZER MB1507 Output Voltage Output Current VCC IOUT mA PLASTIC PACKAGE FPT-16P-M06 VP +10 V V TSTG °CStorage Temperature –55 to +125 Open-drain Voltage VOOP VVOUT V –0.5 to +7.0 VCC to 10.0 –0.5 to VCC +0.5 –0.5 to 8.0 16OSC IN OSC OUT VP VCC D O GND LD fIN ØR ØP f OUT BISW FC LE Data Clock TOP VIEW SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH 2.0GH Z PRESCALER The Fujitsu MB1507 is a single chip serial input PLL frequency synthesizer designed for Broadcast Satelite tuner and cellular telephone applications. It contains a 2.0 GH Z dual modulus prescaler which enables pulse swallow function, and an analog switch to speed up lock up time. It operates supply voltage of 5.0V typ. and dissipates 18mA typ. of current realized through the use of Fujitsu’s unique U-ESBIC Bi-CMOS technology.

  • High operating frequency: fIN MAX =2.0GHZ (PIN MIN =–4dBm)
  • Pulse swallow function: 128/129 or 256/257
  • Low supply current: ICC =18mA typ.
  • Serial input 19-bit programmable divider consisting of: Binary 8-bit swallow counter: 0 to 255 Binary 11-bit programmable counter: 16 to 2047
  • Serial input 15-bit programmable reference divider consisting of: Binary 14-bit programmable reference counter: 8 to 16383 1-bit switch counter (SW) Sets divide ratio of prescaler
  • On-chip analog switch achieves fast lock up time
  • 2types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump
  • Wide operating temperature: –40°C to +85°C
  • 16-pin Plastic Flat Package (Suffix: –PF)

D O LE R P fOUT BISW FC LE Data Clock 16-BIT SHIFT REGISTER 16-BIT SHIFT REGISTER 15-BIT LATCH 15-BIT LATCH PROGRAMMABLE REFERENCE DIVIDER S W BINARY 14-BIT REFERENCE COUNTER 20-BIT SHIFT REGISTER 20-BIT SHIFT REGISTER 19-BIT LATCH 8-BIT LATCH 11-BIT LATCH PROGRAMMABLE DIVIDERPRESCALER CONTROL CIRCUIT fp BINARY 8-BIT SWALLOW COUNTER BINARY 11-BIT PROGRAMMABLE COUNTER fr CRYSTAL OSCILLATOR fIN LD OSC IN OSC OUT VP VCC D O GND 11

Pin No. Pin Name Description I/O OSC IN I VP Oscillator input. Oscillator output. A crystal is placed between OSC IN and OSCOUT . – Power supply input for charge pump and analog switch. 4 VCC – Power supply voltage input. OSC OUT O D O5 Charge pump output. The characteristics of charge pump is reversed depending upon FC input. –6 GND Ground. OLD Phase comparator output. Normally the output level is high level. While the phase difference of fr and fp exists, the output be- comes low level. fIN Prescaler input. The connection with VCO should be AC connection. Clock9 Clock input for 20-bit shift register and 16-bit shift register. On rising edge of the clock shifts one bit of data into the shift registers. Binary serial data input. The last bit of the data is a control bit which specified destination of shift registers. When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When this bit is low level and LE is high level, the data is transferred to 19-bit latch.

10 Data I

Load enable input (with pull up resistor). When LE is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output to be connected to BISW pin because internal analog switch becomes ON state. IFC Phase select input of phase comparator (with pull up resistor). When FC is low level, the characteristics of charge pump, phase comparator is reversed. FC pin input signal controls fout pin (test pin) output level, fr or fp. O13 Analog switch output. Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this pin outputs internal charge pump output. BISW fOUT O Monitor pin of phase comparator input. fout pin outputs programmable reference divider output (fr) or programmable divider output (fp) de- pending upon FC pin input level. FC=H: It is the same as f r output level. FC=L: It is the same as fp output level. O Outputs for external charge pump. The characteristics are reversed according to FC input. ∅ P pin is N-channel open drain output. O I I OØP ØR

Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15–bit programmable reference divider and 19–bit programmable divider, respectively. Binary serial data is input to Data pin. On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit. Control data ”H” data is transferred into 15–bit latch. Control data ”L” data is transferred into 19–bit latch. THE DIVIDE RATIO SETTING fVCO =[(MxN)+A]xfOSC ÷R fVCO : Output frequency of external voltage controlled oscillator (VCO) M: Preset modulus of external dual modulus prescaler (128 or 256) N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047) A: Preset divide ratio of binary 8-bit swallow counter (0≤A≤255, A<N) fOSC : Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383) PROGRAMMABLE REFERENCE DIVIDER Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below. 1234 S S S S S S S 11 12 SS S S W CS S S Control bit LSB Divide ratio of programmable reference counter setting bit Divide ratio of prescaler setting bit MSB S 14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO 14 13 12 11 S S S S S S S SS S SS S SDivide Ratio R 16383 00000000001000 10010000000000 11111111111111 NOTES: Divide ratio less than 8 is prohibited. Divide ratio: 8 to 16383 SW: This bit selects divide ratio of prescaler. SW=H : 128/129 SW=L : 256/257 S1 to S14: These bits select divide ratio of programmable reference divider. C: Control bit (sets as high level). Data is input from MSB side.

Programmable divider consists of 20-bit shift register, 19-bit latch, 8-bit swallow counter and 11-bit programmable counter. Serial 20-bit data format is shown below. 1234 S S S S S S S 11 12 SS S SCS S S Control bit LSB MSB S S S S Divide ratio of programmable counter setting bit S Divide ratio of swallow counter setting bit 8-BIT SWALLOW COUNTER DIVIDE RATIO S S S S SS S Divide Ratio A 255 0000000 1000000 1111111 NOTE: Divide ratio: 0 to 255 S 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO 19 18 17 16 S S S S S S S SS S SDivide Ratio N 2047 00000010000 10001000000 11111111111 NOTES: Divide ratio less than 16 is prohibited. Divide ratio: 16 to 2047 S1 to S8: Swallow counter divide ratio setting bit. (0 to 255) S9 to S19: Programmable counter divide ratio setting bit. (16 to 2047) C: Control bit (sets to low level). Data is input from MSB side.

NOTES: Parenthesis data is used for setting divide ratio of programmable reference divider. On rising edge of clock shifts one bit of data into the shift register. t1, t2, t3, t4, t5≥1µs SERIAL DATA INPUT TIMING Data Clock LE S19=MSB *(SW) (S14) S18 S11 (S7) (S6) S10 (S1) S1=LSB (C: CONTROL BIT) C: CONTROL BIT t1 t2 t4 PHASE CHARACTERISTICS fr>fp FC=H or open FC=L D O ØR ØP f out D O fout HLL( f r)L H Z ( f p) Note: Z=(High impedance) VCO POLARITY VCO INPUT VOLTAGE FC pin is provided to change phase polarity of phase comparator. Characteris- tics of internal charge pump output level (DO ), phase comparator output level (ØR, ØP) are reversed depending upon FC pin input level. Also, monitor pin (fout) output level of phase comparator is controlled by FC pin input level. Depending upon VCO polarity, FC pin should be set accordingly: When VCO polarity are like , FC should be set High or open circuit; When VCO polarity are like , FC should be set Low. ØR ØP fr=fp ZLZ ZLZ( f p)(fr) fr<fp LHZ ( f r)H LL( f p) VCO OUTPUT FREQUENCY

PHASE DETECTOR OUTPUT WAVEFORM (FC=High) NOTES: Phase difference detection range: –2π to +2π Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band. When fr>fp or fr<fp, spike might not appear depending upon charge pump characteristics. fP LD fr D O H fr>fp fr=fp fr<fp fr<fp fr<fp L Z ANALOG SWITCH ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO ) is connected to BISW pin. When the analog switch is OFF, BI-SW pin is set to high-impedance state. H(Changing the divide ratio of internal prescaler) L(Normal operating mode) LE Analog Switch ON OFF When an analog switch is inserted between LP1 and LP2, faster lock up time is achieved to reduce LPF time constant during PLL channel switching. CHARGE PUMP LPF-1 LPF-2 V CO ANALOG SW (CONTROL SIGNAL LE) BISW D O

RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Typ Max Power Supply Voltage Input Voltage Operating Temperature V CC VI TA 4.5 GND –40 5.0 5.5 VCC V V VP VVCC — 8.0 HANDLING PRECAUTIONS

  • This device should be transported and stored in anti-static containers.
  • This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
  • Always turn the power supply off before inserting or removing the device from its socket.
  • Protect leads with a conductive sheet when handling or transporting PC boards with devices.

ELECTRICAL CHARACTERISTICS

V Low-level Input Current ICC fin Pfin VOSC VIH OSC IN Except fin and OSC IN Data Clock fOSC VIL IIH IIL 18.0 mANote 1 Note 2 Input Sensitivity fin OSC IN Input Current IOSC ILE OSC IN LE, FC µA µA High-level Output Current Low-level Output Current VOH Except DO and OSCOUT VOL VCC =5V High Impedance Cutoff Current IOFF Analog Switch On Resistance IOH IOL R ON mA Output Current NOTE 1 :fin=2.0GHz, fOSC =12MHz X’tal VCC =5V. Inputs are grounded and outputs are open. D O ,Ø P Except DO and OSCOUT VP=VCC to 8V VOOP =GND to 8V 0.5 VCC x0.7 1.0 –1.0 4.4 –60 /C003450 –1.0 1.0 VCC x0.3 2000 MHz MHz dBm VPP µA µA V V V µA mA NOTE 2 : AC coupling. Minimum operating frequency is measured with a capacitor 1000PF. 1.1 0.4 — — 50Ω Ω

TEST CIRCUIT (Prescaler Input Sensitivity) 1000pF X’tal VCC =5V V p=6V P•G 50Ω 0.1µF Oscilloscope 87654321 9 1 01 11 21 31 41 51 6 MB1507

TYPICAL APPLICATION EXAMPLE LPF VCO Charge Pump Selection (Internal or external) FROM CONTROLLER OUTPUT VPX (6V) 10k 12k 12k 10k 47k 47k 16 15 14 13 12 11 10 9 12345678 ØR ØP f OUT BISW FC LE Data Clock MB1507 OSC IN OSC OUT Vp VCC D O GND LD f in 1000p VCC (5V) 33k 100k 0.01µ 10k X’tal C 1 C 2 0.1µ 6V 5V Vp, VPX : 8V max. C 1, C2 : Depends on crystal oscillator LE,FC : With pull up resistor ØP : Open drain output LOCK DETECTOR

16-LEAD PLASTIC FLAT PACKAGE (Case No. : FPT-16P-M06) Dimensions in inches (millimeters) “A”  1991 FUJITSU LIMITED F16015S-2C .400+.010 –.008(10.15 )+0.25 –0.20 .209±.012 (5.30±0.30) INDEX .004(0.10) .050(1.27) TYP .018±.004 .307±.016 (7.80±0.40) .002(0.05)MIN (STAND OFF HEIGHT) .089(2.25)MAX (MOUNTING HEIGHT) .006+.002 –.001(0.15 )+0.05 –0.02 .020±.008 (0.50±0.20) .027(0.68) MAX .007(0.18) MAX .008(0.20) .016(0.40) Details of “A” part M .350(8.89) REF “B” .268+.016 –.008(6.80 )+0.40 –0.20 .027(0.68) MAX .007(0.18) MAX .006(0.15) Details of “B” part .008(0.20)

All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.

For further information please contact: Japan North and South America Europe Asia Pacific FUJITSU LIMITED Electronic Devices International Operations Department KAWASAKI PLANT, 1015 Kamikodanaka, Nakahara–ku, Kawasaki–shi, Kanagawa 211, Japan Tel: (044) 754–3753 FAX: (044) 754–3332 FUJITSU MICROELECTRONICS, INC. Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA Tel: (408) 922–9000 FAX: (408) 432–9044/9045 FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10,

63303 Dreieich-Buchschlag,

Tel: (06103) 690-0 FAX: (06103) 690-122 FUJITSU MICROELECTRONICS ASIA PTE LIMITED No.51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 0718 Tel: 336-1600 FAX: 336-1609 9501  FUJITSU LIMITED Printed in Japan