MB1503

MB1503 FUJITSU | Alldatasheet

Document overview

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Technical content

Features

• High operating frequency : fIN = 1.1GHz (PIN = –10dBm)
• Pulse-swallow function : High-speed dual-modulus prescaler with 128/129 divide ratio
• Low supply current : I CC = 8mA typ. at 5V
• Power-saving stand-by mode : 100µA
• Serial input, 18-bit programmable divider consisting of: – Binary 7-bit swallow counter : 0 to 127 – Binary 11-bit programmable counter : 16 to 2,047
• Serial input 15-bit programmable reference divider consisting of: – Binary 15-bit programmable reference counter: 8 to 16,383 – 1-bit switch counter sets prescaler divide ratio
• On-chip analog switch for fast lock-up
• On-chip charge pump
• Wide operating temperature range: –40 to +85°C
• Plastic 16–pin dual inline package (Suffix : –P) Plastic 16–pin small outline package (Suffix : –PF) ABSOLUTE MAXIMUM RATINGS (See NOTE) Ratings Symbol Value Unit VCC –0.5 to +7.0 V Supply Voltage VP VCC ≤ VP ≤ 10.0 V Output Voltage V OUT –0.5 to VCC +0.5 V Output Current I OUT ±10 mA Storage Temperature Tstg –55 to +125 °C LOW-POWER PLL FREQUENCY SYNTHESIZER WITH POWER SAVE FUNCTION (1.1GHz) MB1503 PLASTIC PACKAGE (FPT-16P-M06) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PLASTIC PACKAGE (DIP-16P-M04)

(TOP VIEW)

S W OSC IN OSC OUT VP VCC Oscillator Lock Detection Circuit 16-bit Shift Register 16-bit Shift Register 15-bit Latch 15-bit Latch Programmable Reference Divider Binary 14-bit Reference Counter Intermittent Operation Control Circuit Phase Comparator Phase Characteristics Changing Circuit Charge Pump BiSW Data Schmitt Trigger Schmitt Trigger Schmitt Trigger 1-bit Control Latch 19-bit Shift Register 19-bit Shift Register 7-bit Latch 18-bit Latch 11-bit Latch Binary 7-bit Swallow Counter Programmable Divider Binary 11-bit Programmable Counter Prescaler Control Circuit To Lock Detector PS1 PS1 From Phase Comparator PS1 PS1 PS1 MC SW From Phase Comparator From Charge Pump PS1 Prescaler Output D O 5 GND 6 LD 7 fIN 8 Clock9 LE11 FC12 fP14 fR15 PS16

Pin No. Pin Name I/O Description

1 OSC IN I Programmable reference divider input

An external crystal is connected to this pin.

2 OSC OUT O Oscillator output

An external crystal is connected to this pin. 3V P – Power supply input for charge pump and analog switch 4V CC – Power supply 5D O O Charge pump output The phase of the charge pump is reversed depending on the FC input.

6 GND – Ground

7 LD O Phase comparator output

The output level is high when LD is locked. The output level is low when LD is unlocked. 8f IN I Prescaler input Connection with an external VCO should be done by AC coupling.

9 Clock I Clock input for 19-bit and 16-bit shift registers

Data is shifted into the shift register on the rising edge of the clock.The Schmitt trigger is contained.

10 Data I Serial data input using binary code

The last bit of the data is a control bit. When the control bit is high, data is transmitted to the 15-bit latch. When it is low, data is transmitted to the 18-bit latch.The Schmitt trigger input is involved.

11 LE I Load enable signal input

When LE is high, the data of the shift register are transferred to a latch, depending on the control bit in the serial data. At the same time, an internal analog switch turns on and the output of the internal charge pump is connected to the BiSW pin.The Schmitt trigger input is involved.

12 FC I Phase select input of phase comparator (with internal pull-up resistor)

When FC is low, the characteristics of the charge pump and phase comparator are reversed. The FC input signal is also used to control the f OUT pin (test pin) of fR or fP.

13 BiSW O Analog switch output

BiSW is usually in the high-impedance state. When the switch is turned on (LE is high), the state of the internal charge pump is output. 14 f P O Monitor pin of programmable counter output 15 f R O Monitor pin of reference counter output

16 PS I Power save signal input

Set PS low while the system is powered (never use pin 16 as it is opened) PS = High : Operation mode PS = Low : Stand-by mode

The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC ÷ R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (16 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383) M : Preset divide ratio of modules prescaler (128) Serial data input Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit programmable divider separately. Binary serial data is input to the Data pin. One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, stored data is latched depending on the control data as follows: Control data Destination of serial data H 15-bit latch L 18-bit latch (a) Programmable reference divider ratio The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The serial 16-bit data format is shown below: SSSSSSSSSSSSSS C123456789 1 0 1 1 1 2 1 3 1 4 S W Direction of data shift Control bit LSB Divide ratio setting bit for prescaler MSB Divide ratio setting bit for programmable reference counter

• 14-bit programmable reference counter divide ratio Divide ratio S S S S S S SSSSSSSS R 1 4 1 3 1 2 1 1 1 0 987654321 8 00000000001000 9 00000000001001 16383 1 1 1 1 1 1 1 1 1 11111 (Divide ratio = 8 to 16,383) Notes: 1. Divide ratios less than 8 are prohibited 2. SW: This bit selects the divide ratio of the prescaler SW Low: 128 or 129 (SW must be always be low) 3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383) 4. C: Control bit: Set high 5. Input MSB data first (b) Programmable divider divide ratio The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and 11-bit programmable counter. The serial 19-bit data format is shown below: SSSSSSSSSSSSSSSSSS C123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 Direction of data shift Control bit LSB MSB Divide ratio setting bit for swallow counter Divide ratio setting bit for programmable counter

• 7-bit swallow counter divide ratio • 11-bit programmable counter divide ratio SSSSSSS 7654321 0 0000000 1 0000001 1 2 7 1111111 Divide ratio A SSSSSSSSSSS 18 17 16 15 14 13 12 11 10 9 8 1 6 00000010000 1 7 00000010001 2047 1 1 1 11111111 Divide ratio N (Divide ratio = 0 to 127) (Divide ratio = 16 to 2,047) Notes: 1. Divide ratios less than 16 are prohibited for the 11–bit programmable counter 2. S1 to S7: These bits select the divide ratio of the swallow counter (0 to 127) 3. S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047) 4. C: Control bit: (Set low) 5. Input MSB data first Serial data input timing
• t1 (≥ 1µs) : Data setup time t 2 (≥ 1µs) : Data hold time t 3 (≥ 1µs) : Clock pulse width t4 (≥ 1µs) : LE setup time to the rising edge of last clock t5 (≥ 1µs) : LE pulse width S18 = MSB S17 S10 S9 S1 = LSB C: Control bitData Clock LE (S14) (S8) (S7) (S1) (C: Control bit)(SW) (∗1) t1 t2 t3 t4 ∗1 : Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected. Note: One bit of data is shifted into the shift register on the rising edge of the clock.

Intermittent operation limits power consumption by shutting down or starting the internal circuits according to their necessity. If device operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined phase relationship between the reference frequency (fR ) and the comparison frequency (fP) and frequency lock is lost. To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forcibly correcting the phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set high, the circuit enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is explained below:

• Operating mode (PS =High Level) All circuits are operating, and PLL operation is normal.
• Stand-by mode (PS = Low level) Circuits that do not affect operation are powered down to limit current consumption. The current in the power save state is typically 100µA. At this time, the levels of D O and LD are the same as when the PLL is locked. Since DO is placed in the high-impedance state and the input voltage of the voltage controlled oscillator (VCO) is set to the voltage in the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO (fVCO ) is kept at the locking frequency. The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly correcting the phase of the reference and comparison frequencies to limit power consumption. The device must be set in the stand-by mode (PS = low) when it is powered up. Relationship between the FC input and phase characteristics The FC pin changes the phase characteristics of the phase comparator. The internal charge pump output level (DO ) is reversed, depending on the FC pin input level. The relationship between the FC input level and DO is shown below: FC = High or open FC = Low fR > fP HL fR < fP LH fR = fP Z (∗1) Z ( ∗1) ∗1: High impedance When designing a synthesizer, the FC pin setting depends on the VCO characteristics. VCO input voltage VCO output frequency ∗: When the VCO characteristics are similar to , set FC high or open. ∗: When the VCO characteristics are similar to , set FC low.

Phase comparator output waveform (FC = High) fR fP LD D O Z H L fR > fP fR = fP fR < fP fR < fP fR < fP Notes: 1. Phase difference detection range: –2π to +2π 2. Spike appearance depends on the charge pump characteristics. Also, the spike is output to diminish dead band. 3. When fR > fP or fR < fP, a spike might not appear depending on the charge pump characteristics. 4. LD is low when the phase difference is tw or more. LD is high when the phase difference is tw or less for three or more cycles (when fOSCIN = 12.8MHz, tw = 625 to 1,250ns). Analog switch The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (DO ) is output through the BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state. When LE = high (when the divide ratio of the internal divider is changed): Analog switch = on When LE = low (normal operating mode): Analog switch = off The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up time when the PLL channel is changed. CHP LPF–1 LPF–2 VCO Analog switch BiSW (Control signal LE) D O

RECOMMENDED OPERATING CONDITIONS Parameter Symbol Unit VCC 4.5 5.0 5.5 V Supply Voltage VP VCC ≤ VP ≤ 8.0 V Input Voltage V I GND – V CC V Operating Temperature T A –40 – +85 °C Value Min Typ Max

• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover work- benches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices. HANDLING PRECAUTIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Unit Condition Supply Current I CC – 8.0 12.0 mA Stand-by Current IPS – 100 – µA fIN fIN 10 – 1100 MHz Operating Frequency OSC IN fOSC – 12 20 MHz fIN Pf IN –10 – 6 dBm Input Sensitivity OSC IN VOSC 0.5 – – Vp–p High-level Input Voltage V IH VCC x 0.7 – – V Low-level Input Voltage V IL –– V CC x 0.3 V High-level Input Current I IH – 1.0 – µA IIL – –1.0 – µA Low-level Input Current FC I FC – –60 – µA Input Current OSC IN IOSC – ±50 – µA High-level Output V OH 4.4 – – V V CC = 5V Low-level Output Voltage V OL – – 0.4 V High-impedance VDO = GND to 8V Cut off Current VCC ≤ VP ≤ 8V IOH –1.0 – – mA Output Current IOL 1.0 – – mA Analog Switch ON Resistance R ON –2 5– Ω Value Min Typ Max With fIN = 1.1GHz, OSCIN = 12MHz, VCC = 5.0V. Inputs are VCC and outputs are open. With fIN = 1.1GHz, OSCIN = 12MHz, VCC = 5.0V. The PS pin is grounded, remain- ing inputs are at VCC , and outputs are open. AC coupling. The minimum operating frequency is measured with a 100pF ca- pacitor connected. Except fIN and OSC IN Data, Clock, LEExcept DO and OSC OUT D O IOFF – – 1.1 µA Except DO and OSC OUT Voltage

(FOR MEASURING PRESCALER INPUT SENSITIVITY) 87654321 9 1 01 11 21 31 41 51 6 1000p 50Ω 0.1µ VCC = 5V X’ tal VP = 6V VCC = 5V Oscilloscope P · G

0.1µ C 1 X’ tal 6V LPF VCO PS f R fP BiSW FC LE Data Clock OSC IN OSC OUT VP VCC D O GND LD f IN C 2 47K 47K Output From controller VP, VPX : Maximum 8V C 1, C2 : Depends on the crystal parameters

inches (millimeters) “A” 16-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-16P-M06)  1991 FUJITSU LIMITED F16015S-2C .400+.010 –.008(10.15 )+0.25 –0.20 .209±.012 (5.30±0.30) INDEX .004(0.10) .050(1.27) TYP .018±.004 .307±.016 (7.80±0.40) .002(0.05)MIN (STAND OFF HEIGHT) .089(2.25)MAX (MOUNTING HEIGHT) .006+.002 –.001(0.15 )+0.05 –0.02 .020±.008 (0.50±0.20) M .350(8.89) REF “B” .268+.016 –.008(6.80 )+0.40 –0.20 .027(0.68) MAX .007(0.18) MAX .006(0.15) Details of “B” part .008(0.20) .027(0.68) MAX .007(0.18) MAX .008(0.20) .016(0.40) Details of “A” part

inches (millimeters) 16-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-16P-M04)  1991 FUJITSU LIMITED D16033S-2C .770+.008 –.012(19.55 )+0.20 –0.30 .039+.012 (0.99 )+0.30 .244±.010 (6.20±0.25) INDEX-1 .100(2.54) TYP .050(1.27) MAX .020(0.51)MIN .172(4.36)MAX .118(3.00)MIN .300(7.62) TYP 15°MAX .060+.012 (1.52 )+0.30 INDEX-2 .010±.002 (0.25±0.05) .018±.003 (0.46±0.08)