MB1501 FUJITSU | Alldatasheet

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Edition 6.0a DATA SHEET Copyright  1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC. ABSOLUTE MAXIMUM RATINGS (see NOTE) Rating Power Supply Voltage Symbol Value Unit NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN ASSIGNMENT This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. How- ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated volt- ages to this high impedance circuit. SERIAL INPUT PLL FREQUENCY SYNTHESIZER MB1501/MB1501H/MB1501L Output Voltage Output Current VCC IOUT mA PLASTIC PACKAGE FPT-16P-M06 VPH ±10 V V TSTG °CStorage Temperature –55 to +125 Open-drain Output VVOUT V –0.5 to +7.0 VCC to 12.0 –0.5 to VCC +0.5 16OSC IN OSC OUT VP VCC D O GND LD fin ØR ØP f P fr FC LE Data Clock ( TOP VIEW ) SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH 1.1GHz PRESCALER The Fujitsu MB1501/MB1501H/MB1501L, utilizing BI-CMOS technology, is a single chip serial input PLL frequency synthesizer with pulse-swallow function. The MB1501 series contain a 1.1GHz two modulus prescaler that can select either 64/65 or 128/129 divide ratio; control signal generator; 16-bit shift register; 15-bit latch; programmable reference divider (binary 14-bit programmable reference counter); 1-bit switch counter; phase comparator with phase inverse function; charge pump; crystal oscillator; 19-bit shift register; 18-bit latch; programmable divider (binary 7-bit swallow counter and binary 11-bit programmable counter). The MB1501 operates on a low supply voltage (3V typ) and consumes low power (45mW at 1.1GHz). PLASTIC PACKAGE DIP-16P-M04 MB1501 VP Voltage VOOP Voltage Lock up time D O Output Width High-level Output Current Low-level Output Current 8V max 8.5V max Middle speed Middle Middle Middle MB1501 Product Line Condition VP,VPL MB1501H MB1501/1501L V CC to 10.0 VOOPH –0.5 to 11.0 VOOP ,VOOPL MB1501H MB1501/1501L –0.5 to 9.0

  • High operating frequency: fIN MAX =1.1GHz (PIN MIN =0.20VP-P)
  • On-chip prescaler
  • Low power supply voltage: 2.7V to 5.5V (3.0V typ)
  • Low power supply consumption: 45mW (3.0V, 1.1GHz operation)
  • Serial input 18-bit programmable divider consisting of: Binary 7-bit swallow counter (Divide ratio: 0 to 127) Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
  • Serial input 15-bit programmable reference divider consisting of: Binary 14-bit programmable reference counter (Divide ratio: 8 to 16383) 1-bit switch counter (SW) Sets divide ratio of prescaler
  • 2types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump
  • Wide operating temperature: TA=–40°C to +85°C MB1501H 10V max 10.0V max High speed Low High Low MB1501L 8V max 8.5V max Low speed High Low High

MB1501/MB1501H/MB1501L BLOCK DIAGRAM VCC GND 16-Bit Shift Register 16-Bit Shift Register 15-Bit Latch 15-Bit Latch11LE Programmable Reference Divider Binary 14-Bit Reference Counter 1-bit SW Crystal Oscillator Circuit OSC IN 1 OSC OUT 2 19-Bit Shift Register 19-Bit Shift Register 18-Bit Latch 7-Bit Latch 11-Bit Latch Programmable Divider Control Circuit Binary 7-Bit Swallow Counter Binary 11-Bit Programmable Counter 10Data Control 1-Bit Latch Prescaler Circuit 9Clock 8fin Phase Comparator Charge Pump fr FC LD R P D O5 fP14 VP3

Pin No. Pin Name Descriptions OSC IN VP Oscillator input. Oscillator output. A crystal is placed between OSCIN and OSCOUT . Power supply input for charge pump. 4 VCC Power supply voltage input. OSC OUT D O5 Charge pump output. Phase characteristic can be inversed depending upon FC input. 6 GND Ground. LD Phase comparator output. This pin outputs high when the phase is locked. While the phase difference of fr and fp exists, the output level goes low. fin Prescaler input. The connection with an external VCO should be an AC connection. Clock9 Clock input for 19-bit shift register and 16-bit shift register. Each rising edge of the clock shifts one bit of data into the shift registers. Serial data of binary code input. The last bit of the data is a control bit. The last data bit specifies which latch is activated. When the last bit is high level and LE is high-level, data is transferred to 15-bit latch. When the last bit is low level and LE is high level, data is transferred to 18-bit latch.

10 Data

Load enable input (with internal pull up resistor). When LE is high level (or open), data stored in the shift register is transferred to latch depend- ing on the control data. FC Phase selecting input of phase comparator (with internal pull up resistor). When FC is low level, charge pump and phase detector characteristics can be inversed. 13 Monitor pin of phase comparator input. It is the same as programmable reference divider output. fr fP Monitor pin of phase comparator input. It is the same as programmable divider output. Outputs for external charge pump. Phase characteristics can be inversed depending on FC input. P pin is an N-channel open-drain output. P I/O I O O O I I I I O O O O O R

Serial data input is input using Data pin, Clock pin and LE pin, The 15-bit programmable reference divider and 18-bit programmable divider are controlled respectively. On rising edge of the clock shifts one bit of the data into the internal shift registers. When load enable (LE) is high level (or open), data stored in shift resisters is transferred to 15-bit latch or 18-bit latch depending upon the control bit level. Control data “H” ; Data is transferred into 15-bit latch. Control data “L” ; Data is transferred into 18-bit latch. PROGRAMMABLE REFERENCE DIVIDER Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below. 1234 S S S S S S S 11 12 SS S

14 SWC

Divide ratio of prescaler setting bit MSB S 14 13 12 11 S S S S S S S SS S SS S SDivide ratio R 0 0 000000001000 10010000000000 SW: Divide ratio of prescaler setting bit. SW=“H” : 64 SW=“L” : 128 S1 to S14: Divide ratio of programmable reference counter setting bits (8 to 16383) C: Control bit (Control bit is set to high.) 14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO First data inputLast data input Data input Divide ratio less than 8 is prohibited. Divide ratio R: 8 to 16383 16383 1 1 1 1 1 111111111 Divide ratio of programmable reference counter setting bits

Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter. Serial 19-bit data format is shown below. 1234 S S S S S S S 11 12 SS S S C SS S Control bit LSB MSB S S S S Divide ratio of programmable counter setting bits S S S S SS S Divide ratio A 0000000 1000000 Divide ratio A : 0 to 127 18 17 16 15 S S S S S S S SS S SDivide ratio N 00000010000 10001000000 Divide ratio less than 16 is prohibited. Divide ratio N : 16 to 2047 First data inputLast data input Data input 7-BIT SWALLOW COUNTER DIVIDE RATIO 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO S8 to S18 :Divide ratio of programmable counter setting bits (16 to 2047) S1 to S7 : Divide ratio of swallow counter setting bits (0 to 127) C: Control bit (Control bit is set to low.) Dara is input from MSB data. 127 1 111111 2047 1 1111111 111 Divide ratio of swallow counter setting bits

On the rising edge of the clock shifts one bit of the data into the shift registers. Parenthsis data is used for setting the divide ratio of the programmable reference divider. t1 – t5 ≥ 1µs SERIAL DATA INPUT TIMING Data Clock LE S18=MSB *(SW) (S14) S17 S10 (S8) (S7) (S1) S1=LSB (C: Control bit) C: Control bit t2 t3 PHASE CHARACTERISTICS fr>fp fr<fp fr=fp FC=H (or open) FC=L D O R P D O R P HLLLHZ L ZLZ HZH Z L L L Z Note: Z=(High impedance) VCO CHARACTERISTICS VCO INPUT VOLTAGE FC pin (pin 12) is provided to inverse the phase comparator characteristics. The characteristics of internal charge pump output (DO ), phase detector outputs (R, P) can be inversed depending upon FC input data. Outputs are shown below. Depending upon VCO characteristics, FC pin should be set accord- ingly: When VCO characteristics are like , FC should be set high or open circuit; When VCO characteristics are like , FC should be set Low. VCO OUTPUT FREQUENCY

RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Typ Max Power Supply Voltage Input Voltage Operating temperature VCC VIN TA 2.7 GND –40 3.0 5.5 VCC +85 V V VPH V VCC 10.0 Open-drain Output VOOPH 10.0 V VP, VPL VCC 8.5MB1501 MB1501L MB1501H VOOP , VOOPL 8.5MB1501 MB1501L MB1501H VCC VCC

ELECTRICAL CHARACTERISTICS

(VCC =2.7 to 5.5V, TA =–40 to +85°C) IOZ IDOL IDOHL IDOLH IDOLL VCC =3V VP=12V, TA=25°C VCC =3V VP=6V, TA=25°C VCC =3V, VP=12V TA=25°C Parameter Symbol Value Unit Min Typ Max Power Supply Current Operating Frequency High-level Input Voltage Low-level Input Voltage High-level Input Current V Low-level Input Current ICC fIN Pfin1 VIN VIH OSC IN Except fin and OSC IN Data, Clock f OSC VIL IIH IIL 15 mA Input Sensitivity OSC IN Input Current IIN ILE OSC IN LE, FC µA µA High-level Output Voltage Low-level Output Voltage VOH VOL N-channel Open-drain Cutoff Current IOFFØP –10 0.5 0.7xVCC 2.4 –60 ±50 –1.0 1.0 0.3xVCC 1100 MHz MHz V P-P µA µA V V V µA1.1 0.4 High-level Output Current Leakage Current IOH –1.0 mA Note: *1 VCC =3.0V, fIN=1.1GHz, fOSC =12MHz crystal. Inputs are grounded except fIN, and outputs are open. *2 Input coupling capacitor 1000pF is connected. fin fin Pfin2 –4 6 dBm Pin Name Condition Low-level Output Current I OL mA1.0 High-level Output Current Low-level Output Current VCC Except D O and OSC OUT Except D O and OSC OUT IDOHH IDOH D O D O , ØP VCC =2.7 to 4.0V VCC =4.0 to 5.5V VCC =3.0V VCC ≤ VP ≤ 8V MB1501H MB1501 MB1501L MB1501H MB1501 MB1501L V CC =3V VP=12V, TA=25°C VCC =3V VP=6V, TA=25°C — dBm — — — — — — mA–2.2 –4.5 — mA–0.5 –2.0 — mA–0.5 –1.1 –2.2 mA2.2 6.0 µA— 1.0 mA4.5 12.0 — mA1.5 6.0 — MB1501H MB1501 MB1501L VCC =3V, VP=9V TA=25°C

TYPICAL CHARACTERISTICS CURVES CHARGE PUMP CHARACTERISTICS MB1501/MB1501H MB1501L VP D O GND 10kΩ3.6kΩ 24.8kΩ 20kΩ VP D O GND 10kΩ12kΩ 12kΩ 10kΩ LOCK UP TIME MEASUREMENT Low unlock condition Lock (533MHz) High unlock condition Lock (518MHz) 1V/div 10ns/div MB1501H MB1501L DO PIN OUTPUT CURRENT CURVES (TYPICAL) VOH vs. IOH VOL vs. IOL MB1501L MB1501H 6.0 7.0 8.0 High-level Output Current IOH (mA) MB1501 MB1501H MB1501L 0.0 1.0 2.0 01 0 2 0 Low-level Output Current IOL (mA) High-level Output Voltage VOH (V) Low-level Output Voltage VOL (V) MB1501

D O PIN OUTPUT WAVEFORM AT LOCK CONDITION 1V/div 100ns/div MB1501 MB1501H MB1501L Output Waveform

PHASE CHARACTERISTICS ( Δf vs. DO OUTPUT ENERGY) 150 100 –50 –100 –150 100 80 60 40 20 0 40 60 80 MB1501H MB1501 MB1501L É É É ÉÉ ÉÉ ÉÉ VCC =V P=3.0V fINSfOSC =12MHz fr=fP=46.9kHz VP D O 10k 10k Oscilloscope (+) Energy (–) Energy Time Δf (ns) Energy (En) – V2t

+10 –10 –20 –30 Input Sensitivity vs. Input Frequency (Supply Voltage Dependence) VCC =2.7V –40 –50 Input Frequency fin (GHz) 1000pF 50Ω VCC =4.5V 81 4 VCC Oscilloscope (Counter) TA =25°C Input Sensitivity vs. Input Frequency (Temperature Dependence) Input Frequency fin (GHz) +10 –10 –20 –30 –40 –50 Guaranteed Operating Area VCC =4.0 to 5.5V VCC =2.7 to 4.0V TA=+25°C TA=+85°C TA=–4.0°C 0.1µF P.G VCC =3.0V 1000pF 50Ω 81 4 VCC Oscilloscope (Counter) 0.1µF P.G Guaranteed Operating Area VCC =4.0 to 5.5V VCC =2.7 to 4.0V VCC =5.5V Input Sensitivity PfIN (dBm)Input Sensitivity PfIN (dBm)

D O Pin Output Current (IOH , IOL ) Measurement

(Divide ratio set- ting) Oscilloscope (10M Ω , 10pF) fIN D O LPF Circuit 1kΩ 4kΩ 4kΩ to VCO 1kΩ 10µF 0.1µF1 µF VCC =3V, VP=8V fVCO =Low unlock condition Step to Lock condition (533MHz) fVCO =High unlock condition Step to Lock condition (518MHz) 12.8MHz Phase Characteristics Measurement MB1501 P ⋅ G P ⋅ G OSCin fin VCC VP D O fr fp 10kΩ 10kΩ Oscilloscope (10MΩ , 10pF) VCC =3V, VP=3V Δf=fr–fp Energy (En)=V2t

TYPICAL APPLICATION EXAMPLE LPF VCO Charge Pump Selection (Internal or external) FROM CONTROLLER OUTPUT VPX (6V) 10kΩ 12kΩ 12kΩ 10kΩ 47kΩ 47kΩ 16 15 14 13 12 11 10 9 12345678 ØR ØP f P fr FC LE Data Clock MB1501 OSC IN OSC OUT Vp VCC D O GND LD f IN 1000pF VCC (3V) 33kΩ 100kΩ 0.01µF 10kΩ LOCK DET. X’tal C 1 C 2 0.1µF 6V 3V C 1, C2 : Depends on crystal oscillator LE,FC : With internal pull up resistor ØP : Open drain output

16-LEAD PLASTIC DUAL IN-LINE PACKAGE (Case No.: DIP-16P-M04) Dimensions in inches (millimeters) 1991 FUJITSU LIMITED D16033S-2C .770+.008 –.012(19.55 )+0.20 –0.30 .039+.012 (0.99 )+0.30 .244±.010 (6.20±0.25) INDEX-1 .100(2.54) TYP .050(1.27) MAX .020(0.51)MIN .172(4.36)MAX .118(3.00)MIN .300(7.62) TYP 15°MAX .060+.012 (1.52 )+0.30 INDEX-2 .010±.002 (0.25±0.05) .018±.003 (0.46±0.08)

16-LEAD PLASTIC FLAT PACKAGE (Case No.: FPT-16P-M06) Dimensions in inches (millimeters) “A”  1991 FUJITSU LIMITED F16015S-2C .400+.010 –.008(10.15 )+0.25 –0.20 .209±.012 (5.30±0.30) INDEX .004(0.10) .050(1.27) TYP .018±.004 .307±.016 (7.80±0.40) .002(0.05)MIN (STAND OFF HEIGHT) .089(2.25)MAX (MOUNTING HEIGHT) .006+.002 –.001(0.15 )+0.05 –0.02 .020±.008 (0.50±0.20) .027(0.68) MAX .007(0.18) MAX .008(0.20) .016(0.40) Details of “A” part M .350(8.89) REF “B” .268+.016 –.008(6.80 )+0.40 –0.20 .027(0.68) MAX .007(0.18) MAX .006(0.15) Details of “B” part .008(0.20)