MB1426

MB1426 FUJITSU | Alldatasheet

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April, 1986 Esition 1.0 DESCRIPTION Rl The MB1426 Error Checking and Correction (ECC) device is designed to yw ‘enhance memory reliability in 16-bit systems. Using a modified Hamming Single- << Error-Correction/Double-Error-Detection (SEC/DED) code, the ECC can find oe and correct all single-bit errors and detect all double-bit errors. The MB1426is a TTL device fabricated in low-power Schottky and is housed in a 64-pin Pin-Grid-Array (PGA) package. FEATURES a © Detects and corrects all single-bit errors & P 2 © Detects all double-bit errors ee an! Witiacsenett © On-chip latches for memory-read, check-bit, and syndrome } ara : data vite © Separate busses for CPU and memory data © Direct read/write by ECC-through mode ‘© Low power Schottky TTL for high performance PGA-64C-A01 © Single +5V supply Tea doce contains creat prot eng aura i ead at armel prcatons be toe Ho Bed sett ot Rah ieee 3.39, :

(OnetnGnS: ~MB1426 PIN ASSIGNMENTS BERBL2L82R8 28 BSERRARRAR 2S 2% 88 a8 28 a8 88 2° 8a ah 23 e3

28 R38

28 B% 2233322200 SFSSZERR28 Sse ess ss [nm [vo [tae [0 | v0 [now tener | vo | noe [or | 8 | coo 7/6 Bt Pwo 4 | 6 cBe

02 PWC1 18 B cB2 CD14 50 8 ces

8 cor [we [wom [oe [ep eoe fot etm oe | coe Lo |e [wo [we | cow fee) we | fos |e [com fa [8 | woe fart) com | ss [6] news foe |e [com |e | moo fae) cer [eve | B 001 23 = MD07 3 | B C006 B MD09 os | o ERR 2 |B MD08 40 GND [8 | mon | [0 | 1 [sree fo [es | we [ele | cow [w]e | now | fs [sree [ar [ 8 [wow [oo] + | emen [se [| rox bet t| stoe [wf jae fw fe fe ree T STCB3 Pt “| ' SLE 61 vec | stose perm [a | 1 | mst fe] a | cow | r [som [oe |e Tm [ef we fe | 6 | con fos | om [xf o | rem fw] a [om [els on | B: Bidirectional pin |: Input pin ©: Output pin

‘apn FUJITSU MB1426 _ tiffin PIN DESCRIPTIONS Pin No. | Designator Function

33 PWCO —_| Partial Write Control/Read Write Control:

2 PWC1 —_| These pins are used to control read write and they are also used to control the partial write. If both PWCD and PWC1 = "H’ the read operation is selected if both PWCO and PWC1 = “L" the word write operation is selected. In the partial write mode, if PWCO = “L” and PWC1 = “H’, the lower byte (MDO to MD7) is written CPU data and the upper byte (MD8 to MD15) is written memory data which is latched during previous read operation. On the other hand, if PWCO = "H" and PWC1 = “L" the lower byte is written memory data and the upper byte is written CPU data.

59 RCLK Read Data Latch Clock:

This pin is used to strobe the read data from memory and latch into the internal read data latch. ‘The rising edge of RCLK strobes read data from MD00/MD15 and check bits from CBO/CBS. In the read cycle, data is strobed on the rising of RCLK. 45 ste Syndrome Latch Enable: This pin is used to latch syndrome bits into the internal syndrome latch. The falling edge of SLE strobes and latches the syndrome bits until RST = "L’

46 RST ‘Syndrome Latch Reset:

This pin is used to reset syndrome latch. If RST = “L’, the syndrome latch is reset and the latch is enabied to accept next string of syndrome bits.

43 ERREN | Error Enable:

This pin is used to enable ERR and MERR outputs. If ERREN = “L', ERR and MERR are set “H” and disabled.

44 EN ‘Syndrome Output Enable:

This pin is used to enable syndrome outputs (STCBO and STCBS), If EN = “L", STCBO/STCBS are enabled. If EN = “H’, STCBO/STCBS are disabled and in the high- impedance state.

38 ECCTH | ECC Through

This pin is used to enable the ECC-through mode. if ECCTH = “L", ECC-through mode is enabled anc the read or write cycle is executed without regard to the ECC function. When ECC is utilized, the ECCTH pin must be “H BSCNT | Bus Control This pin is used to control the operating mode of data pins CDO0/CD15 and MDOO/MD15, also to disable PERRO, PERR1 anc PERR. \\f BSCNT = “L’ all data pins are in the input mode and PERAO, PERR1 and PERR are disabled (set “H’). If BSCNT = “H", the operating mode of these data pins is controlled by the states of PWCO, and PWC1, and PERRO, PERR1 and PERR are enabled corresponding the the state of PWCO and PWCI 42 cD00 CPU Data: a cues These pins have a common I/O capability and are connected to the CPU data bus. 6 CD03 In the write cycle, these pins are in the input mode, that is, the CPU data is input to these pins and 341 ,

etait ~-MB1426 PIN DESCRIPTIONS (continued) _ Pin No. | Designator Function 5 CD04 ‘output to memory through MDO0/MD15.

4 CD05 —_| In aread cycle, these pins are in the output mode, that is, memory data from MDOO/MD15 is

39 CD06 —_| output to the CPU via these pins. 3 cpo7 1 coos 37 cDos 36 co10 64 cot 35 cp12 63 cp13 4 co14 62 cos

51 MD00 | Memory Data:

2 woos These pins have a common I/O capability and they are connected to the memory data bus. 20 MDO3 In a write cycle, these pins are in the output mode, that is, CPU data from CD00/CD15 is output to 241 MDO4 memory through these pins. 53 MD05__| In a read cycle, these pins are in the input mode, that is, memory data is input to these pins and 22 MDO6 ‘output through CD00/CD15.

23 MDO7

24 MD08

55 MD09

5 M010

56 MD11

16 MD12

57 M13,

7 MD14

58 M015

PO Parity Bit: PI These pins have a common I/O capability and PO and P1 correspond, respectively, to the lower byte and the upper byte. The parity bit from the CPU should be odd parity.

16 Bo Check Bit

% e ‘These pins have a common I/O capability and are connected to the check bit memory I/O line. 48 ces In awrite cycle, check bit data is generated by the check bit generator using CPU data; the 49 ces Check-bit pattern is output to check bit memory, that is, during a write cycle, these pins operate in 50 CBS the output mode. Ina read cycle, the check-bit pattern from memory is input to these pins, that is, during a read cycle, these pins operate in the input mode.

10 STCBO ‘Syndrome-Through Check Bit:

u STCB! | These pins output the syndrome bits when read or partial write is selected. These outputs are 8 Sees used to analyze an error bit in the data word (CD00/CD15) and in the check bits (CBO/CBS). 14 sTcB4 _| Inthe ECC-through mode, these pins output the check bits from memory. 16 sTOBS Error This pin outputs the error flag when any single- or multiple-bit error is detected 342

PIN DESCRIPTIONS (continued) Pin No. | Designator Function

9 MERR Multiple Error:

This pin outputs the multiple error flag when a multiple-bit error is detected.

32 PERRO Parity Error:

30 PERRT | These pins output a parity error flag when parity error occurs on CPU data. If PERRO = “L’, a 6 PERR | parity error on CD00/CDO7 and PO occurs. If PERRI = “L’, a parity error on CD8/CD16 and P1 occurs. PERR = PERRO - PERRY. BLOCK DIAGRAM cow 000 corn — moor TT f-f_1C aoe[ [tr MY Jp= coe ia wo o me «| ° we | ower J] Em a [|

5 LTT] ms

| | : mi [| ‘ moa ‘“ ° —] srceo = | = —.. J sreas = at ‘DS : Data Selector ED: Error Detector CSB: Control Signal Buffer PC: Parity Checker DC: Data Corrector ‘SD: Syndrome Decoder CG: Check Bit Generator LT : Latch SG: Syndrome Generator PG: Parity Generator 343 ,

‘DGEBA: FUJITSU CmimCIne ~—MB1426 ANALYSIS OF BLOCK DIAGRAM Ifa single-bit error is detected, the ERR flag is raised and the 7 error is corrected by the data corrector, the corrected data is Bs (Data Selector): Selects memory-read or memory-write ‘output to CD00/CD15. When asingle-bit error is detected and SLE is driven Low, the falling edge triggers the syndrome DC (Data Corrector): Corrects a single-bit error by using _ latches; this latched data is output to STCBO/STCBS when syndrome decoder. EN is driven Low. Because data is held in the syndrome . - bit latches until RST is driven Low, “RST = L" should be executed location. ED (Error Detector): Detects single-bit or double-bit errors of If multiple-bit errors or a bit string (Os or 1s) erroris detected, memory-read data (MD00/MD15 and CB0/CB5). Single-bit or both ERR and MERR flags are raised and the latched memory double-biterrorsare determined, respectively. by the states of Gata is output to CDOO/CD15. For these cases, the data EAR and MERR. correction cycle is not executed. ‘SG (Syndrome Generator): Generates asyndrome-bit pattern In the read cycle, odd parity bits for bytes MD00/MDO7 and to check memory-read data. MD08/MD15, respectively, are output to PO and P1. SD (Syndrome Decoder): Decodes syndrome-bit pattern of . ‘Syndrome Generator. When a single-bit error is detected, Write Cycle locates error bit and inverts the parity bit. Write capabilities of the MB1426 include both word write and . partial (byte) write; either operation can be selected by setting CSB (Control Signal Buffer): Buffers all control signals, PWGO and PWC to the proper states—see Truth Tables that CG (Check Bit Generator): Generates check bit for checking _ follow. If the CPU is capable of parity coding, the parity bits of memory-write data. PO and P1 are utilized and, in both the word and paritial-byte PG (Parity Generator): Generates odd parity bit for bus data. Wt® modes, the parity bits are checked . The word write mode is executed by setting both PWCO and PC (Parity Checker): Checks odd parity bit for bus data BWC? to the Low state. In the word-write mode, CPU data ‘SDS (Syndrome Data Selector): Selects syndrome data or _ from CDOO/CD15is transferred to the check-bit generator and memory-check bit, to MD00/MD15. Data appearing at MD00/MD15 is output and written into memory. The check-bit generator uses the CPU FUNCTIONAL DESCRIPTION data to generate the check bits and these are output to The error-detecting and error-correcting capabilites of the CB0/CBS. The CPU and check-bit data are written into MB1426 ECC provides the user with ahigh order of contidence -"®OrY during the same write cycle. in memory reliability. Using a modified Hamming SEC/DED The partial write mode is executed by setting either PWCO or code, the ECCis able to detect and correct all single-biterrors PWCT to the Low state. If PWCO is Low and PWCT is High, and to detect all double-bit errors, even those containing the partial write is performed on byte CD00/CD07; in reverse consecutive strings of Os and 1s. The detect/correct cycle for states, byte CD08/CD15 is affected. Before a partial write is single-bit errors occurs without interrupting the CPU. Error executed, the memory and check-bit data must be latched by flags notify the user when an error is detected. setting BBSCNT to the Low state; this action puts ‘The MB1426 has on-chip latches for memory-read, check-bit, __ ©D00/CD15, MD00/MD15, PO, and P1 in the input mode and and syndrome data; latching of the memory data allows the _-_VOIdS data output to the CPU and memory. user to execute a partial (byte) write. To further enhance ‘The 8-bits of CPU data to be written to memory and the data transmission reliability, a parity generator and checker is to be read from memory are sent to the check-bit generator available to the user. A brief description of the read, write, and __ and to MD00/MD15; the data on MD00/MD15 is written into partial-write capabilities are described in subsequent para- memory. Check bits are generated from 8-bits of CPU data graphs; fora detailed analysis of operating principles, refer to and 8-bits of memory data and the check bits are then output the Functional Truth Tables. to CBO/CBS. The partial write operation can be summarized Read Cycle as follows: PWCi tothe High state. The data and check bits from memory aaa are read out and latched on the rising edge of RCLK, the —~ Set either PWCO or PWC1 Low and execute a write cycie. latched data is sent to the syndrome generator and data (In this case, BSCNT should be High to change MD00/ corrector. The syndrome bit pattern is generated and decoded MD15 from the input to the output mode.) bythe syndrome decoder; the decoded resultsare then sentto. _ — Check bits are generated by 8 bits of CPU data and 8 bits of the data corrector. memory data. 3.44

‘tne FUJITSU MB 1426 Wiles FUNCTIONAL TRUTH TABLES CPU Bus/Memory Bus Control a _ [nor mc [ne | S| SR = BSCNT _ PWCO Pwct | CD07, PO CD15, Pt M00 to MDOT MD08 to MD15 Function | OH | oH Output Output Input Input Read ee ee ee bacterin netion | vow Syndrome Output Control ee zecra | Pwo | pwei | &w | ceowces | stosomstoss | Fncton | H H Input Syndrome _ Feed a —t a a a Hamming Code a : CPU Data __ _ ropa talele ele] ze] [mln | alm [uli | runctn leo t px? te, fel [xf [xf [xt [xt [x] ove ee a rxtx [xpxtx[x|x| fe] | |x| em | [eae [xi x[x| |x BPE xf een ee x px epee | one 3-45 ;

en ~=MB1426 FUNCTIONAL TRUTH TABLES (continued) Check Bit Generation (©B0 = CD01 + CDO3 + CONS + CDO7 + CD09 CD11 + CD13 + CDIS €B1 = CD02 + CDG3 + CDO6 + CDG7 + CD10 + GDIT + CDi4> CDIS CB2 = CD04 + CDOS + CD96 + CDOT + CDOB + CDO9+ CD10 + CD12 + CD15 ©B3 = CD00 + CD01 + CD02 + CDOS + CDOs + CDOS + CD06 + CD07 + CDOB (©B4 = CD00 + CD01 + CDo2 + CD04 + CDO7 + CD12 + CD13 + CD14 + CD15 CBS = CD00 + CD08 + CD09 + CD10 + CD11 + CD12 + CD13 + CD14 + COIS Syndrome Decode Error Bit Syncrome No tsrea) [0] 22] oa| o¢|os [os [ar] os] oo] to] [ve] [ulus] o[ 1 [2a [e[s| enor |e fefsfofsfolsfolafolifolifojrjols[sfololofo| 2 2 Bena [s{+fofo|s[r]o/s [ol ole! fojafolols|+'s[s[s[a[r[ofrfolo a fololsfolo| pos [ltt pilss[ifofolefolofolofolololsfolof o | p+ [eisisfofsfofotsfofofolels[a[aiafoloofoli lof o | Los [sfofofofofofofofifsfaieie[y| fi fofofofofofs[ > | Error Detection and Correction _ ERR |MERR| Message | Detect | Correct [ H | H [Noto | - | = | [ie [ ws oreror [ve | ve Ce Te Tne at erar| yee | no | Error Flag Control wom! owe | wee | ERREN | ECCTH | PWCO | PWCi | MERR oj; 4 1 1 1 0 enable 3-46

MB1426 _iieeniannaiie Parity Error Flag Control =) [ae [eam H Hq H 4 L enable 4 enable a H. Disable state ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Vo | 051055 Output High Current | ton |_| 33 [Sonariemoe [Teo [sem [-c] [Ameninopie| a | @ | |e [e| Note: Permanent device damage may occurit ABSOLUTE MAXIMUM RATINGS bre exceeded, Functional operation shouldbe restricted tothe conditions At detatein ie operational specications ofthis data sheet Exporure to absolute maximum rating conditions for extended periods may affect device reliably. DC CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Value cmon [a] tw [| ow | contin Except for PWCO, BwCi, ECCTH | Input Low Current —— I UA | Voc = 5.5V, Viv = 05V PWCO, PWCI, “400 ECCTH Input High Current [iw [OT | tine Voc = 5.5V, Vin = 5.5V Input Clamp Voltage Vic Voo = 45V, = -18mA Output Low Voltage Vou | 05 | Veo = 4.5V, lo. = 10mA reso oe ec 347

it ~=MB1426 AC CHARACTERISTICS (continued) (Recommended operating conditions and AC test conditions unless otherwise noted.) ee sea a ce Delay Time from RCLK to ERA toxer | | 2 | x7 | ns | Delay Time from RCLK to MERR toxwen ea 42 Delay Time from ERREN to ERR, MERR | tenen | ion [at [Wo SeupTinewannonoRcK S| ws P| | Se a CB Hold Time referenced to RCLK tceckH | 10 | [oasieTinestcotonwcorwcr | teu TemieTie fon ra inom PwOORRGT | me || | | | [owyTimevencowse | ef | ert | Delay Time from CD to CB | tcoce | | at | a4 | ns | Delay Time from CD to PERRO/PERAT 2 | a5 | Delay Time from CD to PERR - | tcorer | 23 | 38 | Cony Tne om uPHWwPEROPERT | tw || | [oe tietomromiorem | ten | tw | [enwieTine rm rem wCRAWET See | | Enable Time of CD from PWCO/PWC1 topze [ 2 | 32 | ns | [oney are tomPwcnrwotwreme S| tw || | | | [enmieTinestMOremasor ite || | | lowwytinetonsigwsres ——SSS~d tee | | Enable Time of STCB from EN terze! (15s | 24 | CLK Set Up Time referenced to SLE Zz tssu! [| [oy TwetommowrahSSC*dtC ee P| | Delay Tine rom GB to STCB [tcesme |e | 0 | mw | RCLK Set Up Time referenced to PWCO, PWC1 [ tons? | or | | | | PWCO, PWC1 Set Up Time referenced to BSCNT — o | | “ns Delay Time from PWCO/PWC! to CD i |__tscn? _ns 3-48 .

Ane, FUJITSU MB1426 _ sinipsietl AC CHARACTERISTICS (continued) (Recommended operating conditions and AC test conditions unless otherwise noted.) | Value Parameter 7 _ _ _ _Symbot_ _Min {ve _ Max Unit RCLK Pulse Width two 20 ns RST Pulse Width twast 20 ns SLE Pulse Width | woe 20 | | ns Notes: "Syndrome Laten 2. EGC-Tnrovgh Moae 3 eartal Wrte Mode AC TEST CONDITONS Output Load: Timing Waveform: vec sw — l" bead eT wweur me th os ia m je ree] (oem - | tw amy ouTeuT ‘MEASURING bad von nate, a, a pany x « wm] |= von ev OM OSs swe | Parameter | Symbol | RL(Q) i) | eur | sws | swe | Delay Time teu soK | 50 of | On i to ms | tee Tom on | 1 | Enable Time | (Pz ok =| 05k 5 | of | on | teuz Off On | teen | I of | on | 349 :

im [a ULEILEN SE NLTLITITL a eee Zoom [LET = NUZIIETTETL a wk ZZ) ene [IQ 2 3-50 ;

I MB1426 anata TIMING DIAGRAMS (continued) Write Mode (Word Write) Rea ‘inp =, vauo oe = va = ial ANN INN Eco

‘aedetenetet sian MB1426 TIMING DIAGRAMS (continued) Partial Write Mode (Byte Write) # 777K = XILITZTD v z OS on (Output) MOY VALID {QQ ° ZA DoT cane Syndrome Latch

‘Reese FUJITSU MB1426 __/inilfetnuinuiatin PACKAGE DIMENSIONS 64-Lead Ceramic (Metal Seal) Repeated Quad In-Line Package {PGA-64C-A01) .040(1.02)01A TYP .09012.29) 71012.79) Zoooccse oO | Tt oe oe | oe oo 1,020125.91) 90012286) |° © ee 1,050126.67) REF oo oe INDEX AREA\\ oe ec | oo oo LI aaa. + l@ e200 002 oO [oreo TYP 3510.89) 1,050126.67) 21015.33)) 2013.05) WAX “150(3.81) Dimensions in inches (mollimeters) 3:53 ;