MAXQ7666 MAXIM | Alldatasheet
Document overview
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Technical content
Features
o High-Performance, Low-Power, 16-Bit RISC Core 8MHz Operation, Approaching 1MIPS per MHz Low Power (< 3mA/MIPS, DVDD = +3.3V) 16-Bit Instruction Word, 16-Bit Data Bus
33 Instructions (Most Require Only One Clock Cycle)
Three Independent Data Pointers with Automatic Increment/Decrement o Program and Data Memory 16KB (8K x 16) Program Flash Up to 512 Bytes (256 x 16) Data Flash
512 Bytes (256 x 16) RAM
o Smart Analog Peripherals Low-Power, Eight Differential-Channel, 12-Bit, 500ksps ADC PGA, Software-Selectable Gain: 1V/V, 2V/V, 4V/V, 8V/V, 16V/V, 32V/V 12-Bit DAC with Buffered Voltage Output External References for ADC and DAC Internal (Die) and External Diode Temperature Sensing o Timer/Digital I/O Peripherals Full CAN 2.0B Controller
15 Message Centers (256-Byte Dual Port Memory)
Programmable Bit Rates from 10kbps to 1Mbps Standard 11-Bit or Extended 29-Bit Identification Modes Two Data Masks and Associated IDs for DeviceNET™, SDS, and Other Higher Layer CAN Protocols External Transmit Disable for Autobaud SIESTA Low-Power Mode Wake-Up on CANRXD Edge Transition UART (LIN) with User-Programmable Baud Rate 16 x 16 Hardware Multiplier with 48-Bit Accumulator, Single Clock-Cycle Operation Three 16-Bit (or Six 8-Bit) Programmable Timer/Counter/PWM Eight General-Purpose, Digital I/Os, with External Interrupt Capability Wake-Up Capable Interrupts o Crystal/Clock Module Internal Oscillator for Use with External Crystal Internal RC Oscillator Eliminates External Crystal External Clock-Source Operation Programmable Watchdog Timer o Power-Management Module Power-On Reset (POR) Power-Supply Supervisor/Brownout Detection for Digital I/O and Digital Core Supplies On-Chip +3.3V, 50mA Linear Regulator o JTAG Interface Extensive Debug and Emulation Support In-System Test Capability Flash-Memory-Program Download Software Bootstrap Loader for Flash Programming o Low-Power Consumption Low-Power Stop Mode (CPU Shutdown) MAXQ7666 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ is a registered trademark of Maxim Integrated Products, Inc. DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc. Ordering Information and Pin Configuration appear at end of data sheet. 19-4257; Rev 0; 8/08 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of a ny device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DV Digital Inputs/Outputs to DGND, AGND, or GNDIO Analog Inputs/Outputs to DGND, AGND, or GNDIO RESET, XIN, XOUT to DGND, AGND, or GNDIO Continuous Power Dissipation (TA = +70°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Safe mode (RC/2 = 3.8MHz) 2.7 3.3 3.6DVDD Normal mode 3.0 3.3 3.6 AVDD 4.75 5.0 5.25Supply Voltage Range DVDDIO 4.75 5.0 5.25 V Shutdown (Note 2) 0.1 10 µAAVDD Supply Current I AVDD All analog functions enabled 6.7 8 mA ADC enabled, fADC = 1ksps, fSYSCLK = 8MHz 4.2 ADC enabled, fADC = 500ksps, fSYSCLK = 8MHz 1890 DAC enabled (zero scale) 305 Internal temperature sensor enabled 502 Additional current when one or more of the ADC, DAC, and/or temperature sensor is enabled (only counted once) 151 µAAnalog Module Subfunction Incremental Supply Current PGA enabled 4.5 mA CPU in stop mode, all peripherals disabled 160 225 µA High-speed mode (Note 3) 28DVDD Supply Current I DVDD Flash erase or write mode 25 35 mA DVDD supervisor and brownout monitor 2 High-frequency crystal oscillator 700DVDD Module Subfunction Incremental Supply Current Internal RC oscillator 200 µA All digital I/Os static at GND or DVDDIO 10DVDDIO Supply Current I DVDDIO (Note 4) 1000 µA
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MEMORY SECTION Program Flash Total Size P r og r am fl ash i s accessed as 16- b i t w or d s1 6K B Program Flash Page Size 64 Bytes Page erase 4Program Flash Erase Size Erase all 256 Pages Using utility ROM function programFlashWritePage: must erase full two pages and rewrite entire page to change any values on that page Program Flash Programming Size Using JTAG boot loader protocol command to load code (family 90h and D0h): must erase full two pages and rewrite two pages Pages Program Flash Erase/ Programming Cell Endurance 10,000 Cycles Program Flash DVDD Supply Voltage Erasing, programming, or fetching instructions 3.0 3.3 3.6 V Page erase 24 30Program Flash Erase Timing Entire flash 240 300 ms Page program 2.2 2.75Program Flash Programming Timing Full program flash program 575 704 ms Program Flash Data Retention T A = +85°C 15 Years Data Flash Total Size Data flash is accessed as 16-bit words (Note 5) 512 Bytes Data Flash Page Size 2 Bytes
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Page erase using utility ROM function dataFlashPageErase 2 Page erase using utility ROM function dataFlashPageEraseEven 1Data Flash Erase Size Erase all 256 Pages Using utility ROM function dataFlashWritePage: must erase full two pages and rewrite entire page to change any values on that page Data Flash Programming Size Using utility ROM function dataFlashWritePageEven: must erase one even page and rewrite entire page to change any values on that page Pages Data Flash Erase/Write Cell Endurance 10,000 Cycles Data Flash DVDD Supply Voltage Erasing, writing, or reading 3.0 3.3 3.6 V Page erase 24 30Data Flash Erase Timing Entire flash 240 300 ms Page write (1 x 16) 73 90 µs 64 x 16 4.7 5.8Data Flash Programming Timing Full data flash write 256 x 16 18.7 23 ms Data Flash Data Retention T A = +85°C 15 Years RAM Data Retention Voltage 2 V Data RAM Memory Size 512 Bytes Utility ROM Size 8192 Bytes
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG SENSE PATH Resolution N ADC No missing codes 12 Bits Gain = 1, bipolar mode, VIN = ±2500mV, 500ksps ±0.5 ±4.0 Gain = 8, unipolar mode, VIN = +400mV, 142ksps ±2.0 Gain = 16, bipolar mode, VIN = ±156mV, 142ksps ±2.0 ±4.0 Integral Nonlinearity INL ADC Gain = 32, bipolar mode, VIN = ±50mV, 142ksps ±2.0 LSB Gain = 1, bipolar, VIN = ±2500mV, 500ksps ±1.0 Gain = 16, bipolar, VIN = ±156mV, 142ksps ±1.0Differential Nonlinearity DNL ADC All other gain settings ±0.6 LSB Offset Error Input referred ±3.2 ±5 mV Offset-Error Temperature Coefficient ±8 µV/°C Zero-Code Error Bipolar, differential measurement of error for ideal ADC output of 0x000 ±3.2 mV Gain Error Exclude offset and reference error -1.0 +1.0 % Gain-Error Temperature Coefficient ±8.5 ppm/°C Signal-to-Noise Plus Distortion SINAD PGA gain = 1V/V -71 dB Total Harmonic Distortion THD PGA gain = 1V/V -85 dB Spurious-Free Dynamic Range SFDR PGA gain = 1V/V -91 dB Input referred, gain = 1 0.2Noise Input referred, gain = 32 3.6 LSBRMS ADC Convert Start Pulse Width Minimum pulse width on P0.4/ADCCNV or a timer port when triggering the ADC 1 ADC CLK Conversion Clock Frequency f ADCCLK fSYSCLK = 8MHz 0.5 8.0 MHz PGA gain = 1V/V, RSOURCE ≤ 1kΩ 500 Sample Rate f SAMPLE Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ 142 ksps
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Conversion Time t CONV tACQ plus 13 ADCCLK cycles at 8MHz tACQ + 1.625 µs PGA gain = 1V/V, RSOURCE ≤ 1kΩ 2Channel/Gain Select Plus Conversion Time Any P GA g ai n setti ng > 1V /V , RS OU R C E ≤ 5kΩ 7 µs PGA gain = 1V/V, RSOURCE ≤ 1kΩ 375 ns Track-and-Hold Acquisition Time t ACQ Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ 5µ s Turn-On Time t RECOV 5µ s Aperture Delay 30 ns Aperture Jitter 50 ps P-P PGA gain = 1V/V 0 AV DD PGA gain = 2V/V 0 1.6 PGA gain = 4V/V 0 0.8 PGA gain = 8V/V 0 0.4 PGA gain = 16V/V 0 0.2 Unipolar mode PGA gain = 32V/V 0 0.1 PGA gain = 1V/V -VREFADC +VREFADC PGA gain = 2V/V -VREFADC +VREFADC PGA gain = 4V/V -VREFADC +VREFADC PGA gain = 8V/V -VREFADC /16 +VREFADC /16 PGA gain = 16V/V -VREFADC /32 +VREFADC /32 Input Voltage Range Bipolar mode PGA gain = 32V/V -VREFADC /64 +VREFADC /64 V Absolute Input Voltage Range AGND AV DD V Input Leakage Current AIN15–AIN0 ±20 nA PGA gain = 1V/V 180 PGA gain = 2V/V 140 PGA gain = 4V/V 120 PGA gain = 8V/V 100 PGA gain = 16V/V 82 Small-Signal Bandwidth (-3dB) V IN x gain = 100mVP-P PGA gain = 32V/V 80 MHz
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PGA gain = 1V/V 180 PGA gain = 2V/V 140 PGA gain = 4V/V 120 PGA gain = 8V/V 100 PGA gain = 16V/V 82 Large-Signal Bandwidth (-3dB) V IN x gain = 3.2VP-P PGA gain = 32V/V 80 MHz PGA gain = 1V/V 13.6 PGA gain = 2V/V 2 PGA gain = 4V/V 4 PGA gain = 8V/V 8 PGA gain = 16V/V 16 Input Capacitance Differential to AGND, any input of AIN0–AIN15 PGA gain = 32V/V 32 pF Crosstalk Between Channels AIN15–AIN0, VIN = 1VP-P, 10kHz, RSOURCE = 5kΩ -80 dB Input Common-Mode Rejection Ratio CMRR AIN15–AIN0 (bipolar, differential), VCM = 100mV to 4.5V 70 88 dB Power-Supply Rejection Ratio PSRR AV DD = +4.75V to +5.25V 67 72 dB DAC SECTION (DACOUT, RL = 5kΩ and CL = 100pF) Resolution N DAC Guaranteed monotonic 12 Bits Differential Nonlinearity DNL DAC Codes 147h to E68h ±0.4 ±1 LSB Integral Nonlinearity INL DAC Codes 147h to E68h ±0.5 ±4 LSB Offset Error Reference to code 040h ±2.5 ±30 mV Offset-Error Temperature Coefficient ±5 µV/°C Gain Error Excludes reference error, tested at E68h ±3 ±20 LSB Gain-Error Temperature Coefficient Excludes offset and reference drift; calculated from FSR ±2 ppm of FSR/°C DAC Output Range No load 0 V REFDAC V DAC enabled 0.5 ΩDC Output Impedance Z OUT Termination resistance to AGND P ow er - d ow n m od e 105 k Ω Output Slew Rate 400h to C00h code swing, rising or falling 0.6 V/µs Output Settling Time 147h to E68h code swing, settling to ±0.5 LSB (Note 6) 81 5µ s Short to AGND 27Output Short-Circuit Current Short to AVDD -46 mA
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC Glitch Impulse From 7FFh to 800h 12 nV ·s DAC Power-On Time Excluding reference, settling to ±0.5 LSB 14 µs Power-Supply Rejection AV D D step fr om + 4.75V to + 5.25V, cod e = E 66h 62 µV/V Output Noise C L = 200pF 200 µV RMS EXTERNAL REFERENCE INPUTS REFADC Input Voltage Range 1.0 AV DD V REFDAC Input Voltage Range 0 AV DD V REFDAC Input Impedance 200 k Ω REFADC Leakage Current ADC disabled 1 µA TEMPERATURE SENSOR (Remote NPN Transistor 2N3904) TA = +25°C ±1 TA = -30°C to +85°C ±2Internal diode TA = -40°C to +125°C ±5 TA = +25°C, TRJ = +25°C ±2 TA = -30°C to +85°C, TRJ = +25°C ±3 TA = -40°C to +125°C, TRJ = +25°C ±3 TA = -30°C to +85°C, TRJ = -30°C to +85°C ±3 Temperature Error External diode, differential configuration (Note 7) TA = -40°C to +125°C, TRJ = -40°C to +125°C ±5 Internal (Die) or External Temperature Measurement Error vs. VREFADC Variation 0.095 °C/mV High level 74.7External Diode Source Current Low level 4 µA E xter nal D i od e D r i ve C ur r ent Rati o 18.7:1 Conversion Time fADCCLK = fSYSCLK = 8MHz, no interrupts, internal utility ROM tempConv 70 µs Temperature Resolution 12-bit ADC 0.125 °C/LSB +3.3V LINEAR REGULATOR (CDVDD = 4.7µF) DVDDIO Input Voltage Range 4.25 5.0 5.25 V DVDD Output Voltage REGEN = GNDIO 3.0 3.4 3.6 V DVDD Input Voltage Range REGEN = DVDDIO 3.0 3.6 V No-Load Quiescent Current C P U i n sl eep m od e; al l d i g i tal p er i p her al s d i sab l ed , no exter nal l oad , REGEN = GNDIO 175 250 µA Output Short-Circuit Current Short to DGND 110 mA
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLY VOLTAGE SUPERVISORS AND BROWNOUT DETECTION DVDD Voltage-Supervisor Reset Rising Threshold Power-on default, DVDD voltage rising (Note 8) 2.70 2.99 V VDBR = 00b (default) 2.70 2.99 VDBR = 01b 2.77 3.06 VDBR = 10b 2.84 3.13 DVDD Voltage-Supervisor Brownout Reset Falling Threshold VVDBR DVDD voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 9) VDBR = 11b 2.91 3.20 V VDBI = 00b (default) 2.77 2.99 VDBI = 01b 2.84 3.13 VDBI = 10b 2.91 3.20 Software-Selectable DVDD Voltage-Supervisor Brownout Interrupt Falling Threshold VVDBI DVDD voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 10) VDBI = 11b 2.99 3.27 V VIOBI = 00b (default) 4.25 4.74 VIOBI = 01b 4.30 4.79 VIOBI = 10b 4.35 4.84 DVDDIO Voltage-Supervisor Brownout Interrupt Threshold VVIOBI DVDDIO voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 11) VIOBI = 11b 4.40 4.89 V Voltage-Supervisor Hysteresis DV DD, DVDDIO 1% DVDD Brownout-Interrupt to Brownout Reset Falling Threshold Voltage difference between VVDBI and VVDBR, time allowing software clean-up before RESET asserted, VDBI = 11b and VDBR = 10b 155 mV Voltage Monitor Supply Voltage Range DVDD 1.0 3.6 V DVDD Ramp-Up Rate Ensure DVDD rises faster than this rate between +2.7V and +3.0V when using either an external DVDD supply or the internal linear regulator 35 mV/ms RESET Hold Time After DVDD rises above the VVDBR voltage trip threshold 10 ms CAN INTERFACE CAN Baud Rate CANCLK = 8MHz 1 Mbps CANCLK Mean Frequency Error 50ppm external crystal error, 8MHz crystal 60 ppm CANCLK Total Frequency Error 50ppm external crystal error, 8MHz crystal, clock divided and measured over 500µs interval, mean plus peak cycle jitter < 0.5 % HIGH-FREQUENCY CRYSTAL OSCILLATOR Using external crystal 7.6 8.12Clock Frequency External clock source 7.6 8.12 MHz
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Crystal Oscillator Startup Time 8MHz crystal 10 ms External Clock Input Duty Cycle Ratio high-to-low or low-to-high 45 55 % Crystal Oscillator Stability Excluding crystal 3 ppm/V HFIC = 00b (default) 7 HFIC = 01b 18 HFIC = 10b 27XIN Input Load Capacitance HFIC = 11b 34 pF HFIC = 00b (default) 7 HFIC = 01b 18 HFIC = 10b 27XOUT Output Load Capacitance HFIC = 11b 34 pF HFOC = 00b (default), ESR = 240Ω 62 HFOC = 01b, ESR = 240Ω 95 HFOC = 10b, ESR = 240Ω 13Crystal Oscillator Drive Strength HFOC = 11b, ESR = 240Ω 23 µW XIN Input Low Voltage Driven with external clock source 0.3 x DVDD V XIN Input High Voltage Driven with external clock source 0.7 x DVDD V INTERNAL RC OSCILLATOR Oscillator Frequency 7.0 7.6 8.0 MHz Oscillator Startup Time 10 µs Oscillator Jitter 2.7 ns UART (LIN) INTERFACE (UTX, URX) UART Baud Rate 2 Mbps Minimum LIN Mode Operation 1 kbps Maximum LIN Mode Operation 20 kbps Crystal clock source -0.5 +0.5 U si ng i nter nal RC osci l l ator b efor e autob aud -14.0 +14.0UART Baud Rates Error Using internal RC oscillator after autobaud -0.5 +0.5 RESET (RESET) RESET Internal Pullup Resistance Pullup to DV DD 305 k Ω High, RESET deasserted, no load 0.9 x DVDDRESET Output Voltage Low, RESET asserted, no load 0.4 V RESET Input High Voltage 0.7 x DVDD V RESET Input Low Voltage 0.3 x DVDD V
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (P0._, CANRXD, URX, REGEN) Input Low Voltage 0.3 x DVDDIO V Input High Voltage 0.7 x DVDDIO V Input Hysteresis 500 mV Input Leakage Current V IN = GNDIO or DVDDIO, pullup disabled -1 ±0.01 +1 µA Input Pullup Resistance Pullup to DV DDIO 400 k Ω Input Capacitance V IN = GNDIO or DVDDIO 15 pF DIGITAL OUTPUTS (P0._, CANTXD, UTX) Output Low Voltage I SINK = 1.6mA 0.4 V Output High Voltage I SOURCE = 1.6mA D V D D I O - 0.5 V Output Leakage Current I/Os three-stated -1 ±0.01 +1 µA Output Capacitance I/Os three-stated 15 pF Short to DVDDIO = +5.25V -29Output Short-Circuit Current Short to GNDIO 28 mA Note 1: All devices are 100% production tested at TA = +25°C. Note 2: All analog functions disabled and all digital inputs connected to DVDDIO or GNDIO. Note 3: High-speed mode: CPU and three timers running at 8MHz from an external crystal oscillator, CAN enabled and communi- cating at 500kbps, all other peripherals disabled, all digital I/Os static at DVDDIO or GNDIO. Note 4: CAN transmitting at 500kbps, one timer output at 500kHz, all active I/Os are loaded with 20pF capacitor, all remaining digi- tal I/Os are at DVDDIO or GNDIO. Note 5: Utility ROM software supports a range of data flash sizes up to 256 x 16 (512 bytes). Refer to the MAXQ7665/MAXQ7666 User’s Guidefor details. Note 6: Guaranteed by design and characterization. Note 7: Based on diode ideality factor of 1.008. Note 8: DVDD must rise above V VDBR for RESET to become deasserted. Caution: Operation is not guaranteed for DV DD below +2.7V (utility ROM) or +3.0V (flash). Note 9: RESET is asserted if DVDD falls below VVDBR. Caution: Operation is not guaranteed for DV DD below +2.7V (utility ROM) or +3.0V (flash). Note 10: An interrupt is generated if DV DD falls below V VDBI. Caution: Operation is not guaranteed for DV DD below +2.7V (utility ROM) or +3.0V (flash). Note 11: An interrupt is generated if DV DDIO falls below V VIOBI. Caution: Operation is not guaranteed if DV DDIO or AVDD is below 4.75V, except for the DV DDIO brownout monitor and +3.3V linear regulator, that still operate down to 0V and +4.25V, respectively.
DACOUT OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT MAXQ7666 toc09 IOH (mA) VOH (V) 4312 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.5 5.4 4.0 VREFDAC = +5V OUTPUT CODE = FFFh MAXQ7666 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) PO._ OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT MAXQ7666 toc01 IOH (mA) VOH (V) 8642 01 0 TA = +125°C TA = -40°C TA = +85°C TA = +25°C PO._ OUTPUT LOW VOLTAGE vs. SINK CURRENT MAXQ7666 toc02 IOL (mA) VOL (V) 8642 0.5 1.0 1.5 2.0 2.5 3.0 01 0 TA = -40°C TA = +125°C TA = +25°C TA = +85°C DAC INL vs. INPUT CODE (VREFDAC = +5V) MAXQ7666 toc03 DIGITAL INPUT CODE INL (LSB) 300020001000 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 -0.5 0 4000 DAC DNL vs. INPUT CODE (VREFDAC = +5V) MAXQ7666 toc04 DIGITAL INPUT CODE DNL (LSB) 300020001000 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 -0.5 0 4000 DAC OFFSET VOLTAGE vs. TEMPERATURE MAXQ7666 toc05 TEMPERATURE (°C) OFFSET VOLTAGE (mV) 1109580655035205-10-25 0.5 1.0 1.5 2.0 2.5 -40 125 DAC GAIN ERROR vs. TEMPERATURE MAXQ7666 toc06 TEMPERATURE (°C) GAIN ERROR (LSB) 1109580655035205-10-25 3.0 4.0 2.5 3.5 2.0 -40 125 DAC OFFSET ERROR vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc07 AVDD SUPPLY VOLTAGE (V) DAC OFFSET ERROR (mV) 5.155.054.954.85 1.5 1.6 1.7 1.8 1.4 4.75 5.25 VREFDAC = +4.75VVREFDAC = AVDD DAC GAIN ERROR vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc08 AVDD SUPPLY VOLTAGE (V) DAC GAIN ERROR (LSB) 5.155.054.954.85 2.5 3.0 3.5 4.0 2.0 4.75 5.25 VREFDAC = AVDD VREFDAC = +4.75V
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) DACOUT OUTPUT LOW VOLTAGE vs. SINK CURRENT MAXQ7666 toc10 IOL (mA) VOL (V) 4312 0.1 0.2 0.3 0.5 0.4 VREFDAC = +5V OUTPUT CODE = 000h DACOUT LARGE-SIGNAL STEP RESPONSE (CODE 000h TO FFFh) MAXQ7666 toc11 DACOUT 4µs/div (1V/div) VREFDAC = +5V ADC INL vs. OUTPUT CODE (VREFADC = +5V, 142ksps, PGA GAIN = 16V/V) MAXQ7666 toc12 DIGITAL OUTPUT CODE ADC INL (LSB) 10240-1024 -1.0 -0.5 0.5 1.0 1.5 -1.5 -2048 2048 BIPOLAR MODE VIN = -156mV TO +156mV ADC DNL vs. OUTPUT CODE (VREFADC = +5V, 142ksps, PGA GAIN = 16V/V) MAXQ7666 toc13 DIGITAL OUTPUT CODE ADC DNL (LSB) 10240-1024 -0.8 -0.6 0.2 0.4 -0.4 -0.2 0.6 0.8 1.0 -1.0 -2048 2048 BIPOLAR MODE VIN = -156mV TO +156mV ADC/PGA OFFSET ERROR (GAIN = 16V/V) vs. TEMPERATURE MAXQ7666 toc14 TEMPERATURE (°C) OFFSET ERROR (mV) 1109565 80-10 5 20 35 50-25 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -40 125 ADC/PGA GAIN ERROR (GAIN = 16V/V) vs. TEMPERATURE MAXQ7666 toc15 TEMPERATURE (°C) GAIN ERROR (% FSR) 1109580655035205-10-25 0.2 0.4 0.6 -0.8 -0.6 -0.4 -0.2 0.8 1.0 -1.0 -40 125 ADC BIPOLAR ZERO-CODE ERROR vs. TEMPERATURE MAXQ7666 toc15b TEMPERATURE (°C) ZERO-CODE ERROR (mV) 1109580655035205-10-25 0.1 0.2 0.3 0.4 0.5 0.6 -40 125 ADC/PGA OFFSET ERROR (GAIN = 16V/V) vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc16 AVDD (V) OFFSET ERROR (mV) 5.155.054.954.85 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4.75 5.25 VREFADC = AVDD VREFDAC = +4.75V ADC/PGA GAIN ERROR (GAIN = 16V/V) vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc17 AVDD (V) GAIN ERROR (% FSR) 5.155.054.954.85 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -1.0 4.75 5.25 VREFADC = AVDD VREFDAC = +4.75V
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) INTERNAL DIODE TEMPERATURE-SENSOR ERROR vs. TEMPERATURE MAXQ7666 toc18 TEMPERATURE (°C) ERROR (ACTUAL - REPORTED °C) 1109565 80-10 5 20 35 50-25 -40 125 EXTERNAL DIODE TEMPERATURE-SENSOR ERROR vs. TEMPERATURE MAXQ7666 toc19 TEMPERATURE (°C) ERROR (ACTUAL - REPORTED °C) 1109565 80-10 5 20 35 50-25 -40 125 DVDD, RESET POWER-UP CHARACTERISTICS MAXQ7666 toc21 10ms/div DVDD (1V/div) RESET (2V/div) DVBR[1:0] = 00 MAXIMUM DVDD TRANSIENT DURATION vs. BOR THRESHOLD OVERDRIVE MAXQ7666 toc23 DVDD BOR THRESHOLD OVERDRIVE (mV) MAXIMUM TRANSIENT DURATION (µs) 10010 100 200 300 400 500 600 700 800 900 1000 11 0 0 0 BOR ASSERTED ABOVE THIS LINE MAXIMUM DVDD TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE MAXQ7666 toc24 DVDD BOI THRESHOLD OVERDRIVE (mV) MAXIMUM TRANSIENT DURATION (µs) 10010 100 200 300 400 500 600 700 800 900 1000 1 1000 BROWNOUT INTERRUPT (BOI) ASSERTED ABOVE THIS LINE MAXIMUM DVDDIO TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE MAXQ7666 toc25 DVDDIO BOI THRESHOLD OVERDRIVE (mV) MAXIMUM TRANSIENT DURATION (μs) 10010 100 200 300 400 500 600 700 800 900 1000 1 1000 BROWNOUT INTERRUPT ASSERTED ABOVE THIS LINE EXTERNAL TEMPERATURE-SENSOR ERROR DUE TO CAPACITIVE LOADING MAXQ7666 toc20 CAPACITIVE LOAD BETWEEN AIN0 AND AIN1 (nF) TEMPERATURE-SENSOR ERROR (°C) 20155 10 02 5 ADC/PGA ZERO-CODE ERROR (GAIN = 16V/V) vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc17b AVDD (V) ZERO-CODE ERROR (mV) 5.155.054.954.85 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 4.75 5.25 VREFADC = AVDDVREFADC = +4.75V BIPOLAR MODE DVDD, RESET POWER-DOWN CHARACTERISTICS MAXQ7666 toc22 10ms/div DVDD (1V/div) RESET (2V/div) DVBR[1:0] = 00
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) DVDD BOR THRESHOLD VOLTAGE vs. TEMPERATURE MAXQ7666 toc26 TEMPERATURE (°C) VDVDD-BOR (V) 1109565 80-10 5 20 35 50-25 2.81 2.82 2.83 2.84 2.85 2.86 2.87 2.88 2.89 2.90 2.80 -40 125 DVBR[1:0] = 00 REGEN = DVDDIO DVDD BOI THRESHOLD VOLTAGE vs. TEMPERATURE MAXQ7666 toc27 TEMPERATURE (°C) VDVDD-BOI (V) 1109565 80-10 5 20 35 50-25 2.86 2.87 2.88 2.89 2.90 2.91 2.92 2.93 2.94 2.95 2.85 -40 125 DVBI[1:0] = 00 REGEN = DVDDIO DVDDIO BOI THRESHOLD VOLTAGE vs. TEMPERATURE MAXQ7666 toc28 TEMPERATURE (°C) VDVDDIO-BOI (V) 1109565 80-10 5 20 35 50-25 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.35 -40 125 VIOBI[1:0] = 00 DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. DVDDIO SUPPLY VOLTAGE MAXQ7666 toc29 DVDDIO SUPPLY VOLTAGE (V) DVDD (V) 5.04.53.5 4.0 2.0 2.5 3.5 1.5 3.0 4.0 1.0 3.0 5.5 REGEN = GNDIO CPU IN STOP MODE ILOAD = 0mA ILOAD = 25mA ILOAD = 50mA DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. TEMPERATURE MAXQ7666 toc30 TEMPERATURE (°C) DVDD (V) 92-7 26 59 3.44 3.42 3.46 3.48 3.50 3.40 -40 125 ILOAD = +25mA REGEN = GNDIO CPU IN STOP MODE DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT MAXQ7666 toc31 LOAD CURRENT (mA) DVDD (V) 40302010 3.45 3.50 3.55 3.60 3.40 05 0 STOP MODE REGEN = GNDIO TA = +85°C TA = +125°C TA = -40°C TA = +25°C DVDD LINEAR REGULATOR OUTPUT VOLTAGE LINE-TRANSIENT RESPONSE (DVDDIO = +4.75V TO +5.25V STEP) MAXQ7666 toc32 100µs/div DVDD (10mV/div) AC-COUPLED DVDDIO (200mV/div) +4.75V OFFSET REGEN = GNDIO ILOAD = 25mA DVDD LINEAR REGULATOR OUTPUT VOLTAGE LOAD-TRANSIENT RESPONSE (IDVDD = 0 TO 50mA STEP) MAXQ7666 toc33 200µs/div DVDD (100mV/div) AC-COUPLED ILOAD (50mA/div) REGEN = GNDIO TA = +25°C TA = -40°C VDROPOUT = DVDDIO - DVDD, WHEN DVDDIO IS REDUCED BELOW +5V UNTIL DVDD DROPS BY 100mV. TA = +85°C TA = +125°C DVDD LINEAR REGULATOR DROPOUT VOLTAGE vs. LOAD CURRENT MAXQ7666 toc34 LOAD CURRENT (mA) VDROPOUT (mV) 20 4010 30 100 200 300 400 500 600 700 05 0 REGEN = GNDIO
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) RC OSCILLATOR OUTPUT FREQUENCY vs. TEMPERATURE MAXQ7666 toc35 TEMPERATURE (°C) FREQUENCY (MHz) 5-25 20-10 7.45 7.50 7.55 7.60 7.65 7.70 7.40 -40 80 50 9565 11035 125 DVDD = +3.3V REGEN = DVDDIO RC OSCILLATOR OUTPUT FREQUENCY vs. DVDD SUPPLY VOLTAGE MAXQ7666 toc36 DVDD (V) FREQUENCY (MHz) 3.33.0 7.45 7.50 7.55 7.60 7.65 7.70 7.40 2.7 3.6 REGEN = DVDDIO DVDD ACTIVE SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE MAXQ7666 toc37 DVDD (V) IDVDD (mA) 3.33.0 2.7 3.6 SEE NOTE 3 AFTER ELECTRICAL CHARACTERISTICS TABLE. FLASH ERASE/PROGRAM HIGH-SPEED MODE DVDD ACTIVE SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc38 TEMPERATURE (°C) IDVDD (mA) 26 59 92-7 -40 125 SEE NOTE 3 AFTER ELECTRICAL CHARACTERISTICS TABLE. FLASH ERASE/PROGRAM HIGH-SPEED MODE DVDD STOP-MODE SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE MAXQ7666 toc39 DVDD SUPPLY VOLTAGE (V) IDVDD (µA) 154 152 156 158 160 150 2.7 3.6 REGEN = DVDDIO CPU IN STOP MODE ALL PERIPHERALS DISABLED BOR DISABLED BOR ENABLED DVDD STOP-MODE SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc40 TEMPERATURE (°C) IDVDD (µA) 925926-7 180 190 160 170 140 150 130 200 120 -40 125 REGEN = DVDDIO CPU IN STOP MODE ALL PERIPHERALS DISABLED BOR DISABLED BOR ENABLED AVDD ACTIVE SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc41 AVDD SUPPLY VOLTAGE (V) IAVDD (mA) 4.95 5.154.85 5.05 5.2 5.4 5.6 5.8 6.0 5.0 4.75 5.25 ALL ANALOG FUNCTIONS ENABLED CONTINUOUS CONVERSION AVDD ACTIVE SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc42 TEMPERATURE (°C) IAVDD (mA) 26 92-7 59 5.2 5.4 5.6 5.8 6.0 5.0 -40 125 ALL ANALOG FUNCTIONS ENABLED CONTINUOUS CONVERSION AVDD SHUTDOWN SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc43 AVDD SUPPLY VOLTAGE (V) IAVDD (nA) 4.95 5.154.85 5.05 0.2 0.4 0.6 0.8 1.0 4.75 5.25 ALL ANALOG FUNCTIONS DISABLED
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) AVDD SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc44 TEMPERATURE (°C) IAVDD (nA) 26 92-7 59 0.1 100 1000 0.01 -40 125 ALL ANALOG FUNCTIONS DISABLED DVDDIO DYNAMIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE MAXQ7666 toc45 DVDDIO SUPPLY VOLTAGE (V) IDVDDIO (µA) 5.1255.0004.875 125 150 175 200 100 4.750 5.250 CAN COMMUNICATING AT 500kbps ONE TIMER OUTPUT AT 500kHz ALL ACTIVE I/O LOADED WITH 20pF CAPACITORS DVDDIO DYNAMIC SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc46 TEMPERATURE (°C) IDVDDIO (µA) 1109565 80-10 5 20 35 50-25 125 150 175 200 100 -40 125 CAN COMMUNICATING AT 500kbps ONE TIMER OUTPUT AT 500kHz ALL ACTIVE I/O LOADED WITH 20pF CAPACITORS DVDDIO STATIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE MAXQ7666 toc47 DVDDIO (V) IDVDDIO (nA) 5.1255.0004.875 150 100 200 250 300 4.750 5.250ALL DIGITAL I/O STATIC REGEN = DVDDIO DVDDIO STATIC SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc48 TEMPERATURE (°C) IDVDDIO (nA) 1109565 80-10 5 20 35 50-25 100 150 200 250 300 -40 125 ALL DIGITAL I/O STATIC REGEN = DVDDIO PGA DISABLED AUTOMATIC SHUTDOWN OFF PGA DISABLED AUTOMATIC SHUTDOWN ON AUTOMATIC SHUTDOWN MAX SAMPLING RATE AVDD SUPPLY CURRENT vs. ADC SAMPLING RATE MAXQ7666 toc49 fADC (ksps) IAVDD (mA) 10 100 0.5 1.0 1.5 2.0 2.5 1 1000 PGA ENABLED AUTOMATIC SHUTDOWN OFF PGA ENABLED AUTOMATIC SHUTDOWN ON AVDD SUPPLY CURRENT vs. ADC SAMPLING RATE (PGA ENABLED) MAXQ7666 toc50 fADC (ksps) IAVDD (mA) 10 100 1 1000 SAMPLING ERROR vs. INPUT SOURCE IMPEDANCE MAXQ7666 toc51 SOURCE IMPEDANCE (kΩ) SAMPLING ERROR (LSB) 1 100 PGA GAIN = 32V/V
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Pin Description PIN NAME FUNCTION 1 AIN11 Analog Input Channel 11. AIN11 is multiplexed to the PGA as a differential input with AIN10. 2 AIN10 Analog Input Channel 10. AIN10 is multiplexed to the PGA as a differential input with AIN11. 3 AIN9 Analog Input Channel 9. AIN9 is multiplexed to the PGA as a differential input with AIN8. 4 AIN8 Analog Input Channel 8. AIN8 is multiplexed to the PGA as a differential input with AIN9. 5, 8 AGND Analog Ground. Connect all AGND nodes together. Connect to DGND at a single point. 6 REFADC ADC External Reference Input. Connect an external reference voltage between 1V and AVDD to REFADC. 7 REFDAC DAC External Reference Input. Connect an external reference voltage between 0V and AVDD to REFDAC. 9 AIN7 Analog Input Channel 7. AIN7 is multiplexed to the PGA as a differential input with AIN6. 10 AIN6 Analog Input Channel 6. AIN6 is multiplexed to the PGA as a differential input with AIN7. 11 AIN5 Analog Input Channel 5. AIN5 is multiplexed to the PGA as a differential input with AIN4. 12 AIN4 Analog Input Channel 4. AIN4 is multiplexed to the PGA as a differential input with AIN5. 13 AIN3 Analog Input Channel 3. AIN3 is multiplexed to the PGA as a differential input with AIN2. AIN3–AIN0 have external temperature sensor capability. 14 AIN2 Analog Input Channel 2. AIN2 is multiplexed to the PGA as a differential input with AIN3. AIN3–AIN0 have external temperature sensor capability. 15 AIN1 Analog Input Channel 1. AIN1 is multiplexed to the PGA as a differential input with AIN0. AIN3–AIN0 have external temperature sensor capability. 16 AIN0 Analog Input Channel 0. AIN0 is multiplexed to the PGA as a differential input with AIN1. AIN3–AIN0 have external temperature sensor capability. 17 DACOUT DAC Buffer Output. DACOUT is the DAC voltage buffer output. 18, 19, 31 DGND Digital Ground for the Digital Core and Flash. Connect all DGND nodes together. Connect to AGND at a single point. 20 CANRXD CAN Bus Receiver Input. Control area network receiver input. 21 CANTXD CAN Bus Transmitter Output. Control area network transmitter output.
22 UTX UART or LIN Transmitter Output
23 URX UART or LIN Receiver Input
24 P0.6/T0 Port 0 Bit 6/Timer 0. P0.6 is a general-purpose digital I/O with interrupt/wake-up input capability. T0 is a primary timer/PWM input or output. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 7 and 8. 25 P0.7/T1 Port 0 Bit 7/Timer 1. P0.7 is a general-purpose digital I/O with interrupt/wake-up input capability. T1 is a primary timer/PWM input or output. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 7 and 8. 26, 39 DV DDIO Digital I/O Supply Voltage. Supplies all digital I/O except for XIN, XOUT, and RESET. Bypass DVDDIO to GNDIO with a 0.1µF capacitor placed as close as possible to the device. DVDDIO also connects to the input of the linear regulator. 27 GNDIO Digital I/O Ground. Connect all grounds together at a single point. 30 I.C. Internal Connection. Leave unconnected or connect to DV DDIO.
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Pin Description (continued) PIN NAME FUNCTION 32 P0.0/TDO Port 0 Data 0/JTAG Serial Test Data Output. P0.0 is a general-purpose digital I/O with interrupt/wake-up capability. TDO is the JTAG serial test, data output. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. 33 P0.1/TMS Port 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wake- up capability. TMS is the JTAG test mode select input. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. 34 P0.2/TDI Port 0 Data 2/JTAG Serial Test Data Input. P0.2 is a general-purpose digital I/O with interrupt/wake-up capability. TDI is the JTAG serial test, data input. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. 35 P0.3/TCK Port 0 Data 3/JTAG Serial Test Clock Input. P0.3 is a general-purpose digital I/O with interrupt/wake-up capability. TCK is the JTAG serial test, clock input. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. 36 P0.4/ADCCNV P or t 0 D ata 4/AD C S tar t C onver si on C ontr ol . P 0.4 i s a g ener al - p ur p ose d i g i tal I/O w i th i nter r up t/w ake- up cap ab i l i ty. AD C C N V i s fi r m w ar e confi g ur ab l e for a r i si ng or fal l i ng ed g e star t/conver t to tr i g g er AD C conver si ons. Refer to the M AX Q 7665/M AX Q7666 U ser ’ s G ui d e secti ons 3 and 8. 37 P 0.5/D AC LOAD P or t 0 D ata 5/D AC D ata Reg i ster Load /U p d ate Inp ut. P 0.5 i s a g ener al - p ur p ose d i g i tal I/O w i th i nter r up t/w ake- up cap ab i l i ty. D AC LOAD i s fi r m w ar e confi g ur ab l e for a r i si ng or fal l i ng ed g e to up d ate the D AC O U T r eg i ster . Refer to the M AX Q7665/M AX Q 7666 U ser ’ s Gui d e secti ons 3 and 8. 38 REGEN Active-Low Linear Regulator Enable Input. Connect REGEN to GNDIO to enable the linear regulator. Connect REGEN to DVDDIO to disable the linear regulator.
40 DV DD
D i g i tal S up p l y V ol tag e. D V DD sup p l i es the i nter nal d i g i tal cor e and fl ash m em or y. D V DD i s i nter nal l y connected to the outp ut of the i nter nal 3.3V l i near r eg ul ator . D i sab l e the i nter nal r eg ul ator to connect D V DD to an exter nal sup p l y. W hen usi ng the on- chi p l i near r eg ul ator , b yp ass D V DD to D GN D w i th a 4.7µF ± 20% cap aci tor w i th a m axi m um E S R of 0.5Ω . In ad d i ti on, b yp ass D V DD w i th a 0.1µF cap aci tor . P l ace b oth b yp ass cap aci tor s as cl ose as p ossi b l e to the d evi ce.
41 RESET
Reset Input and Output. Active-low open-drain input/output with internal 305kΩ (typ) pullup to DVDD. Drive low to reset the µC. RESET is low during power-up reset and during DVDD brownout conditions.
42 XOUT
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation. Leave XOUT unconnected if XIN is driven with an external clock source. XOUT is not driven when using the internal RC oscillator.
43 XIN
High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for normal operation, or drive XIN with an external clock source. XIN is not driven when using the internal RC oscillator.
44 AV DD
Analog Supply Voltage Input. Connect AVDD to a +5V supply. Bypass AVDD to AGND with a 0.1µF capacitor placed as close as possible to the device. 45 AIN15 Analog Input Channel 15. AIN15 is multiplexed to the PGA as a differential input with AIN14. 46 AIN14 Analog Input Channel 14. AIN14 is multiplexed to the PGA as a differential input with AIN15. 47 AIN13 Analog Input Channel 13. AIN13 is multiplexed to the PGA as a differential input with AIN12. 48 AIN12 Analog Input Channel 12. AIN12 is multiplexed to the PGA as a differential input with AIN13. — EP Exposed Pad. EP is internally connected to AGND. Connect EP to AGND externally.
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Block Diagram REFADC 17:1 MUX 12-BIT ADC 12-BIT DAC SOFTWARE- INTERRUPT CONTROLLER DVDDIO BROWNOUT MONITOR I/O BUFFERS 1:2 CURRENT DEMUX 9:1 MUX DACREF AIN0 AIN1 AIN2 AIN3 TSE ADCMX0 AIN4 AIN5 AIN13 AIN12 AIN11 AIN10 AIN14 AIN15 AIN1 AIN3 AIN5 AIN7 AIN9 AIN11 AIN13 AIN15 ADCMX[3.0] HFFINT EIFO UARTI DVBI T0I T1I T2I CANSTI CANERI VIBE AGND VIOBI TEMPERATURE SENSORS INTERNAL IINT ADCMX3 ADCCLK ADCE ADCRY ADCOV GNDIO DVDDIO DACE DACE R R DACOUT REFDAC P0.6/T0 P0.7/T1 P0.4/ADCCNV P0.5/DACLOAD UTX URX UART INTERFACE TIMER2/PWM2 (2 x 8 BITS OR 1 x 16 BITS) PORT 0 I/O REGISTERS TIMER1/PWM1 (2 x 8 BITS OR 1 x 16 BITS) TIMER0/PWM0 (2 x 8 BITS OR 1 x 16 BITS) T2CLK T2I T1CLK T1I T0CLK T0I UARTI WATCHDOG TIMERHFRCCLK EWT 8KB UTILITY ROM 16-BIT MAXQ20 RISC CPU 256 x 16 DATA FLASH
512 BYTES
+3.3V LINEAR REGULATOR DVDD POWER-ON- RESET/ BROWNOUT MONITOR HF CLOCK PRESCALER ADC CLOCK PRESCALER CAN CLOCK PRESCALER JTAG INTERFACE PORT 0 I/O REGISTERS I/O BUFFERS M U X M U X GNDIO HF XTAL OSC. HFRCCLK TIMER CLOCK PRESCALERS XHFE RCE INT HF R-C OSC SYSCLK SYSCLK XHFRY HFFINT 2:1 DGND 16 x 16 HW MULTIPLY CAN 2.0B INTERFACE I/O BUFFERSCANSTI CANERI GNDIO CANCLK CANTXD CANRXD GNDIO DVDDIO DVDD DGND P0.3/TCK P0.1/TMS P0.2/TDI P0.0/TDO DVDDIO REGEN DVDD XOUT GNDIO DGND XIN AGND WDI DVBIVDPE VDBE DVDD RESET AVDD EXTERNAL TEMP-SENSE DIODE CURRENT DRIVE DVDD WTR CANCLK ADCCLK T0CLK T1CLK T2CLK AIN6 AIN7 AIN8 AIN9 DGND GAIN = x1, x2, x4, x8, x16, x32 PGAPGAE PD0 PO0 PI0 EIF0 HFCLK DVDDIO ADCREF MAXQ7666 8K x 16 PROGRAM FLASH
and two power-supply supervisors. through a PGA. See Figure 1.
1 TO 32
12 DATA
Figure 1. Simplified Analog Input Diagram (Eight Fully Differential Inputs)
AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15. and does not use any analog input channel. more detailed information on the ADC and mux. tial) or one analog input and AGND (single -ended). Figures 3 and 4 illustrate these two configurations. Figure 2. Simplified DAC Diagram
Figure 5. DVDD Brownout Interrupt Detection begins at the reset vector (8000h in the utility ROM). tor’s input voltage is falling.
remains above the POR threshold.
- If DV DD remains below the BOR threshold, the RESET pin remains low, and the µC remains in the reset state.
- If DV DD stops falling before reaching the POR threshold, then begins rising above the BOR thresh- old, the RESET pin is released and the µC jumps to the reset vector (8000h in the utility ROM). This is similar to the DV DD power-up case described in the previous scenario, except there is no power-up counter delay and some of the register bits are set to BOR values rather than POR values. See Tables 3 and 5 for the reset behavior of specific bits. In par- ticular, the retained VDBR setting, if higher than the default value of 00b, allows a potentially more robust brownout recovery closer to or above the minimum flash operating level of +3.0V.
- If DV DD falls below the 1.2V POR threshold, all regis- ter bits are reset, and any DV DD recovery from that point is identical to the power-up case described above. See Tables 3 and 5 for the reset behavior of specific bits. Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed programming information, and a more thor- ough description of POR and brownout behavior. Internal 3.3V Linear Regulator An internal +3.3V/50mA linear regulator provides alter- nate supply to the MAXQ7666 core logic if an external supply is not used. Connect REGEN to GNDIO to enable the linear regulator. When using the linear regu- lator, ensure the DV DDIO supply can support both the I/O and digital supply current requirements. Connect REGEN to DV DDIO when using a +3.3V external sup- ply. Apply DV DDIO before DV DD when using external supply for DVDD. System Clock Generator The MAXQ7666 oscillator module is the master clock generator that supplies the system clock for the µC core and all of the peripheral modules using either a crystal oscillator or an internal RC oscillator. The crystal oscillator operates with an 8MHz crystal. Use the RC oscillator in applications that do not require precise tim- ing. The MAXQ7666 executes most instructions in a single SYSCLK period. The oscillator module contains all of the primary clock-generation circuitry. Figure 6 shows a block diagram of the system clock module. The MAXQ7666 supports many features for generating a master clock signal timing source:
- Internal, fast-starting, 7.6MHz RC oscillator elimi- nates external crystal
- Internal high-frequency oscillator that can drive an external 8MHz crystal
- External high-frequency clock input (8MHz)
- Selectable internal capacitors for high-frequency crystal oscillator
- Power-up timer
- Fail-safe modes Watchdog Timer The primary function of the watchdog timer is to watch for stalled or stuck software. The watchdog timer per- forms a controlled system restart when the µP fails to write to the watchdog timer register before a selectable timeout interval expires. In some designs, the watchdog timer is also used to implement a real-time operating system (RTOS) in the µC. When used to implement an RTOS, a watchdog timer typically has four objectives: 1) To detect if a system is operating normally 2) To detect an infinite loop in any of the tasks 3) To detect an arbitration deadlock involving two or more tasks 4) To detect if some lower priority tasks are not running because of higher priority tasks CD0 SYSCLKMUX HFRCCLK CLOCK DIVIDE HF XTAL OSC RC OSC XIN XOUT XT EXTHFRCE HFE
Figure 6. Crystal and RC Oscillator Block Diagram
Figure 10. CAN 0 Controller Block Diagram of a second message into message center 15.
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System message, before accepting an incoming message. This feature allows the CAN unit to directly support the use of higher CAN protocols, which make use of the first and/or second byte of data as a part of the accep- tance layer for storing incoming messages. Program each message center independently to perform testing of the incoming data with or without the use of the glob- al masks. Global controls and status registers in the CAN unit allow the µC to evaluate error messages, validate new data and the location of such data, establish the bus timing for the CAN bus, establish the identification mask bits, and verify the source of individual mes- sages. In addition, each message center is individually equipped with the necessary status and controls to establish directions, interrupt generation, identification mode (standard or extended), data field size, data sta- tus, automatic remote frame request and acknowledg- ment, and masked or nonmasked identification acceptance testing. UART Interface Use the 8051-style universal synchronous/asynchro- nous receiver/transmitter (UART) capable of interfacing with a LIN transceiver for serial interfacing. Figure 11a shows the UART block diagram in synchronous mode and Figure 11b shows asynchronous mode. The UART allows the device to conveniently communicate with other RS-232 interface-enabled devices, as well as PCs and serial modems when paired with an external RS- 232 line driver/receiver. The UART can detect framing errors and indicate the condition through a user-acces- sible software bit. The time base of the serial port is derived from either a division of the system clock or the dedicated baud clock generator. The UART is capable of supporting LIN protocol implementation in software when using one of the timers for autobaud detection. Table 1 summarizes the operating characteristics as well as the maximum baud rate of each mode. Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed UART information. DIVIDE BY 12 LOAD CLOCK OUTPUT SHIFT REGISTER S0 LATCH RECEIVE DATA BUFFER WR SBUF0 RD D0CLOCK RECEIVE SHIFT REGISTER SI BAUD CLOCK LOAD SERIAL BUFFER RECEIVE BUFFER DATA CLOCK SERIAL I/O CONTROL INTS SHIFT READ SERIAL TI FLAG = SCON0.1 RI FLAG = SCON0.0 DIVIDE BY 4 LDSBUF RDSBUF SBUF0 UTX OUTPUT SYSCLK URX INPUT SERIAL INTERRUPT DATA BUS Figure 11a. UART Synchronous Mode (Mode 0)
Table 1. UART Operating Characteristics and Mode Baud Rate
as transmit-and-receive data buffers for a debugger. to form an active serial path. 1/8 of the system clock frequency for proper operation.
- TDO—Serial output signal for test instruction and data. Data transitions on the falling edge of TCK. TDO idles high when inactive. TDO serially trans- fers internal data to the external host. Data trans- fers least significant bit first.
- TDI—Serial input signal for test instruction and data. Transition data on the rising edge of TCK. TDI pulls high when unconnected. TDI serially transfers data from the external host to the internal TAP mod- ule shift registers. Data transfers least significant bit first.
- TCK—Serial clock for the test logic. When TCK stops at 0, storage elements in the test logic must retain their data indefinitely. Force TCK high when inactive.
76543210 S 1 S 0
Figure 12. JTAG Interface Block Diagram
- TMS—Test Mode Selection. The rising edge of TCK samples the test signal at TMS. The TAP controller decodes the test signal at TMS to control the test operation. Force TMS high when inactive. General-Purpose Digital I/Os The MAXQ7666 provides eight general-purpose digital I/Os (GPIOs). All GPIOs have an additional special function (SF), such as a timer input/output, or TAP sig- nal for JTAG communication. For example, the state of P0.6/T0 can be programmed to depend on timer chan- nel 0 logic. When programmed as a port, each I/O is configurable for high-impedance or weak pullup to DV DDIO. At power-up, each GPIO is configured as an input with pullups to DV DDIO. In addition, each GPIO can cause an externally triggered interrupt on falling or rising edges. Any externally triggered interrupt can wake up the device from stop mode. The data input/output direction in a port is independent- ly controlled by the port direction register (PD). Each I/O within the port is individually set as an output or input. The port output register (PO) contains the current state of the logic output buffers. When an I/O is config- ured as an output, writing to the PO register controls the output logic state. Reading the PO register shows the current state of the output buffers, independent of the data direction. The port input register (PI) is a read- only register that always reflects the logic state of the I/Os. When an I/O is configured as an input, writing to the PO register enables/disables the pullup resistor. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information. Port Characteristics The MAXQ7666 contains one GPIO port (P0). It is a bidirectional 8-bit I/O port, which contains the following features:
- Schmitt trigger input circuitry with software-selec- table high-impedance or weak pullup to DV DDIO
- Software-selectable push-pull CMOS output drivers capable of sinking and sourcing 1.6mA
- Software-selectable open-drain output drivers capa- ble of sinking 1.6mA
- Falling or rising edge interrupt capability
- All I/Os contain an additional special function, such as a logic input/output for a timer channel. Selecting an I/O for a special function alters the port characteristics of that I/O (refer to the MAXQ7665/MAXQ7666 User’s Guide for more details). Figure 13 illustrates the func- tional blocks of an I/O. MUX FLAG PD0._ SF DIRECTION SF ENABLE PO0._ SF OUTPUT PI0._ OR SF INPUT EIEO._ EIES._ INTERRUPT FLAG DETECT CIRCUIT MUX DVDDIO DVDDIO I/O PAD GNDIO 400kΩ PD PO P0._ MAXQ7666
Figure 13. Digital I/O Circuitry
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ Core Architecture The MAXQ7666 is structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations complete in one cycle without pipelining, because the instruction contains both the operation code and data. The result is a streamlined 8 million instructions-per-second (MIPS) µC. A 16-level hardware stack supports the highly efficient core, enabling fast subroutine calling and task switch- ing. Manipulate data quickly and efficiently with three internal data pointers. Multiple data pointers allow more than one function to access data memory without hav- ing to save and restore data pointers each time. The data pointers automatically increment or decrement fol- lowing an operation, eliminating the need for software intervention. As a result, application speed is greatly increased. Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca- tions. The highly orthogonal instruction set allows arith- metic and logical operations to use any register along with the accumulator. Special-function registers (also called peripheral registers) control the peripherals and are subdivided into register modules. The architecture is transport-triggered. Writes or reads from certain register locations potentially cause side effects. These side effects form the basis for the higher level opera- tion codes defined by the assembler, such as ADDC, OR, JUMP, etc. The operation codes are implemented as MOVE instructions between certain register locations, while the assembler handles the encoding. Memory Organization The MAXQ7666 incorporates several memory areas:
- 8KB (4K x 16) utility ROM
- 16KB (8K x 16) program flash memory for program storage
- 256B (128 x 16) data flash memory
- 512 bytes (256 x 16) of SRAM for storage of temporary variables
- 16-level stack memory for storage of program return addresses and general-purpose use The memory is arranged by default in a Harvard archi- tecture, with separate address spaces for program and data memory (see Figure 14). A special mode allows data memory mapping into program space, permitting code execution from data memory. Another mode allows program memory mapping into data space, permitting access to code constants as data memory. The flash memory allows reprogramming the devices, eliminating the expense of throwing away one-time pro- grammable devices during development and field upgrades (see Figure 15 for the flash memory sector maps). Password protect flash memory with a 16-word key to deny access to program memory by unautho- rized individuals. A pseudo-Von Neumann memory map places the utility ROM, code, and data memory into a single contiguous memory map. This is useful for applications that require dynamic program modification or unique memory con- figurations. Stack Memory A 16-bit-wide x 16 deep internal hardware stack pro- vides storage for program return addresses and gener- al-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. The stack also explicitly stores and retrieves data by using the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI opera- tions retrieve the value at SP and then decrement SP.
Figure 14. MAXQ7666 Memory Map
- In-system programming (bootstrap loader) over JTAG
- In-circuit debug routines
- User-callable routines for in-application flash pro- gramming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the spe- cial routines mentioned. Access routines within the utili- ty ROM as subroutines by the application software. More information on the utility ROM contents is con- tained in the MAXQ7665/MAXQ7666 User’s Guide. Some applications require protection against unautho- rized viewing of program code memory. For these applications, access to in-system programming, in- application programming, or in-circuit debugging func- tions is prohibited until a password is supplied. The password is defined as the 16 words of physical pro- gram memory at addresses 0010h to 001Fh. A single password lock (PWL) bit is implemented in the SC register. When the PWL is set to one (POR default), the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memo- ry. When PWL is cleared to zero, these utilities are fully accessible without the password. The password is automatically set to all ones following a mass erase. When the password is all ones or all zeros, the PWL bit clears to zero.
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Programming Program the flash memory of the µC using two different methods: in-system programming and in-application programming. Both methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. Password protect these features to prevent unauthorized access to program memory. In-System Programming An internal bootstrap loader programs the device over a simple JTAG interface. This allows in-system soft- ware upgrading, eliminating the need for costly hard- ware retrofit when updates are required. Remote software uploading of physically inaccessible applica- tions are possible. After a power-up or reset, the JTAG interface is active and loading the TAP with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstrap-loader-mode program that resides in the utility ROM. When programming is complete, the boot- strap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. The following bootstrap loader functions are supported:
- Load
- Dump
- CRC
- Verify
- Erase In-Application Programming The in-application programming feature allows the µC to modify its own flash program memory while simulta- neously executing its application software. This allows on-the-fly software updates in mission-critical applica- tions that cannot afford downtime. Alternatively, it allows the application to develop custom loader soft- ware that can operate under the control of the appli- cation software. The utility ROM contains user-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the MAXQ7665/MAXQ7666 User’s Guidefor this device. Program/Data Flash and Data RAM Memory The MAXQ7666 provides the following memory configu- rations (see Figure 15):
- 16KB (8K x 16) of program flash
- Up to 512 bytes (256 x 16) of data flash
- 512 bytes (256 x 16) of data RAM The program flash is divided into 256 pages. Each page contains 64 bytes (32 x 16-bit words). Program flash is erased four pages (128 x 16 = 256 bytes) at a time, and must be programmed a full page (32 x 16 = 64 bytes) at a time from the application code (see Figure 17). Both erase and programming operations are performed by calling built-in utility ROM functions programFlashErasePage and programFlashWritePage (see Figure 19). When programmed over JTAG, the built-in boot loader supports commands to program flash two pages (128 bytes) at a time. The data flash is divided into 256 pages. Each page contains 2 bytes (1 x 16-bit word). A typical data flash configuration is erased two pages (2 x 16 = 4 bytes) at a time using the utility ROM function dataFlashPageErase, and is written one page/word (1 x 16-bit word = 2 bytes) at a time using the utility ROM function dataFlashWrite. It is also possible to write and read from only even data flash addresses using the utility ROM functions dataFlashWriteEven and dataFlashReadEven. The even functions make it possible to work around the asymmet- ric "erase two, write one" page behavior by writing to only even addresses. By putting data into alternate loca- tions, the intrinsic two-page erase function is made to look like a single word erase at the cost of halving the available storage. Figure 16 shows the data flash mem- ory organization for one page and two page write/erase operations. Refer to the MAXQ7665/MAXQ7666 User’s Guide for all possible configurations. Note that the data flash is under application control only through the utility ROM functions discussed in this section and is not available when programmed over JTAG. Register Set Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and address- ing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU,
Figure 15. Memory Organization
1 PAGE WRITE)
2 PAGE ERASE
1 PAGE PROGRAM
1 PAGE ERASE
Figure 16. Two of the Possible Data Flash Organizations
4 PAGE ERASE
Figure 17. Program Flash Organization
different products based on the MAXQ architecture. Power consumption reaches its minimum in stop mode. tor, system clock, and all processing activity is halted. RC oscillator while the warmup period completes. Table 2. System Register Map
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Interrupts Multiple interrupt sources quickly respond to internal and external events. The MAXQ architecture uses a sin- gle interrupt vector (IV), single interrupt-service routine (ISR) design. Enable interrupts globally, individually, or by module. When an interrupt condition occurs, its indi- vidual flag is set, even if the interrupt source is disabled at the local, module, or global level. Clear interrupt flags within the user-interrupt routine to avoid repeated false interrupts from the same source. Application soft- ware must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two- instruction delay. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user pro- gram must determine whether a jump to 0000h came from a reset or interrupt source. Once software control transfers to the ISR, use the interrupt identification register (IIR) to determine if a system register or peripheral register was the source of the interrupt. The specified module can then be interro- gated for the specific interrupt source and software can take appropriate action. The following interrupt sources are available.
- Watchdog interrupt
- External interrupts 0 to 7
- Serial port 0 receive and transmit interrupts
- Timer 0 low compare, low overflow, capture/compare, and overflow interrupts
- Timer 1 low compare, low overflow, capture/compare, and overflow interrupts
- Timer 2 low compare, low overflow, and overflow interrupts
- CAN0 receive and transmit interrupts and a change in CAN0 status register interrupt
- ADC data ready and overrun interrupts
- Digital and I/O voltage brownout interrupts
- Crystal oscillator failure interrupt Reset Sources Several reset sources are provided for µC control. Although code execution is halted in the reset state, the crystal oscillator, and the internal RC oscillator continue to oscillate. The crystal oscillator is turned off by a POR, but not by other reset sources. Internal resets such as the power-on and watchdog resets assert the RESET output low. Power-On Reset (POR) An internal POR circuit enhances system reliability. This circuit forces the device to perform a POR whenever a rising voltage on DV DD climbs above the POR thresh- old level of 2.7V. At this point the following events occur:
- All registers and circuits enter the default state
- The POR flag (WDCN.POR) is set to indicate if the source of the reset was a loss of power
- The internal RC oscillator becomes the clock source
- Code execution begins at location 8000h Watchdog Timer Reset The watchdog timer functions are described in the MAXQ7665/MAXQ7666 User’s Guide. Execution resumes at location 8000h following a watchdog timer reset.
Assert the external RESET input low to enter the reset state. The external reset functions are described in the MAXQ7665/MAXQ7666 User’s Guide . Execution resumes at location 8000h after RESET is released. Crystal Selection The MAXQ7666 requires a crystal with the following specifications: Frequency: 8MHz C LOAD: 6pF (min) Drive level: 5µW (min) Series resonance resistance: 300Ω max Note: Series resonance resistance is the resistance observed when the resonator is in the series resonant condition. This is a parameter often stated by quartz crystal vendors and is called R1. When a resonator is used in the parallel resonant mode with an external load capacitance, as is the case with the MAXQ7666 oscilla- tor circuit, the effective resistance is sometimes stated. This effective resistance at the loaded frequency of oscil- lation is: R1 x ( 1 + (C O/CLOAD))2 For typical C O and C LOAD values, the effective resis- tance can be greater than R1 by a factor of 2. Development and Technical Support A variety of highly versatile, affordably priced develop- ment tools for this µC are available from Maxim and third-party suppliers. These tools include:
- Compilers
- Evaluation kits
- JTAG-to-serial converters for programming and debugging A list of some development-tool vendors can be found at www.maxim-ic.com/microcontrollers Technical support is available through email at maxq.support@maxim-ic.com. MAXQ7666 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System
Table 3. System Register Bit Functions and Reset Values MAXQ7665/MAXQ7666 User’s Guide for more information.
Table 4. Peripheral Register Map Note: Names that appear in bold indicate that the register is read-only.
Table 5. Peripheral Register Bit Functions and Reset Values
Table 5. Peripheral Register Bit Functions and Reset Values (continued)
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System 2N3904 TEMPERATURE SENSOR R+dr R-dr R-dr R+dr ~2nF OUTA- OUTA+ VBRIDGEA DUAL-BRIDGE SENSOR VBRIDGEB GNDA GNDB ~2nF ~2nF OUTB- OUTB+ ~2nF R+dr R-dr R-dr R+dr R+dr R-dr R-dr R+dr ~2nF OUTA- OUTA+ VBRIDGEA DUAL-BRIDGE SENSOR VBRIDGEB GNDA GNDB ~2nF ~2nF OUTB- OUTB+ ~2nF R+dr R-dr R-dr R+dr MAX5024 LDO +12V (+5V) EXTERNAL RESET IS OPTIONAL 10µF +3.3V EN HOLD GND IN OUT SET RESET LIN TRANSCEIVER MAX13050 CAN TRANSCEIVER 8MHz P0.7/T1 P0.6/T0 DIGITAL I/OP0.5/DACLOAD P0.4/ADCCNV P0.3/TCK DACOUT AGND P0.2/TDI JTAGP0.1/TMS P0.0/TD0 REGEN DVDD CANRXD CANTXD GNDIO AGND XOUT XIN RESET DVDDIO AVDD REFDAC REFADC DGND AIN0 AIN2 12-BIT ADC 12-BIT DAC PGA MUX AIN4 AIN6 AIN8 AIN10 AIN12 AIN14 AIN1 AIN3 MUX AIN5 AIN7 AIN9 AIN11 AIN13 AIN15 UART (LIN 2.0) CAN 2.0B MAXQ20 16-BIT RISC MICRO 16KB PROGRAM FLASH 512B DATA FLASH +5V +12V LIN RXD RXD STBY MAXQ7666 UTX URX Typical Operating Circuit
16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. Chip Information PROCESS: BiCMOS and CMOS Pin Configuration TOP VIEW TQFN 7mm x 7mm + 13 AIN3 AIN2 AIN1 AIN0 DACOUT DGND DGND CANRXD CANTXD UTX URX P0.6/TO 123456789 1 0 1 1 1 2 AIN12 AIN13 AIN14 AIN15 AV DD XIN XOUT RESET DVDD DVDDIO REGEN P0.5/DACLOAD AIN4 AIN5 AIN6 AIN7 AGND REFDAC REFADC AGND AIN8 AIN9 AIN10 AIN11 36 35 34 33 32 31 30 29 28 27 26 25 P0.7/T1 DVDDIO GNDIO I.C. I.C. I.C. DGND P0.0/TDO P0.1/TMS P0.2/TDI P0.3/TCK P0.4/ADCCNV MAXQ7666BATM *EXPOSED PAD *CONNECT EXPOSED PAD TO AGND. PART TEMP RANGE PIN-PACKAGE MAXQ7666BATM+ -40°C to +125°C 48 TQFN-EP*
Ordering Information
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.