MAXQ612

MAXQ612_1 MAXIM | Alldatasheet

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Technical content

Features

S High-Performance, Low-Power, 16-Bit RISC Core S DC to 12MHz Operation Across Entire Operating Range S 1.70V to 3.6V Operating Voltage S Can Be Powered from Battery (VDD) or USB (VDDB) S 33 Total Instructions for Simplified Programming S Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement S Dedicated Pointer for Direct Read from Code Space S 16-Bit Instruction Word, 16-Bit Data Bus S 16 x 16-Bit General-Purpose Working Registers S Secure MMU for Application Partitioning and IP Protection S Memory Features 128KB Flash Memory 512-Byte Sectors 20,000 Erase/Write Cycles per Sector 6KB Data SRAM S USB Features (MAXQ622 Only) USB 2.0 Full-Speed Compatible Hardware Receive and Transmit Buffers for High Throughput Integrated Full-Speed Transceiver On-Chip Termination and Pullup Resistors S Additional Peripherals Power-Fail Warning Power-On Reset (POR)/Brownout Reset Automatic IR Carrier Frequency Generation and Modulation Two 16-Bit Programmable Timers/Counters with Prescaler and Capture/Compare Two SPI Communication Ports Two USART Communication Ports I2C Port Programmable Watchdog Timer 8kHz Nanopower Ring Oscillator Wake-Up Timer Up to 56 General-Purpose I/O S Low Power Consumption 0.3µA (typ), 3µA (max) in Stop Mode TA = +25NC, Power-Fail Monitor Disabled 4.8mA (typ) at 12MHz, 520µA (typ) at 1MHz in Active Mode Remote Controls Battery-Powered Portable Equipment Consumer Electronics Home Appliances White Goods +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Note: Bare die versions for most of these devices are available. Contact the factory for availability at https://support.maxim-ic.com/micro. MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. PART TEMP RANGE OPERATING VOLTAGE (V) PROGRAM MEMORY (KB) DATA MEMORY (KB) USB FULL SPEED PIN-PACKAGE MAXQ612J-0000+ 0NC to +70NC 1.7 to 3.6 128 Flash 6 No 44 TQFN-EP* MAXQ612G-0000+ 0NC to +70NC 1.7 to 3.6 128 Flash 6 No 64 LQFP MAXQ622G-0000+ 0NC to +70NC 1.7 to 3.6 128 Flash 6 Yes 64 LQFP

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 TABLE OF CONTENTS

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on Any Lead with Continuous Output Current Voltage Range on DP, DM with RECOMMENDED OPERATING CONDITIONS (VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD VRST 3.6 V 1.8V Internal Regulator VREG18 1.62 1.8 1.98 V Power-Fail Warning Voltage for Supply VPFW Monitors VDD (Notes 2, 3, 4) 1.75 1.8 1.85 V Power-Fail Reset Voltage VRST Monitors VDD (Note 5) 1.64 1.67 1.70 V POR Voltage VPOR Monitors VDD 1.0 1.42 V RAM Data-Retention Voltage VDRV (Note 6) 1.0 V Active Current IDD_1 Sysclk = 12MHz 4.8 5.5 mAIDD_2 Sysclk = 1MHz (Note 6) 0.52 0.8 Stop-Mode Current IS1 Power-Fail Off (Note 7) TA = +25NC 0.3 3 FATA = +70NC 2.8 13 IS2 Power-Fail On TA = +25NC 24 30 TA = +70NC 30 40 Current Consumption During Power Fail IPFR (Notes 6, 8, 9) [(3 x IS2) + ((PCI - 3) x (IS1 + INANO))]/ PCI FA Current Consumption During POR IPOR (Note 10) 100 nA Stop-Mode Resume Time tON 375 + 8192 tHFXIN Fs Power-Fail Monitor Startup Time tPFM_ON (Note 6) 150 Fs Power-Fail Warning Detection Time tPFW (Notes 6, 11) 10 Fs Input Low Voltage for IRTX, IRRX, RESET, and All Port Pins VIL VGND 0.3 x VDD V Input High Voltage for IRTX, IRRX, RESET, and All Port Pins VIH 0.7 x VDD VDD V

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 RECOMMENDED OPERATING CONDITIONS (continued) (VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Hysteresis (Schmitt) VIHYS 300 mV Input Low Voltage for HFXIN VIL_HFXIN External driven clock and not feedback connected crystal oscillator VGND 0.3 x VDD V Input High Voltage for HFXIN VIH_HFXIN External driven clock and not feedback connected crystal oscillator 0.7 x VDD VDD V IRRX Input Filter Pulse-Width Reject tIRRX_R 50 ns IRRX Input Filter Pulse-Width Accept tIRRX_A 300 ns Output Low Voltage for IRTX VOL_IRTX VDD = 3.6V, IOL = 25mA (Note 6) 1.0 VVDD = 2.35V, IOL = 10mA (Note 6) 1.0 VDD = 1.85V, IOL = 4.5mA 1.0 Output Low Voltage for RESET and All Port Pins (Note 12) VOL VDD = 3.6V, IOL = 11mA (Note 6) 0.4 0.5 VVDD = 2.35V, IOL = 8mA (Note 6) 0.4 0.5 VDD = 1.85V, IOL = 4.5mA 0.4 0.5 Output High Voltage for IRTX and All Port Pins VOH IOH = -2mA VDDIO -

0.5 VDDIO V

Input/Output Pin Capacitance for All Port Pins Except DP, DM CIO (Note 6) 15 pF Input Leakage Current IL Internal pullup disabled -100 +100 nA Input Pullup Resistor for RESET, IRTX, IRRX, P0 to P6 RPU VDD = 3V, VOL = VDD/2 (Note 6) 16 25 39 kW VDD = 2V, VOL = VDD/2 17 27 41 VDD = 3.0V, VOL = 0.4V (Note 6) 16 28 39 VDD = 2.0V, VOL = 0.4V (Note 6) 17 30 41 GPIO Supply Output High Voltage VDDIOH VDDIOH current is the sum of VDDIO current and IOH of all GPIO, IOH = 10mA VDD - 0.4 VDD V EXTERNAL CRYSTAL/RESONATOR Crystal/Resonator fHFXIN (Note 13) 1 12 MHz Crystal/Resonator Period tHFXIN 1/fHFXIN ns Crystal/Resonator Warmup Time tXTAL_RDY From initial oscillation 8192 x tHFXIN ms Oscillator Feedback Resistor ROSCF (Note 6) 0.5 1.0 1.5 MW Crystal ESR (Note 6) 60 W EXTERNAL CLOCK INPUT External Clock Frequency fXCLK (Note 13) DC 12 MHz External Clock Period tXCLK 1/fXCLK ns External Clock Duty Cycle tXCLK_DUTY 45 55 % System Clock Frequency fCK fHFXIN MHzHFXOUT = GND fXCLK

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 RECOMMENDED OPERATING CONDITIONS (continued) (VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS System Clock Period tCK 1/fCK ns NANOPOWER RING Nanopower Ring Frequency fNANO TA = +25NC 3 13 20 kHzTA = +25NC, VDD = POR voltage (Note 6) 1.7 2.4 Nanopower Ring Duty Cycle tNANO (Note 6) 40 60 % Nanopower Ring Current INANO Typical at VDD = 1.64V, TA = +25°C (Note 6) 40 400 nA WAKE-UP TIMER Wake-Up Timer Interval tWAKEUP 1/fNANO 65,535/ fNANO s FLASH MEMORY System Clock During Flash Programming/Erase fFPSYSCLK 1 MHz Flash Erase Time tME Mass erase 20 40 mstERASE Page erase 20 40 Flash Programming Time per Word tPROG (Note 14) 20 100 Fs Write/Erase Cycles 20,000 Cycles Data Retention TA = +25NC 100 Years USB USB Supply Voltage VBUS (Note 15) 4.5 5.0 5.5 V VBUS Supply Current (Note 16) IVBUS Transmitting on DP and DM at 12Mbps, CL = 50pF on DP and DM to GND, FRCVDD = 0 13.5 mA Transmitting on DP and DM at 12Mbps, CL = 50pF on DP and DM to GND, FRCVDD = 1 3.5 mA VBUS Supply Current During Idle (Note 16) IVBUSID DP = high, DM = low, FRCVDD = 0 (Note 6) 6 mA DP = high, DM = low, FRCVDD = 1 0.2 mA VBUS Suspend Supply Current IVBUSSUS 500 FA Single-Ended Input High Voltage DP, DM VIHD 2.0 V Single-Ended Input Low Voltage DP, DM VILD 0.8 V Output Low Voltage DP, DM VOLD RL = 1.5kI from DP to 3.6V 0.3 V Output High Voltage DP, DM VOHD RL = 15kI from DP and DM to GND 2.8 V Differential Input Sensitivity DP, DM VDI DP to DM 0.2 V Common-Mode Voltage Range VCM Includes VDI range 0.8 2.5 V

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 RECOMMENDED OPERATING CONDITIONS (continued) (VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Single-Ended Receiver Threshold VSE 0.8 2.0 V Single-Ended Receiver Hysteresis VSEH 200 mV Differential Output Signal Cross-Point Voltage VCRS CL = 50pF (Note 6) 1.3 2.0 V DP, DM Off-State Input Impedance RLZ 300 kW Driver Output Impedance RDRV Steady-state drive 28 44 W DP Pullup Resistor RPU Idle 0.9 1.575 kWReceiving 1.425 3.090 USB TIMING DP, DM Rise Time (Transmit) tR CL = 50pF 4 20 ns DP, DM Fall Time (Transmit) tF CL = 50pF 4 20 ns Rise/Fall Time Matching (Transmit) tR/tF CL = 50pF (Note 6) 90 110 % IR Carrier Frequency fIR fCK/2 Hz SPI (Note 6) SPI Master Operating Frequency 1/tMCK fCK/2 MHz SPI Slave Operating Frequency 1/tSCK fCK/4 MHz SPI I/O Rise/Fall Time tSPI_RF CL = 15pF, pullup = 560W 8 24 ns SCLK_ Output Pulse-Width High/Low tMCH, tMCL tMCK/2 - tSPI_RF ns MOSI_ Output Hold Time After SCLK_ Sample Edge tMOH tMCK/2 - tSPI_RF ns MOSI_ Output Valid to Sample Edge tMOV tMCK/2 - tSPI_RF ns MISO_ Input Valid to SCLK_ Sample Edge Rise/Fall Setup tMIS 25 ns MISO_ Input to SCLK_ Sample Edge Rise/Fall Hold tMIH 0 ns SCLK_ Inactive to MOSI_ Inactive tMLH tMCK/2 - tSPI_RF ns SCLK_ Input Pulse-Width High/Low tSCH, tSCL tSCK/2 ns SSEL_ Active to First Shift Edge tSSE tSPI_RF ns

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 RECOMMENDED OPERATING CONDITIONS (continued) (VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) I2C ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 3.6V, TA = 0NC to +70NC.) (Note 1, Figure 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MOSI_ Input to SCLK_ Sample Edge Rise/Fall Setup tSIS tSPI_RF ns MOSI_ Input from SCLK_ Sample Edge Transition Hold tSIH tSPI_RF ns MISO_ Output Valid After SCLK_ Shift Edge Transition tSOV 50 ns SSEL_ Inactive tSSH tCK + tSPI_RF ns SCLK_ Inactive to SSEL_ Rising tSD tSPI_RF ns MISO_ Output Disabled After SSEL_ Edge Rise tSLH 2tCK + 2tSPI_RF ns PARAMETER SYMBOL CONDITIONS STANDARD MODE FAST MODE UNITSMIN MAX MIN MAX Input Low Voltage VIL_I2C (Note 18) -0.5 0.3 x VDD -0.5 0.3 x VDD V Input High Voltage VIH_I2C (Note 18) 0.7 x VDD 0.7 x VDD VDD + 0.5V V Input Hysteresis (Schmitt) VIHYS_I2C VDD > 2V 0.05 x VDD V Output Logic-Low (Open Drain or Open Collector) VOL_I2C VDD > 2V, 3mA sink cur- rent 0 0.4 0 0.4 V Output Fall Time from VIH_MIN to VIL_MAX with Bus Capacitance from 10pF to 400pF tOF_I2C (Notes 19, 20) 250 20 + 0.1CB 250 ns Pulse Width of Spike Filtering That Must Be Suppressed by Input Filter tSP_I2C 0 50 ns Input Current on I/O IIN_I2C Input voltage from 0.1 x VDD to 0.9 x VDD -10 +10 -10 +10 FA I/O Capacitance CIO_I2C 10 10 pF

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 I2C BUS CONTROLLER TIMING (Notes 6, 21) (Figure 2) Note 1: Specifications to 0NC are guaranteed by design and are not production tested. listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal. Note 3: It is not recommended to write to flash when the supply voltage drops below the power-fail warning levels, as there is uncertainty in the duration of continuous power supply. The user application should check the status of the power-fail warning flag before writing to flash to ensure complete write operations. Note 4: The power-fail warning monitor and the power-fail reset monitor are designed to track each other with a minimum delta between the two of 0.11V. Note 5: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals is active at all times when V DD < VRST, ensuring the device maintains the reset state until minimum operating voltage is achieved. Note 6: Guaranteed by design and not production tested. Note 7: IS1 is measured with the USB data RAM powered down. Note 8: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles. Note 9: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or V DD. Outputs do not source/ sink any current. The device is executing code from flash memory. Note 10: Current consumption during POR when powering up while V DD is less than the POR release voltage. Note 11: The minimum amount of time that V DD must be below VPFW before a power-fail event is detected. Note 12: The maximum total current, IOH(MAX) and IOL(MAX), for all listed outputs combined should not exceed 25mA to satisfy the maximum specified voltage drop. This does not include the IRTX output. Note 13: External clock frequency must be 12MHz to support USB functionality. Full-speed USB(12Mbps)-required bit-rate accu - racy is Q2500ppm or Q0.25%. This is inclusive of all potential error sources: frequency tolerance, temperature, aging, crystal capacitive loading, board layout, etc. Note 14: Programming time does not include overhead associated with utility ROM interface. PARAMETER SYMBOL STANDARD MODE FAST MODE UNITSMIN MAX MIN MAX I2C Bus Operating Frequency fI2C 0 100 0 400 kHz System Frequency fSYS 0.90 3.60 MHz I2C Bit Rate fI2C fSYS/8 fSYS/8 Hz Hold Time After (Repeated) START tHD:STA 4.0 0.6 Fs Clock Low Period tLOW_I2C 4.7 1.3 Fs Clock High Period tHIGH_I2C 4.0 0.6 Fs Setup Time for Repeated START tSU:STA 4.7 0.6 Fs Hold Time for Data (Notes 22, 23) tHD:DAT 0 3.45 0 0.9 Fs Setup Time for Data (Note 24) tSU:DAT 250 100 ns SDA/SCL Fall Time (Note 20) tF_I2C 300 20 + 0.1CB 300 ns SDA/SCL Rise Time (Note 20) tR_I2C 1000 20 + 0.1CB 300 ns Setup Time for STOP tSU:STO 4.0 0.6 Fs Bus Free Time Between STOP and START tBUF 4.7 1.3 Fs Capacitive Load for Each Bus Line CB 400 400 pF Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) VnL_I2C 0.1 x VDD 0.1 x VDD V Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) VnH_I2C 0.2 x VDD 0.2 x VDD V

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 Pin Configurations P0.3/RX1/SDA P0.4/TX1/SCL P0.5/TBA0/TBA1 P0.6/TBB0 P0.7/TBB1 P2.0/MOSI0 P2.1/MISO0 P2.2/SCLK0 P2.3/SSEL0 P0.2/TX0 P0.1/RX0 1 P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 P1.7/INT7 GND IRTX IRRX P0.0/IRTXM P1.2/INT2 P1.1/INT1 P3.2/INT10 P3.1/INT9 P3.0/INT8 HFXOUT HFXIN GND REG18 V DD RESET P3.3/INT11 P3.4/INT1222 P2.6/TMS P2.5/TDI P2.4/TCK GND N.C. N.C. P3.7/INT15 P3.6/INT14 P3.5/INT13 P2.7/TDO P1.0/INT0 TQFN TOP VIEW MAXQ612 + *EP *EXPOSED PAD.

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 Pin Configurations (continued) 38394041424344454647 P4.4 P0.1/RX0 N.C. N.C. P1.0/INT0 P2.7/TDO P2.6/TMS P2.5/TDI P2.4/TCK P5.3/SSEL1 P5.2/SCLK1 P5.1/MISO1 P5.0/MOSI1 N.C. GND P3.7/INT15 P3.6/INT14 P0.0/IRTXM P0.3/RX1/SDA P0.2/TX0 P0.5/TBA0/TBA1 P0.4/TX1/SCL P0.6/TBB0 GND P2.0/MOSI0 P0.7/TBB1 P2.2/SCLK0 P2.1/MISO0 RESET P2.3/SSEL0 N.C. P3.4/INT12 P3.3/INT11 P3.2/INT10 P3.1/INT9 P3.0/INT8 HFXOUT HFXIN GND REG18 VDD 3334353637 N.C. N.C. N.C. N.C. N.C. P4.3 P4.2 P4.1 P4.0 P1.7/INT7 IRTX GND P4.7 P4.6 P4.5 P1.6/INT6 P1.5/INT5 P1.4/INT4 P1.3/INT3 P3.5/INT13P1.2/INT2 P1.1/INT1IRRX 111098765432 16151413121 LQFP TOP VIEW MAXQ612

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 Pin Description Pin Configurations (continued) PIN NAME FUNCTIONMAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP POWER PINS 13 22 22 VDD Supply Voltage 15, 28, 41 8, 24, 35, 8, 17, 24, 35, 63 GND Ground 14 23 23 REG18 Regulator Capacitor. This pin must be connected to ground through a 1.0FF external ceramic-chip capacitor. The capacitor must be placed as close to this pin as possible. No external devices other than the capaci - tor should be connected to this pin. — — — EP Exposed Pad (TQFN Only). Connect EP to the ground plane. 38394041424344454647 P4.4 P0.1/RX0 N.C. N.C. P1.0/INT0 P2.7/TDO P2.6/TMS P2.5/TDI P2.4/TCK P5.3/SSEL1 P5.2/SCLK1 P5.1/MISO1 P5.0/MOSI1 N.C. GND P3.7/INT15 P3.6/INT14 P0.0/IRTXM P0.3/RX1/SDA P0.2/TX0 P0.5/TBA0/TBA1 P0.4/TX1/SCL P0.6/TBB0 GND P2.0/MOSI0 P0.7/TBB1 P2.2/SCLK0 P2.1/MISO0 RESET P2.3/SSEL0 DP P3.4/INT12 P3.3/INT11 P3.2/INT10 P3.1/INT9 P3.0/INT8 HFXOUT HFXIN GND REG18 VDD 3334353637 VDDIO VDDB VBUS DM GND P4.3 P4.2 P4.1 P4.0 P1.7/INT7 IRTX GND P4.7 P4.6 P4.5 P1.6/INT6 P1.5/INT5 P1.4/INT4 P1.3/INT3 P3.5/INT13P1.2/INT2 P1.1/INT1IRRX 111098765432 16151413121 LQFP TOP VIEW MAXQ622

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 Pin Description (continued) PIN NAME FUNCTIONMAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP RESET PINS 12 15 15 RESET Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 4mA. This pin is driven low as an output when an internal reset condition occurs. CLOCK PINS 16 25 25 HFXIN High-Frequency Crystal Input. Connect an external crystal or resona - tor between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external, high-frequency clock source when HFXOUT is shorted to ground during POR.17 26 26 HFXOUT USB FUNCTION PINS — — 19 VBUS USB VBUS Supply Voltage. Connect VBUS to a positive 5.0V power sup - ply. Bypass VBUS to ground with a 1.0FF ceramic capacitor as close to the VBUS pin as possible. — — 16 DP USB D+ Signal. This bidirectional pin carries the positive differential data or single-ended data. Connect this pin to a USB “B” connector. This pin is weakly pulled high internally when the USB is disabled. — — 18 DM USB D- Signal. This bidirectional pin carries the negative differential data or single-ended data. Connect this pin to a USB “B” connector. This pin is weakly pulled high internally when the USB is disabled. — — 20 VDDB USB Transceiver Supply Voltage. This is the power output of the internal voltage regulator that is used for the USB transceiver (3.3V) block. This pin is bypassed to ground with a 1.0 FF capacitor as close as possible to the package. No external circuitry should be powered from this pin. — — 21 VDDIO Switched 3V Power Supply. This is the power output after selection between VBUS and VDD. Must be connected to an external ceramic chip capacitor. The capacitor must be placed as close to this pin as possible. No external devices other than the capacitor should be con - nected to this pin. IR FUNCTION PINS 42 64 64 IRTX IR Transmit Output. Active-low IR transmit pin capable of sinking 25mA. This pin defaults to three-state input with the weak pullup disabled dur - ing all forms of reset. Software must configure this pin after release from reset to remove the three-state input condition. 43 1 1 IRRX IR Receive Input

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 Pin Description (continued) PIN NAME FUNCTIONMAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS P0.0–P0.7; IRTXM, RX0, TX0, RX1, TX1, SDA, SCL, TBA0, TBA1, TBB0, TBB1 General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. All port pins default to three-state mode after a reset. All alternate functions must be enabled from software. MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP PORT SPECIAL FUNCTION 44 2 2 P0.0 IRTXM 1 3 3 P0.1 RX0 2 4 4 P0.2 TX0 3 5 5 P0.3 RX1/SDA 4 6 6 P0.4 TX1/SCL 5 7 7 P0.5 TBA0/TBA1 6 9 9 P0.6 TBB0 7 10 10 P0.7 TBB1 33–40 45, 48–54 45, 48–54 P1.0–P1.7; INT0–INT7 General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins or as inter - rupts. All port pins default to three-state mode after a reset. All interrupt functions must be enabled from software. MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP PORT SPECIAL FUNCTION 33 45 45 P1.0 INT0 34 48 48 P1.1 INT1 35 49 49 P1.2 INT2 36 50 50 P1.3 INT3 37 51 51 P1.4 INT4 38 52 52 P1.5 INT5 39 53 53 P1.6 INT6 40 54 54 P1.7 INT7

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 Pin Description (continued) PIN NAME FUNCTIONMAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP 8–11, 29–32 11–14, 41–44 11–14, 41–44 P2.0–P2.7; MOSI0, MISO0, SCLK0, SSEL0, TCK, TDI, TMS, TDO General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. P2.0 to P2.3 default to three-state mode after a reset. All alternate functions must be enabled from software. Enabling the pin’s special function disables the general-purpose I/O on the pin. The JTAG pins (P2.4 to P2.7) default to their JTAG function with weak pullups enabled after a reset. The JTAG function can be disabled using the TAP bit in the SC register. P2.7 functions as the JTAG test-data output on reset and defaults to an input with a weak pullup. The output function of the test data is only enabled during the TAP’s shift_IR or shift_DR states. MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP PORT SPECIAL FUNCTION 8 11 11 P2.0 MOSI0 9 12 12 P2.1 MISO0 10 13 13 P2.2 SCLK0 11 14 14 P2.3 SSEL0 29 41 41 P2.4 TCK 30 42 42 P2.5 TDI 31 43 43 P2.6 TMS 32 44 44 P2.7 TDO 18–25 27–34 27–34 P3.0–P3.7; INT8–INT15 General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins or as inter - rupts. All port pins default to three-state mode after a reset. All interrupt functions must be enabled from software. MAXQ612 TQFN MAXQ612 LQFP MAXQ622 LQFP PORT SPECIAL FUNCTION 18 27 27 P3.0 INT8 19 28 28 P3.1 INT9 20 29 29 P3.2 INT10 21 30 30 P3.3 INT11 22 31 31 P3.4 INT12 23 32 32 P3.5 INT13 24 33 33 P3.6 INT14 25 34 34 P3.7 INT15

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 Detailed Description The MAXQ612/MAXQ622 provide integrated, low-cost solutions that simplify the design of IR communications equipment such as universal remote controls. Standard features include the highly optimized, single-cycle, MAXQ, 16-bit RISC core; 128KB of flash memory; 6KB data RAM; soft stack; 16 general-purpose registers; and three data pointers. The MAXQ core has the industry’s best MIPS/mA rating, allowing developers to achieve the same performance as competing microcontrollers at substantially lower clock rates. Lower active-mode cur - rent combined with the even lower MAXQ612/MAXQ622 stop-mode current results in increased battery life. IR application-specific peripherals include flexible timers for generating IR carrier frequencies and modulation. A high-current, 25mA, IR drive pin and output pins capable of sinking up to 5mA support IR applications. It also includes a USB slave interface compatible with existing host HID device drivers, I2C, dual SPI, dual USARTs, up to 56 general-purpose I/O pins ideal for keypad matrix input, and a power-fail-detection circuit to notify. Operating from DC to 12MHz, almost all instructions execute in a single clock cycle (83.3ns at 12MHz), enabling nearly 12MIPS true-code operation. When active device opera- tion is not required, an ultra-low-power stop mode can be invoked from software, resulting in quiescent current con- sumption of less than 300nA typical and 3FA maximum. The combination of high-performance instructions and ultra-low Pin Description (continued) PIN NAME FUNCTIONMAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. All port pins default to three-state mode after a reset. MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP PORT SPECIAL FUNCTION — 55 55 P4.0 — — 56 56 P4.1 — — 57 57 P4.2 — — 58 58 P4.3 — — 59 59 P4.4 — — 60 60 P4.5 — — 61 61 P4.6 — — 62 62 P4.7 — — 37–40 37–40 P5.0–P5.3; MOSI1, MISO1, SCLK1, SSEL1 General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. All port pins default to three-state mode after a reset. All alternate functions must be enabled from software. Enabling the pin’s special function disables the general-purpose I/O on the pin. MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP PORT SPECIAL FUNCTION — 37 37 P5.0 MOSI1 — 38 38 P5.1 MISO1 — 39 39 P5.2 SCLK1 — 40 40 P5.3 SSEL1 NO CONNECTION PINS 26, 27 16–21, 36,

ply is low and appropriate action should be taken. sor with performance approaching 1MIPS per MHz. microprocessor used in embedded applications. is supported from any register to any other register. ters with autoincrement/decrement support.

128KB program flash memory
6KB SRAM data memory
6KB utility ROM
Soft stack Memory Protection The optional memory-protection feature separates code memory into three areas: system, user loader, and user application. Code in the system area can be kept con - fidential. Code in the user areas can be prevented from reading and writing system code. The user loader can also be protected from user application code. Memory protection is implemented using privilege levels for code. Each area has an associated privilege level. RAM/ROM are assigned privilege levels as well. Refer to the MAXQ622 User’s Guide for a more thorough expla - nation of the topic. Stack Memory A 16-bit-wide internal stack provides storage for pro - gram return addresses and can also be used for general- purpose data storage. The stack is used automatically by the processor when the CALL, RET, and RETI instruc- tions are executed and when an interrupt is serviced. An application can also store values in the stack explicitly by using the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (BF0h). The CALL, PUSH, and interrupt-vectoring operations decrement SP, then store a value at the loca- tion pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then increment SP. Utility ROM The utility ROM is a 6KB block of internal ROM memory that defaults to a starting address of 8000h. The utility

Table 1. Memory Areas and Associated Maximum Privilege Levels

In-system programming (bootstrap loader) using JTAG interface
In-circuit debug routines
Test routines (internal memory tests, memory loader, etc.)
User-callable routines for in-application flash memory programming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of system code, or to one of the special rou - tines mentioned. Routines within the utility ROM are user accessible and can be called as subroutines by the application software. More information on the utility ROM functions is contained in the MAXQ622 User’s Guide. Some applications require protection against unau - thorized viewing of program code memory. For these applications, access to in-system programming, in- application programming, or in-circuit debugging func - tions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. Three password locks protect three different program memory segments. When the PWL is set to one (power- on reset default) and the contents of the memory at addresses 0010h to 001Fh are any value other than FFh or 00h, the password is required to access the utility ROM, including in-circuit debug and in-system program- ming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without password. The PWLS bit uses a password that is at ULDR + 0010 to ULDR + 001F, and the PWLL uses a password at UAPP + 0010 to UAPP + 001F. The password is automatically set to all ones fol - lowing a mass erase. Watchdog Timer The internal watchdog timer greatly increases system reliability. The timer resets the device if software execu - tion is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the applica- tion software. If software is operating correctly, the coun- ter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. The watchdog timer functions as the source of both the watchdog timer timeout and the watchdog timer reset. The timeout period can be programmed in a range of 215 to 2 24 system clock cycles. An interrupt is gener - ated when the timeout period expires if the interrupt is enabled. All watchdog timer resets follow the pro - grammed interrupt timeouts by 512 system clock cycles. If the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. IR Carrier Generation and Modulation Timer The dedicated IR timer/counter module simplifies low- speed infrared (IR) communication. The IR timer imple - ments two pins (IRTX and IRRX) for supporting IR transmit and receive, respectively. The IRTX pin has no corresponding port pin designation, so the standard PD, PO, and PI port control status bits are not present. However, the IRTX pin output can be manipulated high or low using the PWCN.IRTXOUT and PWCN.IRTXOE bits when the IR timer is not enabled (i.e., IREN = 0).

Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 The IR timer is composed of a carrier generator and a carrier modulator. The carrier generation module uses the 16-bit IR carrier register (IRCA) to define the high and low time of the carrier through the IR carrier high byte (IRCAH) and IR carrier low byte (IRCAL). The carrier modulator uses the IR data bit (IRDATA) and IR modula- tor time register (IRMT) to determine whether the carrier or the idle condition is present on IRTX. Carrier Generation Module The IRCAH byte defines the carrier high time in terms of the number of IR input clocks, whereas the IRCAL byte defines the carrier low time.

IR Input Clock (fIRCLK) = fSYS/2IRDIV[1:0]
Carrier Frequency (f CARRIER) = f IRCLK/(IRCAH + IRCAL + 2)
Carrier High Time = IRCAH + 1
Carrier Low Time = IRCAL + 1
Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2) During transmission, the IRCA register is latched for each IRV downcount interval, and is sampled along with the IRTXPOL and IRDATA bits at the beginning of each new IRV downcount interval so that duty-cycle variation and frequency shifting is possible from one interval to the next. The starting/idle state and the carrier polarity of the IRTX pin can be configured when the IR timer is enabled. IR Transmission During IR transmission (IRMODE = 1), the carrier gen - erator creates the appropriate carrier waveform, while the carrier modulator performs the modulation. The car - rier modulation can be performed as a function of carrier cycles or IRCLK cycles dependent on the setting of the IRCFME bit. When IRCFME = 0, the IRV down counter is clocked by the carrier frequency and thus the modula - tion is a function of carrier cycles. When IRCFME = 1, the IRV down counter is clocked by IRCLK, allowing carrier modulation timing with IRCLK resolution. The IRTXPOL bit defines the starting/idle state as well as the carrier polarity for the IRTX pin. If IRTXPOL = 1, the IRTX pin is set to a logic-high when the IR timer module is enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low when the IR timer is enabled. A separate register bit, IR data (IRDATA), is used to determine whether the carrier generator output is output to the IRTX pin for the next IRMT carrier cycles. When IRDATA = 1, the carrier waveform (or inversion of this waveform if IRTXPOL = 1) is output on the IRTX pin dur - ing the next IRMT cycles. When IRDATA = 0, the idle condition, as defined by IRTXPOL, is output on the IRTX pin during the next IRMT cycles. The IR timer acts as a down counter in transmit mode. An IR transmission starts when the IREN bit is set to 1 when IRMODE = 1; when the IRMODE bit is set to 1 when IREN = 1; or when IREN and IRMODE are both set to 1 in the same instruction. The IRMT and IRCA registers, along with the IRDATA and IRTXPOL bits, are sampled at the beginning of the transmit process and every time the IR timer value reload its value. When the IRV reaches 0000h value, on the next carrier clock, it does the following: 1) Reloads IRV with IRMT. 2) Samples IRCA, IRDATA, and IRTXPOL. 3) Generates IRTX accordingly. 4) Sets IRIF to 1. 5) Generates an interrupt to the CPU if enabled (IRIE = 1). IR Transmit—Independent External Carrier and Modulator Outputs The normal transmit mode modulates the carrier based upon the IRDATA bit. However, the user has the option to input the modulator (envelope) on an external pin if desired. The IRDATA bit is output directly to the IRTXM pin (if IRTXPOL = 0) on each IRV downcount interval boundary just as if it were being used to internally modu- late the carrier frequency. If IRTXPOL = 1, the inverse of the IRDATA bit is output to the IRTXM pin on the IRV interval downcount boundaries. When the envelope mode is enabled, it is possible to output either the modu- lated (IRENV[1:0] = 01b) or unmodulated (INENV[1:0] = 10b) carrier to the IRTX pin. IR Receive When configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX capture function. The IRRXSEL[1:0] bits define which edge(s) of the IRRX pin should trigger the IR timer capture function. Once started, the IR timer (IRV) starts up counting from 0000h when a qualified capture event as defined by IRRXSEL happens. The IRV register is, by default, counting carrier cycles as defined by the IRCA register. However, the IR carrier frequency detect (IRCFME) allows clocking of the IRV register directly with the IRCLK for finer resolution. When IRCFME = 0, the IRCA defined carrier is counted by IRV. When IRCFME = 1, the IRCLK clocks the IRV register. On the next qualified event, it does the following: 1) Captures the IRRX pin state and transfers its value to IRDATA. If a falling edge occurs, IRDATA = 0. If a rising edge occurs, IRDATA = 1.

2) Transfers its current IRV value to the IRMT. 3) Resets IRV content to 0000h (if IRXRL = 1). 4) Continues counting again until the next qualified event. carrier cycles are examined for frequency determination.

16-bit timer/counter
16-bit up/down autoreload
Counter function of external pulse
16-bit timer with capture
16-bit timer with compare
Input/output enhancements for pulse-width modulation
Set/reset/toggle output state on comparator match
Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10) General-Purpose I/O The microcontroller provides port pins for general-pur - pose I/O that have the following features:
CMOS output drivers
Schmitt trigger inputs
Optional weak pullup to V DD when operating in input mode While the microcontroller is in a reset state, all port pins become three-state with both weak pullups and input buffers disabled, unless otherwise noted. From a software perspective, each port appears as a group of peripheral registers with unique addresses. Special function pins can also be used as general-pur - pose I/O pins when the special functions are disabled. For a detailed description of the special functions avail - able for each pin, refer to the IC-specific user’s guide, e.g., the MAXQ622 User’s Guide describes all special functions available on the MAXQ612/MAXQ622. Serial Peripherals The microcontroller supports two independent USARTs, two SPI master/slave communications ports, and an I 2C bus. USART The USART units are implemented with the following characteristics:
2-wire interface
Full-duplex operation for asynchronous data transfers
Half-duplex operation for synchronous data transfers
Programmable interrupt for receive and transmit
Independent baud-rate generator

Table 3. USART Mode Details

Programmable 9th bit parity support
Start/stop bit support Serial Peripheral Interface (SPI) The dual-integrated SPI interfaces provide independent serial communication channels that communicate syn - chronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum SPI master transfer rate is Sysclk/2. When operating as an SPI slave, the MAXQ612/MAXQ622 can support up to Sysclk/4 SPI transfer rate. Data is trans - ferred as an 8-bit or 16-bit value, MSB first. In addition, the SPI module supports configuration of an active SSEL state through the slave active select. Separate pins and registers are used to differentiate between the two SPI ports. I2C Bus The microcontroller integrates an internal I 2C bus mas - ter/slave for communication with a wide variety of other I2C–enabled peripherals. The I 2C bus is a 2-wire, bidi - rectional bus using two bus lines—the serial data line (SDA) and the serial clock line (SCL)—and a ground line. Both the SDA and SDL lines must be driven as open- collector/drain outputs. External resistors are required as shown in Figure 1 to pull the lines to a logic-high state. The device supports both the master and slave proto - cols. In the master mode, the device has ownership of the I2C bus, drives the clock, and generates the START and STOP signals. This allows it to send data to a slave or receive data from a slave as required. In slave mode, the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I2C master device. USB Controller (MAXQ622 Only) The integrated USB controller is compliant with the USB 2.0 specification, providing full-speed operation with the newest generation of USB peripherals. The USB con - troller functions as a full-speed USB peripheral device. Integrating the USB physical interface (PHY) allows direct connection to the USB cable, reducing board space and overall system cost. A system interrupt can be enabled to signal that the USB needs to be serviced. The CPU communicates to the USB controller module through the SFR interface. The microcontroller is seen by a USB host as a peripheral, characterized by the fol - lowing endpoints:
EP0: Bidirectional CONTROL endpoint with a 64-byte data storage.
EP1-OUT: BULK (or INT) OUT endpoint. Double- buffered 64 bytes data storage.
EP2-IN: BULK (or INT) IN endpoint. Double-buffered 64 bytes data storage.
EP3-IN: BULK (or INT) IN endpoint. Single-buffered 64 bytes data storage. The choice to use EP1, EP2, and EP3 as BULK or INTERRUPT endpoints is strictly a function of the end - point descriptors that the USB controller returns to the USB host during enumeration. The USB controller communicates to a total of 384 bytes of endpoint data memory (2 x 64 bytes for each data moving endpoint EP1 and EP2), 64 bytes for the CONTROL endpoint, and 64 bytes for endpoint EP3. Double-buffering EP1 and EP2 improves throughput by allowing the CPU to read or load the next packet while the USB controller is moving the current packet over USB. EP3-IN is intended to serve as a large interrupt endpoint for various USB class specifications such as the Still Image Capture Device. It can also be used as a second BULK IN endpoint. On-Chip Oscillator An external quartz crystal or a ceramic resonator can be connected between HFXIN and HFXOUT, as illustrated in Figure 3. To operate the core from an external clock, connect the clock source to the HFXIN pin and connect the HFXOUT

Figure 3. On-Chip Oscillator

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 pin to GND. The clock source should be driven through a CMOS driver. If the clock driver is a TTL gate, its output must be connected to V DD through a pullup resistor to ensure a satisfactory logic level for active clock pulses. To minimize system noise on the clock circuitry, the external clock source must meet the maximum rise and fall times and the minimum high and low times specified for the clock source. The external noise can affect the clock generation circuit if these parameters do not meet the specification. Noise at HFXIN and HFXOUT can adversely affect on- chip clock timing. It is good design practice to place the crystal and capacitors as near the oscillator circuitry as possible with a direct short trace. The typical values of external capacitors vary with the type of crystal to be used. ROM Loader The ROM loader loads program memory and config - ures loader-specific configuration features. To increase the security of the system, the loader denies access to the system, user loader, or user-application memories unless an area-specific password is provided. Loading Flash Memory An internal bootstrap loader allows reloading over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. The interface hardware can be a JTAG connection to another microcontroller, or a connection to a PC serial port using a USB-to-JTAG converter such as the MAXQUSBJTAG- KIT#, available from Maxim. If in-system programmabil - ity is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and loading the test access port (TAP) with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to one during reset through the JTAG interface executes the bootstrap-loader mode program that resides in the utility ROM. When program - ming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. In addition, the ROM loader also enforces the memory- protection policies. Passwords that are 16 words are required to access the ROM loader interface. In-Application Flash Programming From user-application code, flash memory can be pro - grammed using the ROM utility functions from either C or assembly language. The function declarations below show examples of some of the ROM utility functions provided for in-application flash memory programming: /* Write one 16-bit word to code address ‘dest’. * Dest must be aligned to 16 bits. * Returns 0 = failure, 1 = OK. int flash_write (uint16_t dest, uint16_t data); To erase, the following function would be used: /* Erase the given Flash page * addr: Flash offset (anywhere within page) int flash_erasepage(uint16_t addr); The in-application flash memory programming must call ROM utility functions to erase and program any of the flash memory. Memory protection is enforced by the ROM utility functions. In-Circuit Debug and JTAG Interface Embedded debug hardware and software are devel - oped and integrated to provide full in-circuit debugging capability in a user-application environment. These hard- ware and software features include the following:

Debug engine
Set of registers providing the ability to set breakpoints on register, code, or data using debug service rou - tines stored in ROM Collectively, these hardware and software features sup - port two modes of in-circuit debug functionality:
Background mode: CPU is executing the normal user program Allows the host to configure and set up the in-circuit debugger
Debug mode: Debugger takes over the control of the CPU Read/write accesses to internal registers and memory Single-step of the CPU for trace operation The interface to the debug engine is the TAP control - ler. The interface allows for communication with a bus

that is compatible with the JTAG IEEE Standard 1149. municate synchronously with the host system. is executing inside the system area. when operating from either the battery or the V BUS.

Case 1: The device is powered from V DD and the batteries are removed. Power decays until the power-fail-reset trip point is hit, then the part goes into low-power mode.
Case 2: The device is set to be powered from V DD only, it is connected to USB, and the batteries are removed. Response is identical to Case 1.
Case 3: The device is set to be powered from either VDD or VBUS, it is connected to USB, and the bat - teries are removed. Because the part is already powered from V BUS, nothing changes. If the USB port is subsequently disconnected, power switches over to VDD, the supply decays to the power-fail-reset trip point, and the part goes into low-power mode. As long as there is sufficient charge on the V DD bypass capacitor, it supports the part in power-fail. The hold- up time is similar to the MAXQ610 since the USB port is powered only by V BUS. Note that if the part is powered from VBUS and no battery has been present for a long time (VDD = 0), then upon USB port discon- nection, the power collapses to ground in less than a second. Stop Mode The lowest power mode of operation is stop mode. In this mode, CPU state and memories are preserved, but the CPU is not actively running. Wake-up sources include external I/O interrupts, the power-fail warning interrupt, wake-up timer, or a power-fail reset. Any time the micro - controller is in a state where code does not need to be executed, the user software can put the microcontroller into stop mode. The nanopower ring oscillator is an inter- nal ultra-low-power (400nA) 8kHz ring oscillator that can be used to drive a wake-up timer that exits stop mode. The wake-up timer is programmable by software in steps of 125Fs up to approximately 8s. The power-fail monitor is always on during normal opera- tion. However, it can be selectively disabled during stop

Figure 4. In-Circuit Debugger

the voltage level decays below the warning threshold. when the power-fail warning interrupt is disabled (CKCN. POR and is not affected by other resets. See Table 4. response during normal and stop-mode operation.

Always on—continuous monitoring
211 nanopower ring oscillator clocks (~256ms)
212 nanopower ring oscillator clocks (~512ms)
213 nanopower ring oscillator clocks (~1.024s) In the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two

Table 4. Power-Fail Warning Level Selection Figure 5. Power-Fail Detection During Normal Operation

8000h after satisfying the crystal warmup period. the reset source is removed. Table 5. Power-Fail Detection States During Normal Operation Crystal warmup time, tXTAL_RDY. D On On On — Power drop too short. CPU continues normal operation. Power-fail monitor turns on periodically. Crystal warmup time, tXTAL_RDY. Power-fail monitor turns on periodically. Device held in reset. No operation allowed.

Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled Figure 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled Application enters stop mode. B On Off Off Yes Power drop too short. Power-fail warning detected. Turn on regulator and crystal. Crystal warmup time, tXTAL_RDY. Application enters stop mode. Power-fail monitor turns on periodically. Device held in reset. No operation allowed.

Figure 7. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled Application enters stop mode. Turn on regulator and crystal. Crystal warmup time, tXTAL_RDY. rupt that causes stop mode exit.

is essential to allow the use of dedicated power planes. tors as close to the leads of the devices as possible. can potentially cause a devastating IC latchup. sients that can corrupt system memory. www.maxim-ic.com/microcontrollers.

This MAXQ612/MAXQ622 data sheet, which contains electrical/timing specifications and pin descriptions.
The MAXQ612 /MAXQ622 revision-specific errata sheet (www.maxim-ic.com/errata).
The MAXQ622 User’s Guide, which contains detailed information on features and operation, including pro - gramming.

Application enters stop mode. power-fail, and puts CPU in reset. Power-fail monitor is turned on periodically. Device held in reset. No operation allowed.

16-Bit Microcontrollers with Infrared Module and Optional USBMAXQ612/MAXQ622 Development and Technical Support Maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following:

Compilers
In-circuit emulators
Integrated Development Environments (IDEs)
JTAG-to-serial converters for programming and debugging A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. For technical support, go to https://support.maxim-ic. com/micro.

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Block Diagram 16-BIT MAXQ RISC CPU 8kHz NANO RING 6KB SRAM IR TIMER 2x SPI 2x USART I2C 128KB FLASH SECURE MMU 16-BIT TIMER USB SIE* TXCVR GPIO *MAXQ622 ONLY. VOLTAGE MONITOR IR DRIVERREGULATOR WATCHDOG CLOCK 6KB ROM MAXQ612/MAXQ622 PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

64 LQFP C64+5 21-0083

44 TQFN-EP T4477+2 21-0144

16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 31 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 2/10 Initial release — 1 5/10 Changed the VDDIOH spec for IOH from IOH = 20mA to IOH = 10mA in the Recommended Operating Conditions table 5

Summary

16-Bit Microcontrollers with Infrared Module and Optional USB 19-5117; Rev 1; 5/10

Description