MAXQ3180-RAN+

MAXQ3180 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Supports IEC 60687, IEC 61036, and IEC 61268 Standards ♦ Compatible with 3-Phase/3-Wire, 3-Phase/4-Wire, and Other 3-Phase Services ♦ Calculates Active/Reactive/Apparent Energy, RMS Voltage, RMS Current, Voltage Phasor Angle, and Line Frequency ♦ Less Than 0.1% Active Energy Error Over a Dynamic Range of 1000:1 at +25°C ♦ Less Than 0.2% Reactive Energy Error Over a Dynamic Range of 1000:1 at +25°C ♦ Better Than 0.5% Accuracy for RMS Voltage and RMS Current ♦ Two Pulse Outputs: One for Active Power and One Selectable Between Reactive and Apparent Power ♦ Programmable Pulse Width ♦ Programmable Startup Current Threshold ♦ Programmable Meter Constant ♦ Up to 21st Harmonic Measurement ♦ Neutral Line Current Measurement ♦ Calculates Amp-Hours in the Absence of Voltage Signals ♦ On-Chip User-Programmable Thresholds for Line Voltage Undervoltage and Overvoltage Detection ♦ On-Chip Digital Integrator Enables Direct Interface-to-Current Sensors with di/dt Output ♦ On-Chip Digital Temperature Sensor ♦ Precision Internal Voltage Reference 2.048V (30ppm/°C Typical); Also Supports an External Voltage Reference Input ♦ Active Energy of Each Phase and Combined 3-Phase (kWh), Positive and Negative ♦ Active Power of Each Phase and Combined 3-Phase (kW) ♦ Reactive Energy of Each Phase and Combined 3-Phase (kVarh), Quadrants 1 to 4 ♦ Reactive Power of Each Phase and Combined 3-Phase (kVar) ♦ Apparent Energy of Each Phase and Combined 3-Phase (kVAh) ♦ Apparent Power of Each Phase and Combined 3-Phase (kVA) ♦ Line Frequency (Hz) ♦ Power Factor ♦ Overcurrent and Overvoltage Detection ♦ Voltage Sag Detection ♦ RMS Current and RMS Voltage ♦ Line-Cycle-Wise Instant Current, Voltage, and Power ♦ Phase Sequence Error Detection ♦ Phase Voltage Absence Detection ♦ Supports Software Meter Calibration ♦ Up to 3-Point Multipoint Calibration to Compensate for Transducer Nonlinearity ♦ Power-Fail Detection ♦ Bidirectional Reset Input/Output ♦ SPI-Compatible Serial Interface with Interrupt Request (IRQ) Output ♦ Single 3.3V Supply, Low Power (10mW Typical) ♦ 28-Pin TSSOP Package MAXQ3180 Low-Power, Multifunction, Polyphase AFE

Ordering Information

Rev 0; 2/08 +Denotes a Pb-free/RoHS-compliant package. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of a ny device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. PART TEMP RANGE PIN- PACKAGE MAXQ3180-RAN+ -40 °C to +85°C 28 TSSOP MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. Pin Configuration and Typical Application Circuit appear at end of data sheet.

Low-Power, Multifunction, Polyphase AFE ABSOLUTE MAXIMUM RATINGS METERING SPECIFICATIONS (AVDD = DVDD = VRST to 3.6V, Current Channel Dynamic Range 1000:1 at TA = +25°C, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on Any Pin Relative to JEDEC J-STD-020 Specification. PARAMETER CONDITIONS MIN TYP MAX UNITS Active Energy Error DR 1000:1 0.1 % Reactive Energy Error DR 1000:1 0.2 % Apparent Energy Error DR 1000:1 0.5 % RMS Voltage Error DR 20:1 0.5 % RMS Current Error DR 500:1 0.5 % Line Frequency Error 0.5 % Power Factor Error 0.5 % Active Energy Error with Harmonic Components (Note 2) 0.1 %

ELECTRICAL CHARACTERISTICS

(AVDD = DVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER-SUPPLY SPECIFICATIONS Digital Supply Voltage DV DD V RST 3.6 V Power-Fail Interrupt Trip Point V PFW Active mode, EPWRF = 1 2.84 3.13 V Power-Fail Reset Trip Point V RST Active mode 2.70 2.99 V Analog Supply Voltage AV DD V RST 3.6 V Analog Supply Current I AVDD f CLK = 8MHz 1.1 1.8 mA Digital Supply Current I DVDD f CLK = 8MHz 9.0 14 mA Low-Power Measurement Mode Current ILPMM LOWPM = 1 (Note 1) 3 mA

Low-Power, Multifunction, Polyphase AFE ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL I/O SPECIFICATIONS Input High Voltage V IH 0.7 x DVDD V Input Low Voltage V IL 0.3 x DVDD V Input Hysteresis V IHYS DV DD = 3.3V 550 mV Input Leakage I L V IN = GND or DVDD, pullup off ±0.01 ±1 μA Input Low Current I IL V IN = 0.4V, weak pullup on -40 μA RESET Pullup Resistance R RESET 27 32 36 k IOH = -4mA DVDD -

0.4 Output High Voltage (Except

RESET) V OH IOH = -6mA DVDD - 0.5 V IOL = 4mA 0.4 Output Low Voltage V OL IOL = 6mA 0.5 V SYSTEM CLOCK SOURCES External Clock Input Frequency 0 8.12 MHz External Clock Input Duty Cycle 45 55 % External HF Crystal Frequency Fundamental mode 1.00 8.12 MHz XTAL1, XTAL2 Load Capacitance 30 pF Internal RC Oscillator Frequency 7.4 8.0 8.6 MHz Internal RC Oscillator Drift 250 ppm/ °C Internal RC Oscillator Current 50 120 μA ANALOG-TO-DIGITAL CONVERTER Input Voltage Range 0 2 V Offset Error ± 2 mV Offset Error Drift ±8 μV/ °C Gain Error 0.025 % Total Harmonic Distortion THD Input sine wave f = 1kHz 80 dB Input Capacitance Differential (Note 1) 32 pF Input Bandwidth (-3dB) (Note 1) 7 kHz INTERNAL VOLTAGE REFERENCE Temperature Coefficient (Note 1) 30 ppm/ °C Output Voltage 2.048 V INTERNAL TEMPERATURE SENSOR Temperature Error (Note 1) -4 +4 °C

Low-Power, Multifunction, Polyphase AFE ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI SLAVE-MODE INTERFACE TIMING SCLK Input Pulse-Width High t SCH 4 x tCLCL ns SCLK Input Pulse-Width Low t SCL 4 x tCLCL ns SSEL Low to First SCLK Edge (Slave Enable) tSE 4 x tCLCL ns Last SCLK Edge to SSEL High (Slave Disable) tSD 2 x tCLCL ns MOSI Valid to SCLK Sample Edge (MOSI Setup) tSIS 3 x tCLCL ns SCLK Sample Edge to MOSI Change (MOSI Hold) t SIH t CLCL ns SCLK Shift Edge to MISO Valid (MISO Hold) tSOV 3 x tCLCL ns Note 1: Specifications guaranteed by design but not production tested. Note 2: Conditions abide to Section 5.6.2.1 per IEC 61036. Note 3: Specifications to -40°C are guaranteed by design and are not production tested. SPI Slave Mode Timing SSEL SHIFT EDGE SAMPLE EDGE SCLK DATA OUTPUT DATA INPUT tS tS tS tM tM tM tS tM tS tM tS tM tS

Low-Power, Multifunction, Polyphase AFE Block Diagram MAXQ3180 CFP, CFQ COUNTERS I/O BUFFERSI/O REGISTERS ADC CFQ CFP V2P I0P V0P VCOMM RESET VREF V1P I1P I2P INP SPI I/O BUFFERSI/O REGISTERS WATCHDOG TIMER ADC CLOCK PRESCALER MISO MOSI SCLK SSEL XTAL1 SYSCLK ADCCLK XTAL2 I/O BUFFERS I/O REGISTERS HF RC OSC/8 HF XTAL OSC POR/ BROWNOUT MONITOR 16 x 16 HW MULTIPLY 48-BIT ACCUMULATE IRQ I2N VN I0N I1N TEMP SENSE REF ADC CONTROL, ELECTRICITY METERING DSP, COMMUNICATIONS MANAGER

Low-Power, Multifunction, Polyphase AFE Pin Description PIN NAME FUNCTION 1 VN

2 INP

3 I0P

4 I0N

5 I1P

6 I1N

7 I2P

8 I2N

Analog Inputs for the Phase A, Phase B, Phase C, and Neutral Current Channels

9 AGND Analog Ground

10 XTAL2

11 XTAL1

High-Frequency Crystal Input/Output. When using an external high-frequency crystal, the crystal oscillator circuit s hould be connected between XTAL1 and XTAL2. When using an externally driven clock (EXTCLK = 1), the clock should be input at XTAL1, with XTAL2 left unconnected. 12 IRQ Interrupt Request Output. This line is driven low by the device to indicate to the master that an unmasked interrupt has occurred. 13 SSEL Slave Select Input. This line is the active-low slave select input for the SPI interface. 14 SCLK Slave Clock Input. This line is the clock input for the SPI interface, which always operates in slave mode. 15 MOSI Master Out-Slave In Input. This line is used by the master to transmit data to the slave (the MAXQ3180) over the SPI interface. 16 MISO Master In-Slave Out Output. This line is used by the MAXQ3180 (the slave) to transmit data back to the master over the SPI interface. 17, 22 DVDD Digital Supply Voltage

18 DGND Digital Ground

19 CFP Active Energy Pulse Output

20 CFQ Reactive Energy Pulse Output

21 RESET

Active-Low Reset Input/Output. An external master can reset the MAXQ3180 by driving this pin low. This pin includes a weak pullup resistor to allow for a combination of wired-OR external reset sources. An RC circuit is not required for power-up, as this function is provided internally. This pin also acts as a reset output when the source of the reset is internal to the device (power-fail, watchdog reset, etc.). In this case, the RESET pin is held low by the device until it exits the reset state, then the RESET pin is released. 23 VCOMM Voltage Bias. This pin can be used to create an input common-mode DC offset for ADC channel conversions. 24 VREF Voltage Reference. Reference voltage for the ADC. An external reference voltage can be connected to this pin when extremely high accuracy is required.

25 AVDD Analog Supply Voltage

26 V0P

27 V1P

28 V2P

Analog Inputs for the Phase A, Phase B, and Phase C Voltage Channels

Low-Power, Multifunction, Polyphase AFE Detailed Description Operating Modes The MAXQ3180 has four basic modes of operation, each of which is described in the following sections. The Initialization Mode is the default mode upon power- up or following reset; entry to and exit from the other operating modes is only performed as a result of com- mands sent by the master. Initialization Mode This is the default operating mode for the MAXQ3180 following reset, power-up, or a switch into or out of Low- Power Measurement Mode (LPMM). In this mode, no power measurements are taken because the MAXQ3180 has not yet been configured. When entering this mode, the MAXQ3180 sets the status flag NOINIT to 1 and drives the IRQ pin low to indicate to the master that initialization is required. The master is responsible for performing the following series of operations:

• Interrogating the MAXQ3180 to determine that the NOINIT bit has been set.
• Loading all RAM configuration registers with appro- priate values.
• Clearing the NOINIT bit to zero. Once the NOINIT bit has been cleared to zero, the MAXQ3180 exits Initialization Mode and enters Run Mode (or LPMM mode if LOWPM = 1). It is the master’s responsibility to ensure that all configuration registers have been set to their correct values before clearing the NOINIT bit. Run Mode This mode is the normal operating mode for the MAXQ3180. In this mode, the MAXQ3180 continuously executes the following operations:
• Scans analog front-end channels and collects raw voltage and current samples.
• Processes voltage and current samples through DSP filters as enabled and configured.
• Calculates power, energy, and other required quanti- ties and stores these values in RAM registers.
• Responds to register write and read commands from the master.
• Outputs power pulses on CFP and CFQ as configured.
• Drives IRQ when an interrupt condition has been detected and the interrupt is not masked. Low-Power Measurement Mode (LPMM) This mode allows the MAXQ3180 to perform all normal electric-metering functions while operating at a reduced clock rate to conserve power. In this mode, the MAXQ3180 switches its system clock from the high- frequency external crystal (or external clock source) to its internal RC oscillator. The actual system clock fre- quency used is the RC oscillator output frequency divided by 8, which results in a system clock frequency of approximately 1MHz. Entry to LPMM Mode only occurs at the request of the master. The master must set the LOWPM bit (STATUS.2) to 1 to place the MAXQ3180 into LPMM mode. Setting this bit automatically sets the NOINIT bit and returns the device to Initialization Mode. This is done because changing the clock frequency invalidates a number of configuration registers, which need to be reinitialized with new, updated values before metering-measure- ment operations can continue. Note that it is also possi- ble to set LOWPM = 1 (and load configuration registers appropriately) immediately following reset, which caus- es the MAXQ3180 to transition directly from Initialization Mode to LPMM Mode once NOINIT has been cleared by the master. The master can also instruct the MAXQ3180 to exit LPMM Mode by clearing the LOWPM bit. This causes NOINIT to be set as with LPMM entry, and the master must reset the appropriate configuration registers and clear NOINIT to allow measurement to continue. Stop Mode This mode places the MAXQ3180 into a power-saving state where it consumes the least possible amount of current. In Stop Mode, all functions are suspended, including the ADC and power and voltage measurement and processing. The MAXQ3180 does not respond to any commands from the master in this operating state. Entry into Stop Mode only occurs at the request of the master. To place the MAXQ3180 into Stop Mode, the master must set the STOPM bit (STATUS.1) to 1. Once this bit has been written, the MAXQ3180 enters Stop Mode immediately following the end of the register write command (after the transmission of the final ACK byte by the MAXQ3180). There are three possible ways to bring the MAXQ3180 back out of Stop Mode.
• Power Cycle. The MAXQ3180 automatically exits Stop Mode if a power-on reset occurs. Following exit from Stop Mode, all registers are cleared back to their default states, and the MAXQ3180 transitions to Initialization Mode.
• External Reset. The MAXQ3180 exits Stop Mode if an external reset is triggered by driving RESET low. Once the RESET pin is released and allowed to

INDICATES THAT COMMANDS FROM THE MASTER CAN BE RECEIVED IN THIS MODE. Figure 1. Operating Modes

• External Interrupt. Driving the SSEL pin low causes the MAXQ3180 to exit Stop Mode without undergoing a reset cycle. When exiting Stop Mode in this man- ner, all register and configuration settings are retained, and the MAXQ3180 automatically resumes electric-metering functions and sample processing. Note that when the master is communicating with the MAXQ3180, the SSEL line is normally driven low at the beginning of each SPI command. This means that if the master sends an SPI command after the MAXQ3180 enters Stop Mode, the MAXQ3180 automatically exits Stop Mode and receives the command.

press) driving the RESET pin on the MAXQ3180 low. and resumes execution in Initialization Mode. mands in Initialization Mode. the internal RC oscillator (or approximately 128μs). MAXQ3180 to reset in the same way. Figure 2. External Reset

enter Initialization Mode, the IRQ line drops low. The watchdog timer does not run during Stop Mode. same manner as if an external reset had taken place. not cause the MAXQ3180 to drive the RESET line low. warning) exists and requires attention. BROWNOUT DETECTION DISABLED. Figure 3. Brownout Reset

munications are synchronized to a single system clock. table sources, as shown in Figure 4. suggested by the crystal manufacturer. Figure 4. Simplified Clock Sources

clock input and the XTAL2 pin should be left uncon- nected. The master should also shut down the internal crystal oscillator circuit by setting the EXTCLK bit (STA- TUS0.6) to 1. This bit is only cleared by the MAXQ3180 if a power-on or brownout reset occurs and is unaffect- ed by other resets. When using an external high-frequency clock, the clock signal should be generated by a CMOS driver. If the clock driver is a TTL gate, its output must be connected to DVDD through a pullup resistor to ensure that the correct logic levels are generated. To minimize system noise in the clock circuitry, the external clock source must meet the maximum rise and fall times and the minimum high and low times specified for the clock source in the Electrical Characteristics table. Internal RC Oscillator When the external high-frequency crystal is warming up, or when the MAXQ3180 is placed into LPMM mode, the system clock is sourced from an internal RC oscilla- tor. This internal oscillator is designed to run at approxi- mately 8MHz, although the exact frequency varies over temperature and supply voltage. If no external crystal circuit or high-frequency clock will be used, the MAXQ3180 can be forced to operate indefinitely from the internal oscillator by grounding XTAL1. This ensures that the crystal warmup count never completes, so the MAXQ3180 runs from the inter- nal oscillator in all active modes (Initialization Mode, Run Mode, and LPMM Mode). Master Communications Before the MAXQ3180 can begin performing electric- metering operations, the master must initialize a num- ber of configuration parameters. Since the MAXQ3180 does not contain internal nonvolatile memory, these parameters (stored in internal registers) must be set by the master each time a power-up or reset cycle occurs, or each time a switch is made between LPMM Mode and Run Mode. The external master communicates with the MAXQ3180 over a standard SPI bus, using commands to read and write values to internal registers on the MAXQ3180. These registers include, among many other items:

• Operating mode settings (Stop Mode, LPMM Mode, external clock mode, etc.)
• Status and interrupt flags (not initialized, power-sup- ply failure, overcurrent/overvoltage detection)
• Masking control for interrupts to determine which conditions cause IRQ to be driven low
• Configuration settings for analog channel scanning
• Power pulse output configuration
• Filter coefficients and configuration
• Read-only registers containing accumulated power and energy data Once all the configuration registers have been set by the master to their proper values, the master must clear the NOINIT flag (STATUS1.0) to zero. Once this flag has been cleared, the MAXQ3180 exits Initialization Mode and begins execution in either Run Mode or LPMM Mode, depending on the setting of the LOWPM bit. As the MAXQ3180 obtains voltage and current mea- surements in Run Mode or LPMM Mode, it accumu- lates, filters, and performs a number of calculations on the collected data. Many of these operations (including the various filtering stages) are configured by settings in registers written by the master. The output results can then be read by the master from various read-only registers in parallel with the ongoing measurement and processing operations. SPI Communications Rate and Format The MAXQ3180 provides an SPI bus for master/slave communications. All communications transfers are initi- ated by the external master. The interrupt request line IRQ, while not technically part of the SPI bus interface, is also used for master/slave communications, since it allows the MAXQ3180 to notify the master that an inter- rupt condition exists. During an SPI transfer, data is simultaneously transmit- ted and received over two serial data lines (MISO and MOSI) with respect to a single serial shift clock (SCLK). The polarity and phase of the serial shift clock are the primary components in defining the SPI data transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and, therefore, also defines which clock edge is the active edge. To define a serial shift clock signal that idles in a logic-low state (active clock edge = rising), the clock polarity select (CKPOL; SPICF.0) bit should be configured to a 0, while setting CKPOL = 1 causes the shift clock to idle in a logic-high state (active clock edge = falling). The phase of the serial clock selects which edge is used to sample the serial shift data. The clock phase select (CKPHA; SPICF.1) bit controls whether the active or inactive clock edge is used to latch the data. When CKPHA is set to a logic 1, data is sampled on the inac- tive clock edge (clock returning to the idle state). When CKPHA is set to a logic 0, data is sampled on the active clock edge (clock transition to the active state). Together, the CKPOL and CKPHA bits allow four possi- ble SPI data transfer formats. Low-Power, Multifunction, Polyphase AFE

transfers, allowing the active clock edge to signal the start of a new transfer. The clock rate used for the SPI interface is determined by the bus master, since the MAXQ3180 always oper- ates as an SPI slave device. However, the maximum clock rate is limited by the system clock frequency of the MAXQ3180. For proper communications operation, the SPI clock frequency used by the master must be less than or equal to the MAXQ3180’s clock frequency divided by 8. For example, when the MAXQ3180 is run- ning at 8MHz, the SPI clock frequency must be 1MHz or less. And if the MAXQ3180 is running in LPMM Mode (or if the crystal is still warming up), the SPI clock fre- quency must remain at 125kHz or less for proper com- munications operation. In addition to limiting the overall SPI bus clock rate, the master must also include a communications delay fol- lowing each byte transmit/receive cycle. This delay, which provides the MAXQ3180 with time to process the transmitted byte, should be a minimum of 1 ADC scan slot (time value contained in TIME_FS register, defined as (R_ADCRATE + 1)/(system clock frequency). With default settings and running at 8MHz, this delay time is 25μs. Reducing the system clock frequency to 1MHz (LPMM mode) would increase this delay period by a factor of 8μs to 200μs. SPI Communications Protocol All transactions between the master and the MAXQ3180 consist of the master writing to or reading from one of the MAXQ3180’s registers. There are sever- al different categories of internal registers on the MAXQ3180.

• RAM Registers. The values of these registers are stored in the internal RAM of the MAXQ3180. Some can be read and written by the master, while others are read only. RAM registers are either two or four bytes long (16 or 32 bits), although in some registers not all the bits have defined values. Read/write regis- ters are generally either status/flag registers (which can be written by either the MAXQ3180 or the mas- ter), configuration registers (which are written by the master and read by the MAXQ3180 firmware), or data registers (which are read only and are written by the MAXQ3180 firmware and read by the master).
• Virtual Registers. These read-only registers are not stored in RAM; instead, they contain values that are calculated on the fly by the MAXQ3180 firmware when the master reads them. These registers are used by the master to obtain values such as phase A, B, and C active, reactive, and apparent power; power factor; and RMS voltage and current, which are calculated from currently collected data on an as-needed basis. All virtual registers are 4 bytes in length.
• Hardware Registers. These registers control core functions of the MAXQ3180 including the ADC and the SPI slave bus controller. Each of these registers (R_ACFG, R_ADCRATE, R_ADCADQ, R_SPICF, and STATUS0 (bit 6, EXTCLK only)) has a register loca- tion in RAM that “shadows” the value of the hardware register. To read from a hardware register, the mas- ter must first read from the special command register UPD_MIR (A00h) to copy the values from the hard- ware registers to the mirror registers in RAM, and then the mirror register in RAM can be read. To write to a hardware register, the master reverses the process by writing to the mirror RAM register and then reading from the special command register UPD_SFR (900h) to copy the values from the mirror registers to the hardware registers.
• Special Command Registers. These registers (UPD_SFR and UPD_MIR) do not return meaningful data when read but instead trigger an operation. Reading UPD_SFR causes values to be copied from the mirror registers to hardware, and reading UPD_MIR causes values to be copied from the hard- ware to mirror registers. Every defined register on the MAXQ3180 has a 12-bit address (from 0 to 4095). This address is used when addressing the register for either a read or write opera- tion. Addresses 0 to 1023 (000h to 3FFh) are used to address RAM registers. Registers with addresses from 1024 to 4095 (400h to FFFh) are used for virtual regis- ters and special command registers. Each command consists of a read/write command code, a data length (1, 2, 4, or 8 bytes), a 12-bit regis- ter address, and the specified number of data bytes followed optionally by a CRC. Since SPI is a full-duplex interface, the master and slave must both transmit the same number of bytes during the command. When a multiple-byte register is read or written (2/4/8 byte length), the least significant byte is read or written first in the command. Low-Power, Multifunction, Polyphase AFE

Table 1. Command Format for SPI Register Read

00 Read

01 Reserved

10 Write

3:0 MSB portion of data address. Slave sends 0xC2 byte 7:0 LSB portion of data address. or with ACK when processing complete. Master must receive ACK, then receive data. Table 2. Command Format for SPI Register Write 3:0 MSB portion of data address. Slave sends 0xC2 byte 7:0 LSB portion of data address. or with ACK when processing complete. Master must receive ACK before starting the next transaction.

Table 3. RAM Register Map

Table 3. RAM Register Map (continued)

Table 4. RAM Register Summary 15:7, 0 — Reserved. Should be set to 0.

6 EXTCLK External clock

5 ACCEN Enable energy accumulation

4 RST Software reset

3 CRCEN Enable CRC

2 LOWPM LPMM Mode

1 STOPM Stop Mode

7:6, 2:0 — Reserved. Should be set to 0.

9 TMPC1 Temperature (double)

8 TMPC0 Temperature (single)

3 APPSEL

15 SEQERR Phase sequence error

14 VUNBF Voltage unbalance flag

13 IUNBF Current unbalance flag

12 MISV Missed voltage detected

11 NOZC No zero crossings

10 SAG Voltage sag detected

9 OV Overvoltage detected

8 OC Overcurrent detected

5 DCH_Q Pulse 2 direction change

4 DCH_P Pulse 1 direction change

3 EOVF Energy overflow

2 TMRD Temperature reading ready

1 PWRF Supply power-fail interrupt

0 NOINIT Not initialized

Table 4. RAM Register Summary (continued) 1:0 — Reserved. Should be set to 0.

7 PORF POR flag

5 REV_Q Reverse pulse 2

4 REV_P Reverse pulse 1

2 WTRF Watchdog timer flag

7 INTGN Enable IN integrator (di/dt)

6 INTGC Enable IC integrator (di/dt)

5 INTGB Enable IB integrator (di/dt)

4 INTGA Enable IA integrator (di/dt)

2 INEN Enable neutral current CONNCT 10

7 NOCONV Disable ADC conversion for this

R/W 0x08AF Reserved. Do not modify these bits.

7 ADCASD Automatic shutdown disable

6 ADCRY Sample ready (system)

3 ADCBY ADC busy (system)

2 ADCIE ADC interrupt enable (system)

1 ARBE Internal V REF enable

0 ADCE ADC enable

15:9 — Reserved. Should be set to 0. 15:7 — Reserved. Should be set to 0. 15:8, 5:3 — Reserved. Should be set to 0.

7 ESPII SPI interrupt enable (system)

6 SAS

2 CHR

1 CKPHA SPI clock phase select

0 CKPOL SPI clock polarity select

0x0EC Apparent Energy RO — 15:0 Accumulated apparent energy. Units defined by KWHT setting.

15:13, 7:5 — Reserved. Should be set to 0.

4 MISVF Missing voltage flag

3 NOZCF No zero-crossing flag

2 VSAGF Voltage sag flag

1 OVF Overvoltage flag

0 OCF Overcurrent flag

7 IHOF KWHIH overflow

6 APOF KWHAP overflow

5 R4OF KWHR4 overflow

4 R3OF KWHR3 overflow

3 R2OF KWHR2 overflow

2 R1OF KWHR1 overflow

1 ANOF KWHAN overflow

0 APOF KWHAP overflow

Current RO — 31:0 Per most recent line cycle. Voltage RO — 31:0 Per most recent line cycle. 0x19A Raw Amp-Hours RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle. 0x1DC Apparent Energy RO — 15:0 Accumulated apparent energy. Units defined by KWHT setting.

Current RO — 31:0 Per most recent line cycle. Voltage RO — 31:0 Per most recent line cycle. IH 650 Raw Amp-Hours RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle.

KWHAP 716 Apparent Energy RO — 15:0 Accumulated apparent energy. Units defined by KWHT setting.

Current RO — 31:0 Per most recent line cycle. Voltage RO — 31:0 Per most recent line cycle. IH 890 Raw Amp-Hours RO — 31:0 Per most recent line cycle.

are calculated at the master’s request when needed. cant bit (bit 11) set to 1. All virtual registers are read only. Energy RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle. Energy RO — 31:0 Per most recent line cycle. Current RO — 31:0 Per most recent line-cycle. IH 1000 Raw Amp-Hours RO — 31:0 Per most recent line cycle. Table 5. Virtual Registers

Table 5. Virtual Registers (continued) Table 6. Virtual Register with Special Commands one of the eight differential input pairs is measured.

• Slot 0—Phase A Current (IA)
• Slot 1—Phase A Voltage (VA)
• Slot 2—Phase C Current (IC)
• Slot 3—Phase C Voltage (VC)
• Slot 4—Phase B Current (IB)
• Slot 5—Phase B Voltage (VB)
• Slot 6—Neutral Current (IN)—disabled by default
• Slot 7—Temperature Measurement—normally dis- abled, activated when TMPC0 or TMPC1 is set

measurement command) bits are set by the master. register, as shown in Table 7.

• Zero-crossing detection
• Line frequency and line period calculation
• RMS voltage (phase A, phase B, phase C)
• RMS current (phase A, phase B, phase C, neutral current)
• Power (active, reactive, and apparent) for each phase
• Energy accumulation (including energy pulse output function)
• Peak voltage (phase A, phase B, phase C)
• Peak current (phase A, phase B, phase C)
• Voltage sag condition
• Tamper condition detection Voltage Zero-Crossing Detection The MAXQ3180 monitors each of the three voltage input signals (from phase A, phase B, and phase C) and detects zero-crossing events on each of them indi- vidually. The sequence of the detected zero crossings and the intervals between them are then used to calcu- late additional data. Before zero-crossing detection is performed, each of the three voltage inputs (VA, VB, and VC) are passed through a first-order lowpass filter (LPF) with a cutoff frequency near 50Hz to reduce harmonics, which can trigger false zero-crossing events. The master can con- figure this LPF by setting the register LPF_B0FZC. The equation for the zero-crossing LPF (for all three voltage phase inputs) is as follows: Y n = Yp + (Xn - Yp) x LPF_B0FZC/216 Although the filtered waveform output is not a perfect sine wave, the LPF ensures that the output has no more than one ascending zero crossing per line period. Following the LPF filter processing stage, the MAXQ3180 scans the voltage signals to detect ascend- ing zero-crossing events for each voltage phase. Line Frequency and Period Measurement For each phase A, B, and C, the MAXQ3180 counts the number of scan frames (NS) between two consecutive zero crossings. The NS is a global value, common for all three phases, and is located in RAM at address 0x08C. Each individual phase A, B, or C zero-crossing event contributes raw NS count, which plugs as input to the LPF. Low-Power, Multifunction, Polyphase AFE

Table 7. Analog Scan Slot Time Selection

the filter above receives three inputs each line cycle. the virtual register LINEFREQ. NOZC back to 0 to remove the interrupt condition. to remove the interrupt condition. cycle-based integration process. the next DSP trigger to avoid losing accumulated data. provide plenty of CPU time for both tasks.

• P1 = (VA x IA)
• P2 = (VB x IB) or -IB x (VA + VC) or -IB x VA
• P3 = (VC x IC) The P1 and P3 accumulators always operate in a single mode: (VA x IA) for the P1 accumulator, (VC x IC) for the P3 accumulator. Alternately, the operating mode of the P2 accumulator is defined by setting bits 0 and 1 in the CONNCT register as shown in Table 8. If the CONNCT bits are set to 01b, then the P2 (phase B) input voltage sample is calculated using an allpass filter described as: (VA + VC) n = (AVCO/216)(VCn + VAn-1) + (AVC1/216)(VCn-1 + VAn) MAXQ3180 Low-Power, Multifunction, Polyphase AFE

Table 8. P2 Power Accumulator Modes

and can be configured by the master. by factor 16 in the MAXQ3180. path when the current integrator is active. operation is selected by the HRM configuration bits.

• HRM = 00b—Full mode. Neither the bandpass or the bandstop filters are applied.
• HRM = 01b—Fundamental mode. The voltage chan- nel signal is put through the bandpass filter (BPF). This BPF is centered on the fundamental frequency, so only fundamental power is measured.
• HRM = 10b—Harmonics mode. The voltage channel signal is put through the bandstop filter (BSF). That BSF is centered on the fundamental frequency, so fundamental power is removed and only harmonics power is measured. Both filters, the BPF and BSF, are second-order filters and use the same set of coefficients. The filter formulas are: BPF: Y n = 2Yn-1 - Yn-2 + (bpf_b0f/220) x (2Yn-2 + Xn - Xn-2) - (bpf_a1f/220) x Yn-1 BSF: Yn = 2Yn-1 - Yn-2 + Xn - 2Xn-1 - Xn-2 + (bpf_b0f/220) x (2Yn-2 - Xn - Xn-2) + (bpf_a1f/220) x (Xn-1 - Yn-1) Low-Power, Multifunction, Polyphase AFE INTEGRATOR + HPF PHASE ANGLE COMPENSATION GAIN, OFFSET, AND LINEARITY CALIBRATION SI2 I2_RMS V2_RMS P.V2 ACTIVE REACTIVE HPF HPFI SV2 S HPFV BPF BSF P.R P.A P.I2

Figure 8. DSP Flow

Low-Power, Multifunction, Polyphase AFE Filter coefficients (bpf_b0f and bpf_a1f) are signed 16- bit values and can be configured by the master. By default they are tuned to 50Hz frequency, provided that all other parameters are also set to default values. The coefficients of the filters should be updated periodically by the master to track the actual line frequency that may deviate from the preset value. It is usually enough to update only one coefficient (bpf_a1) to change the filter’s peak frequency slightly. The same mechanism of BPF can be used for a special feature—measuring individual harmonics. The BPF coefficients can be set to values that pass only the Nth- order harmonics on the voltage channel. Then, the V RMS output produces the Nth harmonics voltage and the power output produces the Nth harmonics power. The current I RMS can then be calculated by the master as IRMS = Power/VRMS. Phase Angle Compensation Phase angle compensation requires two coefficients— cosine and sine of the phase angle PA. The phase compensation angle PA is calculated based on the log- arithm of the raw RMS-current values using 3rd-order curve fitting: PA x 2 16 = PA_0 + (PA_1 x X) + (PA_2 x X2) + (PA_3 x X3) Where Where brackets [ ] denote the integer and ln_off is the hard-coded value 6100h. Curve-fitting coefficients are usually obtained during the calibration process and loaded into RAM registers upon initialization. Once the phase angle PA has been calcu- lated, the MAXQ3180 calculates SIN(PA) and COS(PA) and performs phase compensation for active and reac- tive energy. By default, all curve-fitting coefficients are zeros: PA_0 = PA_1 = PA_2 = PA_3 = 0. The calibration procedure is discussed in the Typical Calibration Procedure for MAXQ3180section. Apparent Power Apparent power is then calculated. The method used is selectable using the APPSEL (OPMODE.3) bit. If APPSEL = 0 (the default mode), then Pwr_S = sqrt (Pwr_A 2 + Pwr_R2) If APPSEL = 1, then Pwr_S = VRMS x IRMS x NS, and scaled by shifting in order to produce the same magnitude as the square-root method (APPSEL = 0). Linearity Correction The MAXQ3180 applies linearity compensation to active, reactive, and apparent energy based on whether input current signal level is in high range or in low range. The signal is considered high range if the voltage across the analog input pins is greater than approximately 48mV P-P; otherwise the signal is consid- ered low range. For high range, offset correction is applied to the apparent power value: Pwr_S_corr = Pwr_S - Eoff_hi x K For low range, both offset and gain correction factors are applied to the apparent power value: Pwr_S_corr = (1 + Gain_lo/2 16) x (Pwr_S - Eoff_lo x K) The factor K accounts for possible voltage and line fre- quency changes: K = [NS/216] x [VRMS/216]/216 Separate linearity compensation coefficients (Eoff_hi, Eoff_lo, Gain_lo) are used for each phase. Initial values of those coefficients are loaded upon default initialization; the master can then overwrite coefficients if necessary. Once the corrected apparent power has been calculat- ed, the MAXQ3180 applies proportional correction to active and reactive power, and applies common power gain to all power samples: Pwr_A_corr = (1 + E_gain/2 16) x Pwr_A x Pwr_S_corr/Pwr_S, Pwr_R_corr = (1 + E_gain/216) x Pwr_R x Pwr_S_corr/Pwr_S, Pwr_S_corr = (1 + E_gain/216) x Pwr_S_corr The calibration procedure is discussed in the Typical Calibration Procedure for MAXQ3180 section. Energy Accumulation Start Delay All filters have a certain settling time before accurate energy readings can be accumulated. To avoid accu- mulation of invalid data from filters that are still settling, an energy accumulation timeout period can be set in the ACC_TIMO register. Together with the accumula- tion enable (ACC_EN) bit, this provides a means to control the preaccumulation delay. After reset, ACC_EN = 0 and no energy is accumulated. After the ACC_TIMO scan slots have elapsed, the MAXQ3180 sets ACC_EN = 1 and energy accumulation begins. No-Load Feature To avoid meter creep, no energy accumulation should take place when calculated apparent power is less than a certain threshold. The NOLOAD register can be X xI n I R M S I n o f f([( ) ([ / ])] _ )= 22 12 16

NOLOAD = 0 disables this feature. accumulation from the level PLS1 = PLS1 - THR1. phase(s) are included in the pulse output. quantity that is directed into the pulse 2 output. accumulator is cleared and starts accumulation over. request to the master if enabled (unmasked). rupt request to the master if enabled (unmasked). Table 9. Pulse Output Configuration

001 E1 001 E1

010 E2 010 E2

011 E1 + E2 011 E1 + E2

100 E3 100 E3

101 E1 + E3 101 E1 + E3

110 E2 + E3 110 E2 + E3

111 E1 + E2 + E3 111 E1 + E2 + E3

Table 10. Pulse Output Quantity Selection

00000 AP - AN True active energy (may be negative)

00001 AP + AN Absolute active energy

00010 R1 + R2 - R3 - R4 True reactive energy (may be negative)

00011 R1 + R2 + R3 + R4 Absolute reactive energy

00100 VA Apparent energy

00101 IH Amp-hours

00110 I RMS I RMS (for calibration purposes)

00111 V RMS V RMS (for calibration purposes)

01000 AP Active positive energy

01001 AN Active negative energy

nificant bits of the raw RMS registers, i.e., bits 31:16. overcurrent level is determined by the OCLVL register. most significant bits of the VRMS or IRMS registers. Table 10. Pulse Output Quantity Selection (continued)

01010 R1 Reactive quadrant 1 energy

01011 R2 Reactive quadrant 2 energy

01100 R3 Reactive quadrant 3 energy

01101 R4 Reactive quadrant 4 energy

01110 R1 + R3 Absolute inductive energy

01111 R2 + R4 Absolute capacitive energy

Figure 9. Peak Current-Detection Timing

master by writing the appropriate register. events on each phase independently. interrupt request when they are set to 1.

• Missing Potential. The MAXQ3180 detects a miss- ing potential condition if a phase voltage waveform either has a magnitude less than 10% of the full- scale range or has no zero crossings, i.e., the entire waveform lies above or below zero. The MISVF bit is set in the FLAGS status register for phase A, B, or C to report a missing potential condition. Also, the MISV flag bit is set in the STATUS1 register, which can cause an interrupt request signal if enabled.
• Voltage Unbalance. The MAXQ3180 detects a volt- age unbalance condition if the sum of all three volt- age signals (e.g., VA + VB + VC) has a magnitude greater than VUBLVL/2. The VUBLVL register repre- sents the 16 most significant bits of the raw VRMS register. The VUNBF flag is set in the STATUS1 reg- ister to report voltage unbalance. This can cause an interrupt request signal if enabled.
• Current Unbalance. The MAXQ3180 detects a cur- rent unbalance condition if the sum of current signals IA + IB + IC has a magnitude greater than IUBLVL/2. The IUBLVL register represents the 16 most significant bits of a raw IRMS register. The IUNBF flag is set in the STATUS1 register to report a current unbalance. Meter Units to Real Units Conversion All energy calculations, including various threshold checks, are performed internally in fixed format in meter units. Therefore, the threshold values must be supplied by the user in meter units as well. This section describes how to convert real units (V, A, kWh, etc.) into meter units and vice versa. The conversion factors are based on the settings shown in Table 11, defined by the user’s design. Meter units are defined with respect to the base para- meters in Table 11 as shown in Table 12. Low-Power, Multifunction, Polyphase AFE

Table 11. Meter to Real Units Conversion Default conditions are R_ADCRATE = 199, f SYS = 8MHz. Default conditions are t FR = 200μs, f LINE = 50Hz. Default conditions are V FSADC = 1V, VTR = 545V/V (for reference meter design). Default conditions are V FSADC = 1V, ITR = 100A/V (for reference meter design).

Table 12. Meter Unit Definitions

Table 13. Virtual Register Coefficients describes how to set the coefficients. raw ADC sample proportional to absolute temperature. read the TEMP register and clear the TMRD status flag. MAXQ3180 with the calibration constants.

• Current Gain Calibration
• Voltage Gain Calibration
• Power Gain Calibration
• Power Linearity Calibration
• Phase Angle Calibration Each item requires one or more signals be applied to the meter’s inputs, then the output to be measured. The calibration coefficients are then calculated, verified, and loaded into the MAXQ3180’s RAM registers. The power linearity calibration and the phase angle calibra- tion can be performed in any order. Current Gain Calibration To perform the current gain calibration, all three phase voltages 220V should be applied. Only one current sig- nal of max amplitude (I MAX) is applied to the phase input being calibrated. From the view of the MAXQ3180 pins, the other current inputs should be grounded or

connected together to result in zero current. Note: All intermediate calculations should be performed with double precision, and the last result rounded to the nearest integer. 1) Clear I_gain coefficient that is being calibrated to 0x0000. 2) Measure average raw IRMS by reading the RAM register several times. 3) Calculate expected raw RMS value using the fol- lowing proportion: Full_scale_current: produces FS_raw_rms = 2 I_input_current: produces Expected_raw_rms Here, Full_scale_current is the input current that is transformed into 1V RMS at the input pins. That Full_scale_current value depends on the transduc- er chosen for meter design. For example, if current sensor is a transformer 10A to 5mA with 20 Ω load resistor, then Full_scale_current = 100A, because it is transformed to 50mA x 20Ω = 1V. 4) Calculate I_gain coefficient: I_gain = [Expected_raw_rms/ Measured_raw_rms) - 1] x 2 Voltage Gain Calibration To perform the voltage gain calibration, all three phase voltages 220V should be applied. Current inputs should be zero. Note: All intermediate calculations should be performed with double precision, the last result round- ed to the nearest integer. 1) Clear V_gain coefficient being calibrated to 0x0000. 2) Measure average raw VRMS by reading the RAM register several times. 3) Calculate expected raw RMS value using the fol- lowing proportion: Full_scale_voltage: produces FS_raw_rms = 2 V_input_voltage: produces Expected_raw_rms Here, Full_scale_voltage is the input voltage that is transformed into 1V RMS at the input pins. That Full_scale_voltage value depends on the trans- ducer chosen for meter design. For example, if voltage sensor is a divider with a 544:1 resistor ratio, then Full_scale_voltage = 545V, because it is transformed to 1V. 4) Calculate V_gain coefficient: V_gain = [(Expected_raw_rms/ Measured_raw_rms) - 1] x 2 Power Gain Calibration To perform the power gain calibration, all three phase voltages 220V must be applied. Only one current signal of max amplitude (I MAX) is applied to the phase input being calibrated. The current sine wave should be in phase with the corresponding voltage sine wave, i.e., power factor 1. Other current inputs should be zero. 1) Clear the E_gain coefficient being calibrated to 0x0000. 2) Measure the power output of the meter. This can be done in two ways: (a) by reading raw RAM reg- isters from the MAXQ3180, or (b) by measuring pulse output error. The following procedure depends on the way of measuring power output. a) Measure average raw apparent energy by reading the RAM register several times. b) Pulse output error is typically measured by the tester equipment. The pulse output parameters in the MAXQ3180 must be properly configured before pulse output error can be measured. The PLSCFG register should be set to output apparent energy of one phase being calibrat- ed. That setting is: If measuring pulse 1 output on the CFP pin: PLSCFG = 0x0021 for phase A PLSCFG = 0x0022 for phase B PLSCFG = 0x0024 for phase C or If measuring pulse 2 output on the CFQ pin: PLSCFG = 0x2100 for phase A PLSCFG = 0x2200 for phase B PLSCFG = 0x2400 for phase C c) Then, the corresponding pulse threshold regis- ter should be set to the proper value; that is, THR1 register if measure pulse 1 output on the CFP pin, or THR2 register if measure pulse 2 output on the CFQ pin. The value for the thresh- old register defines the pulse output rate and should match the rate expected by tester equipment. The tester typically expresses pulse output rate as a meter constant (MC) indicating the number of pulses per kWh. The proper threshold value is then calculated as: (THR1 or THR2) = 2 18 x 103/(MC x IFS x VFS x tFR) In this formula IFS is the Full_scale_current described in the Current Gain Calibration sec- tion, VFS is the Full_scale_voltage described in MAXQ3180 Low-Power, Multifunction, Polyphase AFE

the Voltage Gain Calibration section, and tFR is the sampling time that depends on the MAXQ3180 system clock frequency and sam- pling rate register setting (ADCRATE): t FR = (ADCRATE + 1) x 8/fSYS For example, for the default conditions ADCRATE = 199 and f SYS = 8MHz, then t FR = 200μs = 55.55nh. Using typical example values IFS = 100A and VFS = 545V, the formula for the threshold can be transformed into the following: Typical (THR1 or THR2) = 86,579,669,725/MC Note: Threshold is a 32-bit register, which imposes a limitation on the minimal meter con- stant to avoid overflow. When the PLSCFG and THR1 (or THR2) regis- ters are set, the pulse output error can be mea- sured by tester equipment. That error is usually expressed as % of the expected power. 3) If choice 2a was made (apparent energy by read- ing RAM register), then perform step 3. Calculate expected raw energy value using the following proportion: Full_scale voltage x Full_scale_current: pro- duce FS_raw_pwr = 2 18/(fLINE x tFR) V_input_voltage x I_input_current: produce Expected_raw_pwr Here, Full_scale_voltage, Full_scale_current, and t FR are the same as described above, f LINE is the line frequency of the input voltage, typically 50Hz or 60Hz. 4) Calculate E_gain coefficient: a) If output was measured by reading RAM register: E_gain = [(Expected_raw_pwr/ Measured_raw_pwr) - 1] x 2 b) If output was measured through pulse output error: E_gain = (216) x (-Measured_Error%)/ (100% +Measured_Error%) Note: All intermediate calculations should be performed with double precision, the last result rounded to the nearest integer. Power Linearity Calibration This calibration compensates for nonlinearity over the range and requires at least four power measurements at different loads. To perform the power linearity cali- bration, all three phase voltages 220V must be applied. Only one current signal is applied to the phase input being calibrated. The current sine wave should be in phase with the corresponding voltage sine wave, i.e., power factor 1. Other current inputs should be 0. 1) Clear the Eoff_hi, Gain_lo, and Eoff_lo coefficients being calibrated to 0x0000. 2) Make power measurements. a) First power measurement. Apply current input signal of the RMS value close to IFS/2 1.5 to the phase input being calibrated. For example, typ- ical target value is 100/2 1.5 = 35.36A, so rea- sonable input current is 30A or 40A. Measure average raw apparent energy by reading the RAM register several times. Denote applied current as I1 and measured power as P1 for future reference. b) Second power measurement. Apply current input signal of the RMS value close to IFS/2 4.5 to the phase input being calibrated. For exam- ple, typical target value is 100/2 4.5 = 4.42A, so reasonable input current is 4A or 5A. Measure average raw apparent energy by reading the RAM register several times. Denote applied current as I2 and measured power as P2 for future reference. c) Third power measurement. Apply current input signal of the RMS value close to IFS/2 6.5 to the phase input being calibrated. For example, typ- ical target value is 100/2 6.5 = 1.10A, so reason- able input current is 1A. Measure average raw apparent energy by reading the RAM register several times. Denote applied current as I3 and measured power as P3 for future reference. d) Fourth power measurement. Apply current input signal of the RMS value close to IFS/2 9.5 to the phase input being calibrated. For exam- ple, typical target value is 100/2 9.5 = 0.14A, so reasonable input current is 0.1A or 0.2A. Measure average raw apparent energy by reading the RAM register several times. Denote applied current as I4 and measured power as P4 for future reference. Low-Power, Multifunction, Polyphase AFE

3) Measure average raw VRMS by reading the RAM register several times. 4) Measure average NS by reading the RAM register several times. 5) Calculate coefficient K = [NS/216] x [VRMS/216]/216. 6) Calculate Eoff_hi coefficient: Eoff_hi = [(P2 x I1 - P1 x I2)/(I1 - I2)])/K. 7) Calculate Eoff_lo coefficient: Eoff_lo = [(P4 x I3 - P3 x I4)/(I3 - I4)]/K. 8) Calculate Gain_lo coefficient (using calculated above Eoff_hi, Eoff_lo, and K): Gain_lo = ({(I3/I1) x (P1 + K x Eoff_hi)/ (P3 + K x Eoff_lo)} – 1) x 216 Note: All intermediate calculations should be per- formed with double precision, the last result rounded to the nearest integer. Eoff_hi, Gain_lo, and Eoff_lo are 16- bit signed coefficients. If a calculated value exceeds 16 bits, the part cannot be calibrated. In this case, assign the largest possible value, i.e., 0x7FFF for positive over- flow or 0x8000 for negative overflow. Phase Angle Calibration This calibration is intended to compensate for phase angle errors across the range of input loads. The MAXQ3180 uses four PA_n coefficients to calculate the compensation phase angle as a 3rd-order polynomial: compensation_phase_angle = PA_0 + (PA_1 x X) + (PA_2 x X 2) + (PA_3 x X3) Where X is proportional to the logarithm of raw IRMS. Full calibration of all four coefficients requires at least four measurements of the phase angle across the range. However, in most cases, only one coefficient PA_0 is needed that requires at least one phase angle measurement. For input signals, all three phase nominal voltages 220V should be applied. Only one current signal is applied to the phase input being calibrated. Other cur- rent inputs should be 0. Phase Angle Error Measurement This calibration procedure requires measuring the phase angle error of the meter’s output at the given current input level I_in. This can be done in two ways: (I) by reading raw RAM registers, or (II) by measuring pulse output errors at different power factors. Measurement Technique I: Measure Output Phase Angle Error by Reading RAM Registers 1) Measure average raw active power by reading the RAM registers several times. 2) Measure average raw reactive power by reading the RAM registers several times. 3) Calculate output phase angle: output_PA = atan(Reactive_raw_pwr/ Active_raw_pwr) 4) Calculate output phase angle error: output_PA_error = output_PA - input_PA Measurement Technique II: Measure Output Phase Angle Using Pulse Output Before the pulse output can be measured, the pulse configuration registers PLSCFG and THR1 (or THR2) must be properly configured. The pulse output should be set to active power. For details on how to set those registers, see the Power Gain Calibration section. 1) Apply input signal with power factor 1 (input phase angle 0 °) to the meter’s inputs. Measure pulse output error for active power, in percent. Denote it as Err00 for future reference. 2) Apply input signal with power factor 0.5L (input phase angle 60 °) to the meter’s inputs. Measure pulse output error for active power, in percent. Denote it as Err60 for future reference. 3) Calculate output phase angle error: output_PA_error = atan{(1/sqrt(3)) x (Err00 – Err60)/(100% + Err00)} Phase Angle Calibration Procedure 1) Clear PA_0, PA_1, PA_2, PA_3 coefficients being calibrated to 0x0000. 2) Phase angle error measurement. a) Apply current input signal of the RMS value close to IFS/21.5 to the phase input being calibrated. For example, typical target value is 100/2 1.5 = 35.36A, so reasonable input current is 30A or 40A. Measure the output phase angle error as described above. Denote applied current as I1 and measured phase angle error expressed in radians as PAerr1 for future reference. b) Measure average raw IRMS by reading the RAM register several times. Denote this as I1_raw for future reference. MAXQ3180 Low-Power, Multifunction, Polyphase AFE

c) Calculate pair of coordinates (x1,y1): y1 = (-PAerr1) x 216 3) Repeat the phase angle error measurement across the range. Repeat steps 2a to 2c using other input currents across the range. It is recommended to spread input current points uniformly in logarithmic scale, resulting in a set of point coordinates: (x1,y1), (x2,y2), . . . (xN,yN) The number of points N is not limited. 4) Calculate the coefficients (PA_n) of best fit polyno- mial curve. The calculation recipe depends on the order of polynomial. a) For zero-order curve (requires at least one point): PA_0 = average(y1,y2, . . . yN) PA_1 = PA_2 = PA_3 = 0 5) For first-order curve (requires at least two points): PA_1 = {∑ (xi-x_avg)(yi-y_avg)}/{∑ (xi-x_avg) PA_0 = y_avg - PA_1 x x_avg PA_2 = PA_3 = 0 where x_avg = average (x1,x2, . . . xN), y_avg = average (y1,y2, . . . yN) These two cases cover the majority of practical situa- tions. For higher order curves, the formulas are more complex, and the calculations can be performed using built-in functions of Microsoft Excel ® or MATLAB® from The MathWorks, Inc. Note that all intermediate calculations should be per- formed with double precision, the last result rounded to the nearest integer. Also note that PA_n are 16-bit signed coefficients. If the calculated value exceeds 16 bits, the phase angle cannot be calibrated. In this case, assign the largest possible value, i.e., 0x7FFF for posi- tive overflow or 0x8000 for negative overflow.

Application Information

Careful PCB layout significantly minimizes noise on the analog inputs, resulting in less noise on the digital I/O that could cause improper operation. The use of multi- layer boards is essential to allow the use of dedicated power planes. The area under any digital components should be a continuous ground plane if possible. Keep any bypass capacitor leads short for best noise rejec- tion and place the capacitors as close to the leads of the devices as possible. The MAXQ3180 must have separate ground areas for the analog (AGND) and digital (DGND) portions, con- nected together at a single point. CMOS design guidelines for any semiconductor require that no pin be taken above DVDD or below DGND. Violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft fail- ure (unintentional modification of memory contents). Voltage spikes above or below the device’s absolute maximum ratings can potentially cause a devastating IC latchup. Microcontrollers commonly experience negative volt- age spikes through either their power pins or general- purpose I/O pins. Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. Devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System designers must protect components against these transients that can corrupt system memory. Specific Design Considerations for MAXQ3180-Based Systems To reduce the possibility of coupling noise into the microcontroller, the system should be designed with a crystal or oscillator in a metal case that is grounded to the digital plane. Doing so reduces the susceptibility of the design to fast transient noise. Because the MAXQ3180 is designed for use in systems where high voltages are present, care must be taken to route all signal paths, both analog and digital, as far away as possible from the high-voltage components. It is possible to construct more elaborate metering designs using multiple MAXQ3180 devices. This can be accomplished by using a single SPI bus to connect all the MAXQ3180 devices together but using separate slave select lines to individually select each MAXQ3180. Additional Documentation Designers must ensure they have the latest MAXQ3180 errata documents. Errata sheets contain deviations from published specifications. A MAXQ3180 errata sheet for any specific device revision is available at www.maxim-ic.com/errata Low-Power, Multifunction, Polyphase AFE Microsoft Excel is a registered trademark of Microsoft Corp. MATLAB is a registered trademark of The MathWorks, Inc.

Low-Power, Multifunction, Polyphase AFE MAXQ3180 V0P SSEL SCLK MOSI MISO V1P V2P VN VCOMM I0P I0N I1P I1N I2P I2N VOLTAGE SENSE VA VB VC N CURRENT TRANSFORMER LCLBLA MASTER Typical Application Circuit

Low-Power, Multifunction, Polyphase AFE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 48 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. TOP VIEW MAXQ3180 TSSOP

254 AVDDI0N

263 V0PI0P

272 V1PINP

281 V2PVN

227 DVDDI2P

236 VCOMMI1N

218 RESETI2N

209 CFQAGND

1910 CFPXTAL2

1811 DGNDXTAL1

1712 DVDDIRQ

1613 MISOSSEL

245 VREFI1P

1514 MOSISCLK

Pin Configuration Package Information (For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 TSSOP U28+2 21-0066