MAXQ1004 MAXIM | Alldatasheet

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Technical content

Features

S High-Performance, Low-Power, 16-Bit MAXQ20 RISC Core S 6MHz Operation from an Internal Oscillator, Approaching 1MIPS per MHz S 1.7V to 3.6V Wide Operating Voltage S Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement S Up to Eight General-Purpose I/O Pins S 16-Level Hardware Stack S Optimized for C-Compiler (High-Speed/Density Code) S Memory 16KB Flash Memory, In-Application Programmable 640B of Data RAM 4KB of ROM JTAG/TAP Bootloader Mode for In-System Programming S Peripheral Features 10-Bit Delta-Sigma ADC, Internal Reference 1-Wire Slave Interface On-Chip Power-On Reset (POR)/Power-Fail Reset Overvoltage Detection Programmable Watchdog Timer Built-In Temperature Sensor, ±6NC S Secure Programming Interface Flash Programming Through Secure ROM Loader Secret Key Destruction on Mass Erase Permanent Loader Lockout Option Code and Secret Scrambling S Unique 64-Bit Serial Number S Low-Power Consumption 300nA (typ) in Stop Mode 3.75mA (typ) at 6MHz, 0.8mA (typ) at 1 MHz Low-Power Divide-by Modes (2, 4, 8, 256) 1-Wire/Interrupt Activity Detector +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. 1-Wire and MAXQ are registered trademarks of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. PART TEMP RANGE AES ENCRYPTION PIN- PACKAGE MAXQ1004-B01+ -40°C to +85°C Yes 16 TQFN- EP*

1-Wire and SPI Authentication Microcontroller TABLE OF CONTENTS

1-Wire and SPI Authentication Microcontroller Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on All Pins (including V DD), Continuous Output Current Continuous Power Dissipation (TA = +70NC) Single-Layer Board (derate 16.9mW/NC above +70NC) ..1349.1mW Multilayer Board (derate 25mW/ NC above +70NC) ....2000mW RECOMMENDED DC OPERATING CONDITIONS (VDD = 1.7V to 3.6V, T A = -40NC to +85NC, unless otherwise noted. Typical values are at T A = +25NC and VDD = 3.3V, unless oth - erwise noted.) (Note 1) ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD VRST 3.3 3.6 V 1.8V Internal Regulator VREG18 1.62 1.8 1.98 V Power-On Reset Voltage VPOR 1.0 1.42 V Power-Fail Reset Voltage VRST (Note 2) 1.64 1.695 V Power-Fail Warning Voltage VPFW (Notes 3, 4) 1.75 1.85 V Digital Overvoltage Detect VHV Monitors VREG18 2.4 2.8 V Supply Current (Note 5) IDD1 Device is executing from flash fSYS = 6MHz 3.5 mAIDD2 fSYS = 1MHz 0.8 Stop-Mode Current (Note 5) ISTOP1 TA = +25NC, CPU not backed up 5 FAISTOP2 TA = +85NC, CPU not backed up 7.5 ISTOP3 TA = +25NC, CPU backed up 6.5 ISTOP4 TA = +85NC, CPU backed up 9 DIGITAL I/O Input High Voltage (P0, RST) VIH 0.7 x VDD VDD V Input Hysteresis VIHYS (Note 6) 0.3 V Input Low Voltage (P0, RST) VIL VGND 0.3 x VDD V Output Low Voltage (P0, RST) (Note 7) VOL VDD = 3.6V, IOL = 4mA (Note 6) 0.4 VVDD = 1.85V, IOL = 4mA 0.4 Output High Voltage (P0, RST) VOH IOH = -2mA VDD -

0.4 VDD V

Input Leakage Current IL Internal pullup disabled -100 +100 nA Input/Output Pin Capacitance CIO (Note 6) 15 pF Input Low Current for All Pins IIL VIN = 0.4V, pullup enabled -70 FA RST Pullup Resistor RRST 65 Q20% kI

1-Wire and SPI Authentication Microcontroller RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = 1.7V to 3.6V, T A = -40NC to +85NC, unless otherwise noted. Typical values are at T A = +25NC and VDD = 3.3V, unless oth - erwise noted.) (Note 1) 10-BIT ADC PERFORMANCE (VDD = 1.7V to 3.6V, VREF = 1.845V, TA = -40NC to +85NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL OSCILLATOR Oscillator Frequency fOSC 5 6 7 MHz Oscillator Startup Time tOSC_RDY VREG18 = 1.8V (Note 6) 350 Fs Oscillator Duty Cycle (Note 6) 45 55 % NANOPOWER RING OSCILLATOR Nanopower Ring Frequency fNANO TA = +25NC 3 11 22 kHz Nanopower Ring Current INANO Typical at VDD = 3.0V, active during wake-up (Note 6) 120 400 nA Wakeup Timer Interval tWAKEUP 1/fNANO tNANO 65,535 x tNANO s FLASH MEMORY Flash Erase Time Mass erase 20 40 msPage erase 20 40 Flash Programming Time per Word tPROG 20 40 Fs Write/Erase Cycles 1000 Cycles Data Retention TA = +25NC 100 Years Analog Supply Voltage VAVDD VDD V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution 10 Bits ADC Clock Frequency fACLK fSYSCLK MHz ADC Clock Period tACLK 1/fACLK Fs AN0 Input Voltage Range VAN0 VGND VAVDD V Analog Input Capacitance CAIN 1 pF Integral Nonlinearity INL (Note 6) Q2 LSB Differential Nonlinearity DNL No missing codes over temperature Q1 LSB Offset Error VOS Q2 LSB ADC Active Current Consumption IADC ACLK = 6MHz, internal reference on, ADEN = 1 (Note 6) 100 150 FA ADC Setup Time tADC_SETUP 25 Fs ADC Output Latency tADC 1025 tACLK ADC Settling Time tADC_SETTLE Settling time due to channel, refer- ence or scale change (not produc- tion tested) 10 Fs ADC Throughput fADC fADC/tADC ksps TEMPERATURE SENSOR Temperature Sensor Setup Time tTSN_SETUP 25 Fs Temperature Sensor Error DTSN Q6 NC

1-Wire and SPI Authentication Microcontroller 10-BIT ADC PERFORMANCE (continued) (VDD = 1.7V to 3.6V, VREF = 1.845V, TA = -40NC to +85NC, unless otherwise noted.) SPI ELECTRICAL CHARACTERISTICS (VDD = 1.7V to 3.6V, T A = -40NC to +85NC, unless otherwise noted. AC electrical specifications are guaranteed by design and are not production tested.) Note 1: Specifications to -40NC are guaranteed by design and are not production tested. Note 2: The power-fail reset and POR detectors operate in tandem so one or both of these signals are active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is achieved. Note 3: The power-fail warning monitor and the power-fail reset monitor track each other with a typical delta between the two of 0.13V. Note 4: Writes to flash memory must not be performed when the supply voltage drops below the power-fail warning levels, as there is uncertainty in the duration of continuous power supply. The user application should check the status of the power- fail warning flag before writing to flash to ensure valid write operations. Note 5: Measured on the combined AVDD and V DD pins and the part not in reset. All inputs are connected to GND or V DD. Outputs do not source/sink any current. Note 6: Guaranteed by design and not production tested. Note 7: The maximum total current, IOH(MAX) and IOL(MAX), for all outputs combined should not exceed 35mA to satisfy the maxi - mum specified voltage drop. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10-BIT ADC REFERENCE VOLTAGE Internal Reference Voltage VIREF 1.845 Q5% V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI Master Operating Frequency 1/tMCK fSYSCLK/2 MHz SPI Slave Operating Frequency 1/tSCK fSYSCLK/4 MHz SPI I/O Rise/Fall Time tSPI_RF CL = 15pF, pullup = 560W 8.3 23.6 ns SCLK Output Pulse-Width High/Low tMCH, tMCL tMCK/2 - tSPI_RF ns MOSI Output Hold Time After SCLK Sample Edge tMOH tMCK/2 - tSPI_RF ns MOSI Output Valid to Sample Edge tMOV tMCK/2 - tSPI_RF ns MISO Input Valid to SCLK Sample Edge Rise/Fall Setup tMIS 25 ns MISO Input to SCLK Sample Edge Rise/Fall Hold tMIH 0 ns SCLK Inactive to MOSI Inactive tMLH tMCK/2 - tSPI_RF ns SCLK Input Pulse-Width High/Low tSCH, tSCL tSCK/2 ns SSEL Active to First Shift Edge tSSE tSPI_RF ns MOSI Input to SCLK Sample Edge Rise/Fall Setup tSIS tSPI_RF ns MOSI Input from SCLK Sample Edge Transition Hold tSIH tSPI_RF ns MISO Output Valid After SCLK Shift Edge Transition tSOV 2tSPI_RF ns SSEL Inactive tSSH tCK + tSPI_RF ns SCLK Inactive to SSEL Rising tSD tSPI_RF ns MISO Output Disabled After SSEL Edge Rise tSLH 2tCK + 2tSPI_RF ns

1-Wire and SPI Authentication Microcontroller SPI Master Communications Timing SPI Slave Communications Timing SSEL (SAS = 0) SCLK CKPOL/CKPHA SCLK CKPOL/CKPHA MOSI MISO LSB LSB SHIFT SAMPLE SHIFT SAMPLE tMCK tMCH tMOH tMIS tMOV tRF tMLH tMIH tMCL MSB MSB-1 MSB MSB-1 SHIFT SAMPLE SHIFT SAMPLE SSEL (SAS = 1) MOSI MISO tSSE tSCK tSCH tSCL tSIS tSOV tSLH tSSH tSD tRF tSIH MSB MSB-1 MSB MSB-1 LSB LSB SCLK CKPOL/CKPHA SCLK CKPOL/CKPHA

1-Wire and SPI Authentication Microcontroller Pin Configuration Pin Description DQ P0.1/INT1/MISO RST AN0 P0.6/INT6/TMS AVREF 1 2 GND 12 11 9 REG18 VDD + P0.5/INT5/TDI/T0G P0.4/INT4/TCK/T0 P0.3/INT3/SSEL P0.2/INT2/SCLKEP P0.0/INT0/MOSI P0.7/INT7/TDO AVDD TQFN (4mm × 4mm) TOP VIEW MAXQ1004 PIN NAME FUNCTION POWER PINS 11 AN0 Analog Input 0. This pin is the analog input to the ADC. 12 AVREF Analog Voltage Reference. Do not connect anything external to this pin. 13 AVDD Analog Supply Voltage. Directly connect AVDD to DVDD.

14 GND Digital Ground

15 REG18 Regulator Capacitor. This pin must be connected to ground through an external 1 FF low ESR (< 5I) capacitor. 16 VDD Digital Supply Voltage. +3.3V nominal supply voltage. — EP Exposed Pad. Connect the EP to the ground plane. RESET AND STATUS PINS

1 RST

Active-Low Reset. This bidirectional pin recognizes external active-low reset inputs and employs an internal pullup resistor to allow for a combination of wired-OR external reset sources. This pin also acts as an output when the source of the reset is internal to the device (e.g., watchdog timer, power-fail, etc.). In this case, the pin is low while the processor is in a reset state, and it returns high as the processor exits this state.

1-Wire and SPI Authentication Microcontroller Pin Description (continued) Block Diagram MAXQ1004 16KB FLASH MEMORY 640B DATA SRAM 4KB UTILITY ROM WATCHDOG TIMER GND +1.7V TO +3.6V INTERNAL 6MHz OSCILLATOR RANDOM-NUMBER GENERATOR AES ENCRYPTION ENGINE TEMP SENSOR INTERNAL REFERENCE 10-BIT ADC VOLTAGE MONITOR MAXQ RISC CPU GPIO (UP TO 8) SPI JTAG 1-Wire INTERFACE TIMER 0 PIN NAME FUNCTION GENERAL-PURPOSE I/O PINS 3–10 P0.0–P0.7, INT0–INT7, MOSI, MISO, SCLK, SSEL, TCK, TDI, TMS, TDO General-Purpose, Digital I/O, Type D Port/SPI Interface/JTAG Interface/External Edge- Selectable Interrupt. This port functions as 8-bit I/O and as an alternate interface to external interrupts. Each interrupt can be individually enabled and the active edge can be selected. The default reset condition of the pins is as a weak pullup input. To drive port 0 as output, the port direction register must be programmed to enable output. P0.7–P0.4 default to their JTAG function on any reset. PIN PORT EXTERNAL INTERRUPT SPECIAL FUNCTION 3 P0.0 INT0 MOSI: Master Out-Slave In (SPI) 4 P0.1 INT1 MISO: Master In-Slave Out (SPI) 5 P0.2 INT2 SCLK: Slave Clock (SPI) 6 P0.3 INT3 SSEL: Active-Low Slave Select (SPI) 7 P0.4 INT4 TCK: Test Clock (JTAG)/T0 8 P0.5 INT5 TDI: Test Data In (JTAG)/T0G 9 P0.6 INT6 TMS: Test Mode Select (JTAG) 10 P0.7 INT7 TDO: Test Data Out (JTAG) 2 DQ 1-Wire Slave Interface, I/O. This 5V tolerant, open-drain I/O pin serves as both transmit and receive pin for the 1-Wire interface. The DQ pin requires an external pullup resistor, the value of which is determined by the speed mode.

1-Wire and SPI Authentication Microcontroller Detailed Description The MAXQ1004 is a low-power, high-performance, 16-bit MAXQ microcontroller providing the high security and reliability demanded in today’s portable electronics, bat- tery chargers, and battery packs. An ISO/IEC 9797-1 standards-based authentication protocol is available as standard application code. A 1-Wire communication interface minimizes battery- pack connections required to authenticate and monitor battery health. The 1-Wire I/O pin (DQ) can wake the device from low-power stop mode. In stop mode, power is supplied only to the circuitry required to wake up the slave microcontroller. During stop mode, 512 bytes of data memory are preserved, with an option to preserve the CPU state and the remaining 128 bytes of data memory. MAXQ Core Architecture The microcontroller is based on a low-power implemen - tation of the 16-bit MAXQ family of RISC cores. The core supports the Harvard memory architecture with separate 16-bit program and data address buses. A fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. The core is implemented as a pipelined pro- cessor with performance approaching 1MIPS per MHz. The 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. The accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (ALU). Execution of instructions is triggered by data transfer between functional register modules or between a func - tional register module and memory. Because data move- ment involves only source and destination modules, circuit-switching activities are limited to active modules only. For power-conscious applications, this approach localizes power dissipation and minimizes switching noise. The modular architecture also provides a maxi - mum of flexibility and reusability that is important for a microprocessor used in embedded applications. The MAXQ instruction set is highly orthogonal. All arith - metical and logical operations can use any register in conjunction with the accumulator. Data movement is supported from any register to any other register. Memory is accessed through specific data-pointer regis- ters with automatic increment/decrement support. Memory Organization There are three distinct memory areas: registers, pro - gram memory, and data memory. All registers are located on-chip. The device contains built-in program and data memory, including:

  • 16KB flash memory, in-application programmable
  • 640B of data RAM
  • 4KB of ROM Program flash memory is arranged in 1024-byte pages that can be individually erased and programmed through the use of utility ROM functions. Utility ROM The utility ROM is a block of internal ROM that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software. These include the following:
  • In-system programming using a bootstrap loader
  • Test routines (internal memory tests, memory loader, etc.)
  • User-callable routines for in-application flash program- ming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of application code, or to one of the special routines mentioned. Routines within the utility ROM are user-accessible and can be called as subroutines by the application software. More information on the utility ROM functions is contained in the MAXQ1004 User’s Guide. Some applications require protection against unau - thorized viewing of program code memory. For these applications, access to in-system programming, in- application programming, or in-circuit debugging func - tions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h–001Fh. A single password lock (PWL) bit is implemented in the SC register. When the PWL is set to one (POR default) and the contents of the memory at addresses 0010h–001Fh are any value other than FFh or 00h, the password is required to access the utility ROM, includ - ing in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without the password. The password is automatically set to all ones following a mass erase.

1-Wire and SPI Authentication Microcontroller Loading Flash Memory with the Bootstrap Loader An internal bootstrap loader allows the device to be reloaded over a simple JTAG interface. As a result, soft - ware can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. If in-system programmability is not required, a commercial gang programmer can be used for mass programming. In-Application Flash Programming From user-application code, internal flash memory can be programmed/erased by calling internal ROM utility functions from either C or assembly language. Memory protection is enforced by the ROM utility functions. The function declarations below show examples of some of the ROM utility functions provided for in-application flash memory programming. /* Write one 16-bit word to code address ‘dest’. * Dest must be aligned to 16 bits. * Returns 0 = failure, 1 = OK. int flash_write16(uint16_t dest, uint16_t data); To erase, the following function would be used: /* Erase the given Flash page * addr: Flash offset (anywhere within page) int flash_erasepage(uint16_t addr); Code Scrambling Automated code scrambling protects user-code mem - ory against attempts to determine the code contents. The proprietary scrambling algorithm is transparent to the user and still allows in-application programming. Address shuffling prevents well-known startup code from always being at the known location 0000h and interrupt vector code at known locations. This obfuscates confi - dential software and makes the application secure from hackers and copiers. ADC The 10-bit delta-sigma analog-to-digital converter (ADC) allows the application to measure external voltages, most commonly the voltage of the batteries driving V DD. The analog input, AN0, can be optionally scaled by 50% for direct supply voltage measurement. The ADC value saturates (all data bits read 1) when the input voltage exceeds the maximum allowable ADC reference voltage. The internal temperature sensor is measured by the ADC when selected. Each conversion can choose its own reference from AVDD or the internal reference. Data can be retrieved in either left-justified or right-justified format, giving the application direct control on data format. A conversion takes 1025 ADCCLK cycles to com - plete. The ADCCLK is derived from the system clock with divide ratio defined by the ADC clock-divider bits (ADCCLK). Therefore, with 1025 ADCCLK to acquire one data, the fastest ADC rate = Sysclk/1025 (ADCCLK = 0h). See Figure 1. Temperature Sensor An integrated temperature sensor measures the internal temperature of the device with an error of Q6NC. The tem- perature sensor is connected to channel 1 of the ADC. To read the temperature sensor, select ADCH to 1. Nanopower Ring Wake-Up Timer A nanopower-ring oscillator can be used to drive a wake-up timer that causes the device to exit stop mode after a user-selectable time period. The wake-up timer is software programmable in 16-bit steps of the nanopower ring clock up to approximately 8 seconds. Serial Number/Device ID Each device has a factory-programmed, unique, 64-bit device identification number (ID). This ID ensures device traceability and serves as an input to the device’s authentication protocol. The first 8 bits of the device ID are a 1-Wire family code that is the same for all MAXQ1004 devices. The next 48 bits are a factory-programmed unique serial number. Even if multiple devices are used in a 1-Wire network, the unique, 48-bit serialization field prevents any address conflict, allowing communication with each device indi - vidually. The last 8 bits are a factory-programmed cyclic redundancy check (CRC) of the first 56 bits. The 1-Wire CRC is generated using a polynomial generator consist - ing of a shift register and XOR gates. The polynomial is x8 + x5 + x4 + 1.

provides AES engine operation status and option control.

  • 128-bit key size—55 cycles (9.2µs at 6MHz)
  • 192-bit key size—70 cycles (12.0µs at 6MHz)
  • 256-bit key size—75 cycles (12.5µs at 6MHz) An optional jitter injection feature reduces the effec - tiveness of differential power analysis (DPA) attacks against the device. Adding jitter causes random delays in both the start and ending times of the calculation, confounding attempts to determine the values in the AES operation by measuring minute power fluctuations. When active, the feature adds a variable random delay of 0 to 30 clock cycles to AES calculations. This is accom - plished by randomly adding 0 to 15 clock cycles before the AES operation is started, and adding 0 to 15 clock cycles after the operation is complete. Watchdog Timer The watchdog timer functions as the source of both the timer timeout and the watchdog timer reset. The timeout period can be programmed in a range of 212 to 229 sys- tem clock cycles. An interrupt is generated when the time- out period expires, if the interrupt is enabled. All watchdog timer resets follow the programmed interrupt timeouts by 512 clock cycles. If the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. Table 1 shows values that demonstrate the various interrupt timeouts based on an internal clock frequency of 6MHz.

Figure 1. ADC Block Diagram

  • 13-bit timer/counter
  • 16-bit timer/counter
  • 8-bit timer with autoreload
  • 2 8-bit timer/counters Serial Peripherals Serial Peripheral Interface (SPI) The integrated SPI is an independent serial communi - cation channel that communicates synchronously with peripheral devices in a multiple-master or multiple-slave system. The interface allows access to a 4-wire, full- duplex serial bus and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum SPI master transfer rate is Sysclk/2. When operating as an SPI slave, the device can support up to Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit or 16-bit value, MSB first. In addition, the SPI module supports configuration of an active SSEL state through the slave active select. 1-Wire Bus System The 1-Wire bus is a system that has a single bus master and one or more slaves. This microcontroller is always a slave device in any system. The bus master is typi - cally another microcontroller. The discussion of this bus system is broken down into three topics: hardware con - figuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. Refer to Application Note 937: Book of iButton® Standards for a more detailed description the 1-Wire network and protocols. The device permits the use of lower 1-Wire voltage levels (as low as 1.7V) to support the device’s full operating voltage, but can still be connected to a regular 1-Wire bus of up to 6V. Hardware Configuration The 1-Wire bus has only a single data line (DQ); all devices on the bus must be able to drive it at the appro - priate time. This means that each device attached to the 1-Wire bus must have open-drain or high-impedance outputs. The 1-Wire port is open drain. Both the standard and overdrive communication speed of 15.4kbps (max) and 111kbps (max), respectively, are supported. The value of the pullup resistor primar - ily depends on the network size and load conditions. Recommended pullup resistor values can be found in Table 4-1 of Application Note 937: Book of iButton® Standards. The idle state for the 1-Wire bus is high. If, for any rea - son, a transaction needs to be suspended, the bus must remain in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120Fs (standard speed), one or more devices on the bus can be reset.

Table 1. Watchdog Interrupt Timeout

1-Wire and SPI Authentication Microcontroller Slave Functionality The 1-Wire slave provides three functions. The first is that of a totally independent slave function, which can be externally accessed at any time to verify its identity. The 1-Wire front-end functions in an identical fashion to that of the DS1990 serial ID to verify the serial ID number. The bus master must provide one of the ROM function commands:

  • Read ROM
  • Match ROM
  • Search ROM
  • Skip ROM
  • Overdrive-Skip ROM
  • Overdrive-Match ROM
  • Resume The second function is that of a 1-Wire that includes full bidirectional data flow and data flow control. The 1-Wire functions that become accessible after a ROM function command is successfully executed initiate communica - tions with the microcontroller through the use of specific 1-Wire commands:
  • Read I/O Buffer
  • Write I/O Buffer
  • Read Command Buffer
  • Write Command Buffer
  • Read Command Buffer Extended
  • Write Command Buffer Extended
  • Status Register Read
  • Status Register Write The third function controls the operation of the 1-Wire interface:
  • 1-Wire Micro Reset And the remaining are 1-Wire run commands:
  • Start Program
  • Continue Program
  • Write Command Buffer Extended and Start Program
  • Write Command Buffer Extended and Continue Program Operating Modes The low-power mode of operation is stop mode. In this mode, CPU state and memories are preserved, but the CPU is not actively running. Wake-up sources include external I/O interrupts, the power-fail warning interrupt, a valid 1-Wire command received, or a power-fail reset. Any time the microcontroller is in a state where code does not need to be executed, the user software can enter stop mode. An even lower stop mode is the data-retention mode, in which the CPU is not active. When the data-retention mode option is invoked (DRET = 1) and the regula - tor is disabled (REGEN = 0), only the first 512 bytes of data memory is retained (data memory word offset 0000h–00FFh). CPU status and 1-Wire/AES memory are powered down and contents are lost. A POR occurs when exiting stop mode from data-retention mode. This mode can be exited from any of the following enabled interrupt sources:
  • Enabled external interrupts
  • External reset
  • Enabled PFW interrupt
  • Valid 1-Wire command received
  • Wake-up timer The wake-up timer causes the device to exit stop mode after a user-selectable time period. The power-fail moni - tor is always on during normal operation. However, it can be selectively disabled during stop mode using the pow- er-fail monitor disable (PFD) bit in the PWCN register. By default, the power-fail monitor function is enabled during stop mode. If power-fail monitoring is disabled (PFD = 1) during stop mode, the circuitry responsible for generat - ing a power-fail warning or reset is shut down and neither condition is detected. Thus, the V DD < V RST condition does not invoke a reset state. However, in the event that VDD falls below the POR level, a POR is generated. The power-fail monitor is enabled prior to stop mode exit and before code execution begins. If a power-fail warning condition (VDD < VPFW) is then detected, the power-fail interrupt flag is set on stop mode exit. If a power-fail con- dition is detected (VDD < VRST), the CPU goes into reset. The 1-Wire peripheral can operate in a special mode that draws minimal power, yet can serve as a wake- up source to bring the device out of stop mode. If the 1-Wire peripheral is required to run in stop mode, it can be enabled so a regular 1-Wire reset pulse briefly wakes up the 1-Wire controller. The 1-Wire controller then deter- mines if it was addressed. If so, the 1-Wire controller wakes up the CPU from stop mode. If the microcontroller is not being addressed, then stop mode continues and the 1-Wire controller is powered down again, and the device returns to its lowest power state. The device does not respond to an overdrive reset pulse in stop mode.

1-Wire and SPI Authentication Microcontroller In-Circuit Debug Embedded debugging capability is available through the JTAG-compatible test access port (TAP). Embedded debug hardware and embedded ROM firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. See Figure 2. The in-circuit debug features include the following:

  • Hardware debug engine
  • Set of debug service routines stored in the utility ROM The embedded hardware debug engine is an indepen - dent hardware block in the microcontroller. The debug engine can monitor internal activities and interact with selected internal registers while the CPU is executing user code. Collectively, the hardware and software fea - tures allow two basic modes of in-circuit debugging:
  • Background mode allows the host to configure and set up the in-circuit debugger while the CPU continues to execute the application software at full speed. Debug mode can be invoked from background mode.
  • Debug mode allows the debug engine to take control of the CPU, providing read/write access to internal registers and memory and single-step trace operation. Applications Information Grounds and Bypassing Careful PCB layout significantly minimizes crosstalk among the high-speed external address/data bus sig - nals and with digital I/O that could cause improper operation. The use of multilayer boards is essential to allow the use of dedicated power planes. Bypass V DD on each microcontroller with a 0.1 FF capacitor located as close as possible to the pin. Design Guidelines for ESD Protection CMOS design guidelines for any semiconductor require that no pin be taken above V DD or below ground. Violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (unintentional modification of memory contents). Voltage spikes above or below the device’s absolute maximum ratings can cause a temporary brownout of the internal power rail, possibly corrupting memory. Microcontrollers commonly experience negative volt - age spikes through either their power pins or general- purpose I/O pins. Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. Devices such as keypads can conduct electrostatic discharges directly into the micro - controller and seriously damage the device. System designers must protect components against these tran - sients that can corrupt system memory. In a practical application, it is difficult to remove all volt - ages above VDD or below ground. Undershoots of 0.3V can be tolerated by the microcontroller, and 5V tolerant pins can accept up to 5.5V. Figure 3 demonstrates a diode protection scheme that can be used to protect the I/O pins of a microcontroller. The scheme relies on the use of a Schottky diode and current limiting resistor to reduce the effect of current spikes on the device. When the voltage approaching the device pin exceeds V DD or GND by more than 0.1V to 0.2V, the Schottky diodes become forward biased, conducting the excess voltage away from the device pins. The current limiting resistors also help dampen the effect of the voltage spike on the microcontroller.Figure 2. In-Circuit Debugger TAP CONTROLLER CPU DEBUG ENGINE DEBUG SERVICE ROUTINES (UTILITY ROM) CONTROL BREAKPOINT ADDRESS DATA MAXQ1004 TMS TCK TDI TDO

below the maximum drive current of the sourcing device. www.maxim-ic.com/microcontrollers.

  • This MAXQ1004 data sheet, which contains electrical/ timing specifications, pin descriptions, and package information.
  • The MAXQ1004 revision-specific errata sheet (www.maxim-ic.com/errata).
  • The MAXQ1004 User’s Guide, which contains detailed information on core features and operation, including programming. Development and Technical Support Maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following:
  • Compilers
  • In-circuit emulators
  • Integrated Development Environments (IDEs)
  • Serial-to-JTAG converters for programming and debugging. A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. For technical support, go to https://support.maxim-ic. com/micro. Typical Application Circuit The 1-Wire interface can be used to authenticate a 3-contact battery pack and also measure the battery voltage and temperature. See Figure 4 for a typical appli- cation circuit.

Figure 3. I/O Protection

1-Wire and SPI Authentication Microcontroller

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Figure 4. Typical Application Circuit PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

16 TQFN-EP T1644+4 21-0139

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAXQ1004 1-Wire and SPI Authentication Microcontroller

Revision History

0 4/10 Initial release —