MAX800

MAX691A MAXIM | Alldatasheet

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The MAX691A/MAX693A/MAX800L/MAX800M micro- processor (µP) supervisory circuits are pin-compatible upgrades to the MAX691, MAX693, and MAX695. They improve performance with 30µA supply current, 200ms typ reset active delay on power-up, and 6ns chip- enable propagation delay. Features include write pro- tection of CMOS RAM or EEPROM, separate watchdog outputs, backup-battery switchover, and a RESET out- put that is valid with V CC down to 1V. The MAX691A/ MAX800L have a 4.65V typical reset-threshold voltage, and the MAX693A/MAX800M’s reset threshold is 4.4V typical. The MAX800L/MAX800M guarantee power-fail accuracies to ±2%. Computers Controllers Intelligent Instruments Automotive Systems Critical µP Power Monitoring ' 200ms Power-OK/Reset Timeout Period ' 1µA Standby Current, 30µA Operating Current ' On-Board Gating of Chip-Enable Signals, 10ns Max Delay ' MaxCap ™ or SuperCap™ Compatible ' Guaranteed RREESSEETT Assertion to VCC = +1V ' Voltage Monitor for Power-Fail or Low-Battery Warning ' Power-Fail Accuracy Guaranteed to ±2% (MAX800L/M) ' Available in 16-Pin Narrow SO and Plastic DIP Packages Ordering Information continued on last page. * Dice are specified at TA = +25 °C, DC parameters only. MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits RESET RESET WDO CE INGND V CC VOUT VBATT TOP VIEW MAX691A MAX693A MAX800L MAX800M CE OUT WDI PFO PFIOSC SEL OSC IN LOW LINE BATT ON DIP/SO MAX691A MAX693A MAX800L MAX800M VOUT VCC BATT ON CE OUT CE IN WDI PFO RESET VBATT PFI GND OSC IN OSC SEL ADDRESS DECODE AUDIBLE ALARM REGULATOR+8V 0.1µF CMOS RAM A0-A15 I/O NMI RESET µP LOW LINE WDO SYSTEM STATUS INDICATORS NO CONNECTION 0.47F* 1N4148 *MaxCap 61 4 19-0094; Rev 7a; 12/96 PART MAX691A CPE MAX691ACSE MAX691ACWE 0°C to +70°C 0°C to +70°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE

16 Plastic DIP

16 Narrow SO

16 Wide SO

MAX691AEJE -40°C to +85°C 0°C to +70°C Dice*

16 CERDIP

MAX691AESE -40°C to +85°C -40°C to +85°C 16 Plastic DIP MAX691AEWE -40°C to +85°C 16 Wide SO MAX691AMJE -55°C to +125°C 16 CERDIP SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of The Carborundum Corp. For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.

TA = TMIN + TMIN MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Terminal Voltage (with respect to GND) Input Current Continuous Power Dissipation (TA = +70° C) Operating Temperature Ranges VBATT - 0.15 MAX69_AC, MAX800_C 0.8 1.2 VBATT = 4.5V, IOUT = 20mA µA-1.0 0.02VBATT + 0.2V ≤ VCC VBATT Standby Current (Note 3) -0.1 0.02 µA VCC < VBATT - 1.2V VBATT = 2.8V Supply Current in Battery-Backup Mode (Excludes I OUT) (Note 2) VBATT = 2.8V, IOUT = 10mA V0 5.5 CONDITIONS Operating Voltage Range, VCC, VBATT (Note 1) VBATT = 4.5V 0.04 1 µA30 100 Supply Current in Normal Operating Mode (Excludes I OUT) VVOUT in Battery-Backup Mode VBATT - 0.25 VBATT = 2.8V Ω VBATT - 0.3 VBATT-to-VOUT On-Resistance UNITSMIN TYP MAXPARAMETER TA = +25° C VCC > VBATT - 1V TA = TMIN + TMIN VBATT = 2.0V, IOUT = 5mA TA = +25° C TA = TMIN + TMIN VBATT = 2.0V VCC = 4.5V IOUT = 250mA VCC - 0.02 VCC - 0.05IOUT = 25mA MAX69_AC/AE, MAX800_C/EIOUT = 210mA VCC - 0.2 VCC - 0.35 VCC - 0.2 VCC - 0.3 V VCC - 0.40 VCC - 0.17 VCC - 0.3V VOUT Output MAX69_AE, MAX800_C/E MAX69_AC MAX69_A/M MAX69_AE, MAX800_E 0.8 1.4 MAX69_A/M 0.8 1.6 ΩVCC = 4.5VVCC-to-VOUT On-Resistance VVBATT - 0.3 Power-upBattery Switchover Threshold VBATT + 0.3 Power-down

MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits MAX691A, MAX800L mA7 20 –RESET Output Short-Circuit Current V 3.5 RESET Output Voltage 0.1 0.4 0.004 0.3 ns100Minimum Watchdog Input Pulse Width Clock Cycles1024 Watchdog Timeout Period, External Clock (Note 4) 4096 ms70 100 140 Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 Clock Cycles2048Reset Active Timeout Period, External Clock (Note 4) ms140 200 280Reset Active Timeout Period, Internal Oscillator ns800LOW LINE-to-RESET Delay µs80VCC to RESET Delay MAX693A, MAX800M CONDITIONS mV15Reset Threshold Hysteresis V 4.30 4.45 Reset Threshold Voltage 4.55 4.70 4.25 4.40 4.50 4.50 4.65 4.75 UNITSMIN TYP MAXPARAMETER Output source current ISOURCE = 1.6mA, VCC = 5V ISINK = 3.2mA, VCC = 4.25V ISINK = 50µA, VCC = 1V, VBATT = 0V, VCC falling VIL = 0.8V, VIH = 0.75 x VCC Short period Long period Short period Long period MAX800M, TA = +25° C, VCC falling Power-up Power-up MAX800L, TA = +25° C, VCC falling Power-down ELECTRICAL CHARACTERISTICS (continued) unless otherwise noted.) RESET Output Voltage Low (Note 5) ISINK = 3.2mA 0.1 0.4 V ISINK = 3.2mA, VCC = 4.25V 0.4LOW LINE Output Voltage ISOURCE = 1µA, VCC = 5V 3.5 V LOW LINE Output Short-Circuit Current Output source current 1 15 100 µA ISINK = 3.2mA 0.4WDO Output Voltage ISOURCE = 500µA, VCC = 5V 3.5 V WDO Output Short-Circuit Current Output source current 3 10 mA VIH 0.75 x VCCWDI Threshold Voltage (Note 6) VIL 0.8 V WDI = 0V -50 -10WDI Input Current WDI = VOUT 20 50 µA sec mV60Battery Switchover Hysteresis ISINK = 25mA V0.7 1.5 BATT ON Output Low Voltage ISINK = 3.2mA 0.1 0.4 Source current µA1 15 100 BATT ON Output Short-Circuit Current Sink current mA60 RESET AND WATCHDOG TIMER

MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits MAX69_AC/AE/AM, VCC = 5V µA0.10 ±5OSC IN Leakage Current µs12RESET-to-CE OUT Delay 2.7 CE OUT Output Voltage High (Reset Active) 3.5 ns6 10CE IN-to-CE OUT Propagation Delay (Note 8) mA0.1 0.75 2.0CE OUT Short-Circuit Current (Reset Active) Ω75 150CE IN-to-CE OUT Resistance (Note 7) µA±0.005 ±1CE IN Leakage Current 60PFI-to-PFO Delay µs25 µA1 15 100PFO Output Short-Circuit Current MAX800_C/E, VCC = 5V CONDITIONS 3.5PFO Output Voltage V0.4 nA±0.01 ±25PFI Leakage Current UNITSMIN TYP MAXPARAMETER OSC SEL = 0V Power-down VCC = 0V, VBATT = 2.8V, IOUT = 1µA VCC = 5V, IOUT = -100µA 50Ω source impedance driver, CLOAD = 50pF Disable mode, –CE OUT = 0V Enable mode Disable mode ISOURCE = 1µA, VCC = 5V ISINK = 3.2mA VIN = 20mV, VOD = 15mV VIN = -20mV, VOD = 15mV Output source current Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V. Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding IOUT typically goes to 10µA when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region. Note 3: “+” = battery-discharging current, “--” = battery-charging current. Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. Note 5: RESET is an open-drain output and sinks current only. Note 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function. Note 7: The chip-enable resistance is tested with VCC = +4.75V for the MAX691A/MAX800L and VCC = +4.5V for the MAX693A/MAX800M. CE IN = CE OUT = VCC / 2. Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. ELECTRICAL CHARACTERISTICS (continued) unless otherwise noted.) kHz50OSC IN Frequency Range µA10 100OSC SEL Input Pull-Up Current µA10 100OSC INInput Pull-Up Current OSC SEL = 0V OSC SEL = 0V OSC SEL = VOUT or floating, OSC IN = 0V VVOUT - 0.3 VOUT - 0.6VIH 3.65 2.00 OSC IN External Oscillator Threshold Voltage VIL kHz100OSC IN Frequency with External Capacitor OSC SEL = 0V, COSC = 47pF V POWER-FAIL COMPARATOR CHIP-ENABLE GATING INTERNAL OSCILLATOR

MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits -60 120 150 VCC SUPPLY CURRENT vs. TEMPERATURE (NORMAL OPERATING MODE) MAX691A TOC-01 TEMPERATURE (°C) VCC SUPPLY CURRENT (µA) -30 0 90 VCC = 5V VBATT = 2.8V PFI, CE IN = 0V -60 120 150 BATTERY SUPPLY CURRENT vs. TEMPERATURE (BATTERY-BACKUP MODE) MAX691A TOC-02 TEMPERATURE (°C) BATTERY SUPPLY CURRENT (µA) 0.5 -30 0 90 1.5 VCC = 5V VBATT = 2.8V NO LOAD 120 -60 120 150 180 CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE 100 MAX691A TOC-03 TEMPERATURE (°C) CE ON-RESISTANCE (Ω ) -30 0 90 VCC = 4.75V VBATT = 2.8V V CE IN = VCC/2 -60 120 150 VBATT to VOUT ON-RESISTANCE vs. TEMPERATURE MAX691A TOC-04 TEMPERATURE (°C) VBATT-to-VOUT ON-RESISTANCE (Ω ) -30 0 90 VCC = 0V VBATT = 2.8V VBATT = 2.0V VBATT = 4.5V 4.75 4.30 -60 120 150 RESET THRESHOLD vs. TEMPERATURE MAX691A TOC-07 TEMPERATURE (°C) RESET THRESHOLD (V) 4.45 -30 0 90 4.65 4.40 4.35 4.50 4.70 4.55 4.60 VBATT = 2.8V MAX691A MAX800L MAX693A MAX800M 1.2 0.6 -60 120 150 VCC to VOUT ON-RESISTANCE vs. TEMPERATURE MAX691A TOC-05 TEMPERATURE (°C) VCC-to-VOUT ON-RESISTANCE (Ω ) 0.8 -30 0 90 1.0 0.7 0.9 1.1 VCC = 5V, VBATT = 0V 1.50 -60 120 150 PFI THRESHOLD vs. TEMPERATURE MAX691A TOC-06 TEMPERATURE (°C) PFI THRESHOLD (V) 0.50 -30 0 90 1.00 0.25 0.75 1.25 VCC = +5V, VBATT = 0V NO LOAD ON PFO 600 -60 120 150 RESET OUTPUT RESISTANCE vs. TEMPERATURE MAX691A TOC-08 TEMPERATURE (°C) RESET OUTPUT RESISTANCE (Ω ) 200 -30 0 90 100 500 300 400 VCC = 5V, VBATT = 2.8V SOURCING CURRENT VCC = 0V, VBATT = 2.8V SINKING CURRENT -60 120 150 RESET DELAY vs. TEMPERATURE 230 MAX691A TOC-09 TEMPERATURE (°C) RESET DELAY (ms) 190 170 -30 0 90 210 220 180 200 VCC = 0V TO 5V STEP VBATT = 2.8V (TA = +25° C, unless otherwise noted.)

MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits (TA = +25° C, unless otherwise noted.) BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE MAX691A TOC-10 VCC (V) IBATT (µA) 1 2 5 VBATT = 2.8V IOUT = 0A 100 0.1 WATCHDOG AND RESET TIMEOUT PERIOD vs. OSC IN TIMING CAPACITOR (COSC) MAX691A TOC-11 COSC (pF) WATCHDOG AND RESET TIMEOUT PERIOD (sec) 100 10 1000 VCC = 5V VBATT = 2.8V LONG WATCHDOG TIMEOUT PERIOD SHORT WATCHDOG TIMEOUT PERIOD RESET ACTIVE TIMEOUT PERIOD 0 300 CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE MAX691A TOC-12 CLOAD (pF) PROPAGATION DELAY (ns) 150 50 100 250 200 VCC = 5V CE IN = 0V TO 5V DRIVER SOURCE IMPEDANCE = 50Ω 1000 VCC to VOUT vs. OUTPUT CURRENT (NORMAL OPERATING MODE) 100 MAX691A TOC-13 IOUT (mA) VCC to VOUT (mV) 100 10 1000 VCC = 4.5V VBATT = 0V SLOPE = 0.8Ω 1000 VBATT to VOUT vs. OUTPUT CURRENT (BATTERY-BACKUP MODE) 100 MAX691A TOC-14 IOUT (mA) VBATT to VOUT (mV) 1 100 VCC = 0V VBATT = 4.5V SLOPE = 8Ω LO VCC to LOW LINE AND CE OUT DELAY MAX691A TOC-15 LOW LINE VCC RESET THRESHOLD LO HI HI HI LO CE OUT RESET 12µs 800ns 80µs

MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits NAME FUNCTION 1 VBATT Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GND.

2 VOUT

Output Supply Voltage. When VCC is greater than VBATT and above the reset threshold, VOUT connects to VCC. When VCC falls below VBATT and is below the reset threshold, VOUT connects to VBATT. Connect a 0.1µF capacitor from VOUT to GND. Connect VOUT to VCC if no backup battery is used. PIN 3 VCC Input Supply Voltage, 5V input. 4 GND Ground. 0V reference for all signals.

8 OSC SEL

Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1). OSC SEL has a 10µA internal pull-up.

7 OSC IN

External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from VOUT to OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3). 6 LOW LINE LOW LINE output goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold.

5 BATT ON

Battery On Output. When VOUT switches to VBATT, BATT ON goes high. When VOUT switches to VCC, BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current require- ments greater than 250mA. 13 CE IN Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or VOUT. 12 CE OUT Chip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE IN is low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs first.

11 WDI

Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time- out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran- sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between V OUT and GND, which sets it to mid-supply when left unconnected. 10 PFO Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry. 9 PFI Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. When PFI is not used, connect PFI to GND or VOUT . 16 RESET RESET is an active-high output. It is open drain, and the inverse of RESET. 15 RESET RESET Output goes low whenever VCC falls below the reset threshold. RESET will remain low typically for 200ms after VCC crosses the reset threshold on power-up.

14 WDO

Watchdog Output. If WDI remains high or low longer than the watchdog timeout period,WDO goes low and reset is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. The MAX691A/MAX693A/MAX800L/MAX800M’s RESET and RESET outputs ensure that the µP (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors dur - ing power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, –RESET sources 1.6mA at typically V OUT - 0.5V. RESET output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to V CC = 1V, and an external 10k Ω pull-down resistor on RESET insures that it will be valid with V CC down to GND (Figure 1). As V CC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the R DS(ON) and the saturation voltage. The 10k Ω pull- down resistor insures the parallel combination of switch plus resistor is around 10k Ω and the output saturation voltage is below 0.4V while sinking 40 µA. When using a 10k Ω external pull-down resistor, the high state for RESET output with V CC = 4.75V will be 4.5V typical. For battery voltages ‡ 2V connected to VBATT, RESET and RESET remain valid for VCC from 0V to 5.5V.

OUT enables the parts to be used with most µPs. abled mode) while RESET and –R—E—S—E—T– are asserted. deasserted following the reset timeout period. as a 75Ω resistor in series with the load at CE OUT. use a low output-impedance driver. turns off when the transmission gate is enabled. comparator. LOW LINE typically sinks 3.2mA at 0.1V. old), LOW LINE is pulled to VOUT. that has no effect on the other functions of the IC. Figure 3. Oscillator Circuits Table 1. Reset Pulse Width and Watchdog Timeout Selections

tus of the inputs and outputs in battery-backup mode. which controls the internal V CC and VBATT switches. power-on transients may reach a maximum of 1A. Figure 6. CE Propagation Delay Test Circuit Figure 7. Low-Battery Indicator 1 VBATT Supply current is 1µA max.

3 VCC

4 GND GND 0V, 0V reference for all signals.

6 LOWLINE Logic low*

8 OSC SEL OSC SEL is ignored.

9 PFI

10 PFO

13 CE IN High impedance

15 RESET Logic low*

16 RESET High impedance*

diode and the switch are each approximately 10 Ω . peak currents (only during power-up) limited to 250mA. temperature and supply voltage (Figure 8). pling capacitor, destroys the device. that would forward bias the chip’s protection diodes. only leakage currents flow from the battery. until the voltage at VBATT is less than 0.5V above V CC. Figure 8. VCC and VBATT to VOUT Switch Figure 9. SuperCap or MaxCap on VBATT

CC fall rate is just the inverse or 1A/100 µF = 0.01V/µs. Figure 14. Watchdog Flow Diagram

MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits _Ordering Information (continued) PART MAX693A CPE MAX693ACSE MAX693ACWE 0° C to +70° C 0° C to +70° C 0° C to +70° C TEMP. RANGE PIN-PACKAGE MAX693AEJE -40° C to +85° C 0° C to +70° C Dice* MAX693AESE -40° C to +85° C -40° C to +85° C 16 Plastic SO MAX693AEWE -40° C to +85° C 16 Wide SO MAX693AMJE -55° C to +125° C 16 CERDIP MAX800L CPE MAX800LCSE MAX800LEPE -40° C to +85° C 0° C to +70° C 0° C to +70° C 16 Plastic DIP -40° C to +85° C 16 Narrow SO MAX800MEPE -40° C to +85° C 0° C to +70° C 0° C to +70° C 16 Plastic DIP MAX800MESE -40° C to +85° C 16 Narrow SO * Dice are specified at TA = +25° C, DC parameters only. WDI CE IN CE OUT VCC GND WDO BATT ON LOW LINE VOUT VBATT RESET RESET PFI PFO OSC SEL OSC IN 0.11" (2.794mm) 0.07" (1.778mm) TRANSISTOR COUNT: 729 SUBSTRATE CONNECTED TO VOUT SOICN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.