MAX7036GTP+

MAX7036_10 MAXIM | Alldatasheet

Document overview

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Technical content

Features

o < 250µs Enable Turn-On Time o On-Chip PLL, VCO, Mixer, IF, Baseband o Low IF (200kHz Nominal) o 5.5mA DC Current o 1µA Standby Current o 3.3V/5V Operation o Small 20-Pin Thin QFN Package with an Exposed Pad MAX7036 300MHz to 450MHz ASK Receiver with Internal IF Filter MAX7036 THIN QFN 5mm x 5mm TOP VIEW

20 EP+

Ordering Information

19-4386; Rev 1; 8/10 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. EVALUATION KIT AVAILABLE PART TEMP RANGE PIN-PACKAGE MAX7036GTP/V+ -40°C to +105°C 20 Thin QFN-EP* /Vdenotes an automative qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.

300MHz to 450MHz ASK Receiver with Internal IF Filter ABSOLUTE MAXIMUM RATINGS 3.3V DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VDD = 3.0V to 3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD = VDVDD = VDD = 3.3V, T A = +25°C, unless otherwise noted.) (100% tested at TA = +105°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DD + 0.3V) DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) Junction-to-Case Thermal Resistance (θJC) (Note 1) Junction-to-Ambient Thermal Resistance (θJA) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD VAVDD = VDVDD = VDD 3.0 3.3 3.6 V fRF = 315MHz 5.3 6.7 fRF = 433MHz 5.8 7.3 mA Supply Current I IN TA < +105°C Deep-sleep mode, VENABLE = 0V 1 2.7 µA DIGITAL INPUT (ENABLE) Input High Voltage V IH VAVDD = VDVDD = VDD VDD - 0.4 V Input Low Voltage V IL VAVDD = VDVDD = VDD 0.4 V Input Current I ENABLE 0 ≤ VENABLE ≤ VDD 20 µA DIGITAL OUTPUT (DATAOUT) Output Low Voltage V OL ISINK = 100µA 0.4 V Output High Voltage V OH ISOURCE = 100µA VDD - 0.4 V Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a single- layer board. For detailed information on package thermal considerations, go to www.maxim-ic.com/thermal-tutorial.

300MHz to 450MHz ASK Receiver with Internal IF Filter PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD 4.5 5.0 5.5 V fRF = 315MHz 5.4 6.8 fRF = 433MHz 5.9 7.4 mA Supply Current I IN TA < +105°C Deep-sleep mode, VENABLE = 0V 1 3.4 µA DIGITAL INPUT (ENABLE) Input High Voltage V IH VAVDD = VDVDD VDD - 0.4 V Input Low Voltage V IL VAVDD = VDVDD 0.4 V Input Current I ENABLE 0 ≤ VENABLE ≤ VDD 20 µA DIGITAL OUTPUT (DATAOUT) Output Low Voltage V OL ISINK = 100µA 0.4 V Output High Voltage V OH ISOURCE = 100µA VDD - 0.4 V 5.0V DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit , 50Ω system impedance, V DD = 4.5V to 5.5V, f RF = 300MHz to 450MHz, T A = -40°C to +105°C, unless otherwise noted. Typical values are at VDD = 5.0V, TA = +25°C, unless otherwise noted.) (100% tested at TA = +105°C.) AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VDD = 3.0V to 3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD = VDVDD = VDD = 3.3V, TA = +25°C, fRF = 315MHz, unless otherwise noted.) (100% tested at TA = +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Receiver Input Frequency Range f RF 300 450 MHz Maximum Receiver Input Level P RFIN 0 dBm fRF = 315MHz -109Sensitivity (Note 2) fRF = 433MHz -107 dBm Enable power on (VDD > 3.0V) 250 µs Power-On Time t ON Time for valid RSSI output, does not include baseband filter settling VDD power on 1 ms AGC Hysteresis 5d B AGC Low Gain-to-High Gain Switching Time 13 ms

300MHz to 450MHz ASK Receiver with Internal IF Filter AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VDD = 3.0V to 3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at V AVDD = VDVDD = VDD = 3.3V, TA = +25°C, fRF = 315MHz, unless otherwise noted.) (100% tested at TA = +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LNA/MIXER fRF = 315MHz 0.4 - j5.6 LNA Input Impedance Z INLNA Normalized to 50Ω fRF = 433MHz 0.4 - j4.0 Ω LO Signal Feedthrough to Antenna -75 dBm Voltage Gain Reduction Low-gain mode, AGC enabled 29 dB High-gain LNA mode 55LNA/Mixer Voltage Gain Low-gain LNA mode 26 dB 3dB Cutoff Frequency BW IF Set by capacitors on IFC1 and IFC2 (see the Typical Application Circuit) 400 kHz RSSI Linearity ±0.5 dB RSSI Dynamic Range Includes AGC 80 dB PRFIN < -120dBm 1.34RSSI Level PRFIN > 0dBm, AGC enabled 2.35 V Intermediate Frequency f IF 200 kHz Maximum Data-Filter Bandwidth BW DF 50 kHz Maximum Data-Slicer Bandwidth BW DS 100 kHz Maximum Peak Detector Bandwidth 50 kHz Manchester coded 33Maximum Data Rate Nonreturn to zero (NRZ) 66 kbps Crystal Frequency f XTAL 9.36 14.06 MHz Crystal Load Capacitance C LOAD 10 pF Note 2: BER = 2 x 10-3, Manchester coded, data rate = 4kbps. IF bandwidth = 400kHz.

300MHz to 450MHz ASK Receiver with Internal IF Filter SUPPLY CURRENT vs. SUPPLY VOLTAGE (3.3V OPERATION) MAX7036 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 3.43.33.23.1 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.8 3.0 3.6 3.5 TA = -40°C TA = +25°C TA = +85°C TA = +105°C VAVDD = VDVDD = VDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (5.0V OPERATION) MAX7036 toc02 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 5.35.14.94.7 5.05 5.10 5.15 5.20 5.25 5.30 5.35 5.40 5.45 5.00 4.5 5.5 5.0V APPLICATION CIRCUIT TA = +105°C TA = -40°C TA = +85°C TA = +25° SUPPLY CURRENT vs. RF FREQUENCY MAX7036 toc03 RF FREQUENCY (MHz) SUPPLY CURRENT (mA) 450400350300 4.5 5.0 5.5 6.0 6.5 7.0 4.0 250 500 TA = +105°C TA = -40°C TA = +85°C TA = +25° PRF = -80dBm BIT ERROR RATE vs. PEAK RF INPUT POWER MAX7036 toc04 PEAK RF INPUT POWER (dBm) BIT ERROR RATE (%) -105-110-115-120 0.01 0.1 100 0.001 -125 fRF = 315MHz fRF = 433MHz SENSITIVITY vs. TEMPERATURE MAX7036 toc05 TEMPERATURE (°C) SENSITIVITY (dBm) 60 85 1053510-15 -108.5 -108.0 -107.5 -107.0 -106.5 -106.0 -110.5 -110.0 -109.5 -109.0 -40 fRF = 433MHz fRF = 315MHz BER = 0.2% DATA RATE = 4kbps MANCHESTER RSSI vs. INPUT POWER MAX7036 toc06 INPUT POWER (dBm) RSSI (V) 1.4 1.6 1.8 2.0 2.2 2.4 1.2 -120 fRF = 433MHz fIF = 200kHz LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY MAX7036 toc07 IF FREQUENCY (kHz) LNA/MIXER VOLTAGE GAIN (dB) 800 1000600400200 fRF = 433.92MHz PRF = -71dBm S11 SMITH CHART PLOT OF RFIN (315MHz CIRCUIT) MAX7036 toc08 S11 = 7.9729Ω - j0.6085Ω at fRF = 315MHz S11 SMITH CHART PLOT OF RFIN (433MHz CIRCUIT) MAX7036 toc09 S11 = 6.5175Ω - j5.5849Ω at fRF = 433MHz Typical Operating Characteristics (Typical Application Circuit, VAVDD = VDD = VDVDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)

300MHz to 450MHz ASK Receiver with Internal IF Filter Pin Description Typical Operating Characteristics (continued) (Typical Application Circuit, VAVDD = VDD = VDVDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) PIN NAME FUNCTION 1 ENABLE Enable Input. Internally pulled down to ground. Set V ENABLE = VDD for normal operation. 2 XTAL2 Crystal Input 2. Connect an external crystal from XTAL2 to XTAL1. Bypass to GND if XTAL1 is driven from an AC-coupled external reference (see the Crystal Oscillator section). 3 XTAL1 Crystal Input 1. Connect an external crystal from XTAL2 to XTAL1. Can also be driven with an AC- coupled external reference oscillator (see the Crystal Oscillator section).

4 AVDD

Positive Analog Supply Voltage. Connect to DVDD. Bypass to GND with a 0.1µF capacitor as close as possible to the device (see the Typical Application Circuit). For 5.0V operation, AVDD is internally connected to an on-chip 3.2V LDO regulator. For 3.3V operation, connect AVDD to VDD. 5 LNAIN Low-Noise Amplifier Input. Must be AC-coupled (see the Low-Noise Amplifier section). 6 LNAOUT Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank circuit. AC- couple to MIXIN2 (see the Low-Noise Amplifier section). 7 MIXIN2 2nd Differential Mixer Input. Connect to the LNAOUT side of the LC tank filter through a 100pF capacitor (see the Typical Application Circuit). 8 MIXIN1 1st Differential Mixer Input. Connect to the AVDD side of the LC tank filter through a 100pF capacitor (see the Typical Application Circuit). 9 IFC2 IF Fi l ter C ap aci tor C onnecti on 2. Thi s i s for the S al l en- Key IF fi l ter . C onnect a cap aci tor fr om IFC 2 to GN D . The val ue of the cap aci tor i s d eter m i ned b y the IF fi l ter b and w i d th ( see the Typical Application Circuit) . 10 IFC1 IF Fi l ter C ap aci tor C onnecti on 1. Thi s i s for the S al l en- Key IF fi l ter . C onnect a cap aci tor fr om IFC 1 to IFC 3. The val ue of the cap aci tor i s d eter m i ned b y the IF fi l ter b and w i d th ( see the Typical Application Circuit) . 11 IFC3 IF Fi l ter C ap aci tor C onnecti on 3. Thi s i s for the S al l en- Key IF fi l ter . C onnect a cap aci tor fr om IFC 3 to IFC 1. The val ue of the cap aci tor i s d eter m i ned b y the IF fi l ter b and w i d th ( see the Typical Application Circuit) . 12 DVDD Positive Digital Supply Voltage Input. Connect to AVDD. Bypass to GND with a 0.01µF capacitor as close as possible to the device (see the Typical Application Circuit). REGULATOR VOLTAGE vs. REGULATOR CURRENT MAX7036 toc10 REGULATOR CURRENT (mA) REGULATOR VOLTAGE (V) 20 2515105 3.05 3.10 3.15 3.00 TA = -40°C TA = +25°CTA = +85°C TA = +105°C VDD = 5V, +5V CIRCUIT PHASE NOISE vs. OFFSET FREQUENCY MAX7036 toc11 OFFSET FREQUENCY (kHz) PHASE NOISE (dBc/Hz) 100 10,0001 10 10000.1 -70 -60 -50 -120 -110 -100 -90 -80 0.01 fRF = 315MHz PHASE NOISE vs. OFFSET FREQUENCY MAX7036 toc12 OFFSET FREQUENCY (kHz) PHASE NOISE (dBc/Hz) 100 10,0001 10 10000.1 -70 -60 -50 -120 -110 -100 -90 -80 0.01 fRF = 433MHz

300MHz to 450MHz ASK Receiver with Internal IF Filter Functional Diagram Pin Description (continued) PIN NAME FUNCTION 13 DCOC DC Offset Capacitor Connection. This is for the RSSI amplifier. Connect a 1µF capacitor from this pin to ground (see the Typical Application Circuit). 14 OPP Noninverting Op-Amp Input. This is for the Sallen-Key data filter. Connect a capacitor from this pin to GND. The value of the capacitor is determined by the data-filter bandwidth. 15 DFFB Data-Filter Feedback Input. Input for the feedback of the Sallen-Key data filter. Connect a capacitor from this pin to DSP. The value of the capacitor is determined by the data-filter bandwidth. 16 DSP Positive Data-Slicer Input. Connect a capacitor from this pin to DFFB. The value of the capacitor is determined by the data-filter bandwidth.

17 DSN Negative Data-Slicer Input

18 PDOUT Peak-Detector Output

19 V DD

Power-Supply Voltage Input. For 5.0V operation, VDD is the input to an on-chip voltage regulator whose 3.2V output drives AVDD. Bypass to ground with a 0.1µF capacitor as close as possible to the device (see the Typical Application Circuit).

20 DATAOUT Digital Baseband Data Output

—E P Exposed Pad. Internally connected to ground. Connect to a large ground plane using multiple vias to maximize thermal and electrical performance. MAX7036 EP* *EXPOSED PAD. CONNECT TO GND. 3.2V REGULATOR PEAK DETECTOR REF REF AGC DATAOUT DSN PDOUT DSP OPP DFFB LNAOUT MIXIN1 MIXIN2 XTAL1 XTAL2 ENABLE VDD AVDD DVDD LNAIN IFC1 IFC2 IFC3 DCOC PLL 68 7 1 0 9 1 3 11 20 17 18 16 14 15

The MAX7036 CMOS RF receiver, and a few external components, provide the complete receiver chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 33kbps Manchester (66kbps NRZ) can be achieved. The MAX7036 is designed to receive binary ASK/OOK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent digital data. Voltage Regulator For operation with a single 3.0V to 3.6V supply voltage, connect AVDD, DVDD, and V DD to the supply voltage. For operation with a single 4.5V to 5.5V supply voltage, connect V DD to the supply voltage. An on-chip voltage regulator drives the AVDD pin to approximately 3.2V. For proper operation, connect DVDD and AVDD togeth- er. Bypass V DD and AVDD to GND with 0.1µF capaci- tors placed as close as possible to the device. Bypass DVDD to GND with a 0.01µF capacitor (see the Typical Application Circuit). Low-Noise Amplifier The LNA is an nMOS cascode amplifier. The LNA and mixer have a combined 55dB voltage gain. The gain and noise figures are dependent on both the antenna- matching network at the LNA input and the LC tank net- work between the LNA output and the mixer inputs. L2 and C1 comprise the LC tank filter connected to LNAOUT (see the Typical Application Circuit ). L2 also serves as a bias inductor to LNAOUT. Bypass the power-supply side of L2 to GND with a capacitor that provides a low-impedance path at the RF carrier fre- quency (e.g., 220pF). Select L2 and C1 to resonate at the desired RF input frequency. The resonant frequen- cy is given by: where L TOTAL = L2 + L PARASITICS and CTOTAL = C1 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PCB traces, package pins, mixer input impedance, LNA output impedance, etc. At high frequencies, these parasitics can have a dramatic effect on the tank filter center frequency and must not be ignored. The total parasitic capacitance is generally 4pF to 6pF. Adjust L2 and C1 accordingly to achieve the desired tank center frequency. Automatic Gain Control (AGC) The AGC circuit monitors the RSSI output. The AGC switches to its low-gain state when the RSSI output reaches 2.2V. The AGC gain reduction is typically 29dB, corresponding to an RSSI voltage drop of 435mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.67V for 13ms for 315MHz and 10ms for 433MHz operation. The AGC has a hysteresis of 5dB. With this AGC function, the MAX7036 can reliably produce an ASK output for RF input levels up to 0dBm, with modulation depth of 30dB. Mixer The mixer cell is a double-balanced mixer that performs a downconversion of the RF input to a typical IF of 200kHz from either a high-side or a low-side injected LO. The mixer output drives the input of the on-chip IF filter. Phase-Locked Loop (PLL) The PLL block contains a phase detector, charge pump, integrated loop filter, VCO, asynchronous clock dividers, and crystal-oscillator driver. Besides the crystal, this PLL does not require any external components. The VCO generates the LO. The relationship between the RF, IF, and crystal reference frequencies is given by: where f LO = fRF ±f IF Received-Signal-Strength Indicator (RSSI) The RSSI circuit provides a DC output proportional to the logarithm of the input power level. RSSI output volt- age has a slope of about 14.5mV/dB (of input power).The RSSI monotonic dynamic range exceeds 80dB. This includes the 30dB of AGC. Applications Information Crystal Oscillator The crystal (XTAL) oscillator in the MAX7036 is designed to present a capacitance of approximately 4pF between XTAL1 and XTAL2. In most cases, this corresponds to a 6pF load capacitance applied to the external crystal when typical PCB parasitics are added. The MAX7036 is designed to operate with a typical 10pF load capacitance crystal. It is very important to use a crystal with a load capacitance equal to the capacitance of the MAX7036 crystal oscillator plus PCB parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing f f XTAL LO= 32 f LCRF TOTAL TOTAL 300MHz to 450MHz ASK Receiver with Internal IF Filter

as short as possible to minimize losses and radiation. close to all power-supply connections. Figure 4. Using PDOUT for Faster Startup Table 2. Component Values

300MHz to 450MHz ASK Receiver with Internal IF Filter Typical Application Circuit Chip Information PROCESS: CMOS ENABLE XTAL2 XTAL1 DFFB OPP DCOC IFC3 DVDD LNAIN AVDD LNAOUT MIXIN2 MIXIN1 IFC1 IFC2 DATAOUT V DD PDOUT DSP DSN MAX7036 Y1C14 C13 C15 C16 R2 C17 C12 C10 VSUP IF VSUP IS THEN V3V IS 3.0V TO 3.6V TIED TO VSUP 4.5V TO 5.5V CREATED BY LDO, AVAILABLE AT AVDD (PIN 4) (SEE TABLE ABOVE) V3V C11 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

20 Thin QFN-EP T2055+3 21-0140 90-0008

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of RoHS status.

300MHz to 450MHz ASK Receiver with Internal IF Filter Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 3/09 Initial release — 1 8/10 Updated Absolute Maximum Ratings, TOCs 5, 11, and 12, Pin Description, Phase-Locked Loop (PLL) and Crystal Oscillator sections, and Typical Application Circuit 2, 5, 6, 8, 9, 12