MAX7033

MAX7033_1109 MAXIM | Alldatasheet

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Technical content

Features

o Optimized for 315MHz or 433MHz Band o Operates from Single +3.3V or +5.0V Supplies o High Dynamic Range with On-Chip AGC o AGC Hold Circuit o 1ms AGC Release Time o Selectable Image-Rejection Center Frequency o Selectable x64 or x32 fLO/fXTAL Ratio o Low 5.2mA Operating Supply Current o < 3.5µA Low-Current Power-Down Mode for Efficient Power Cycling o 250µs Startup Time o Built-In 44dB RF Image Rejection o Better than -114dBm Receive Sensitivity o -40°C to +105°C Operation MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock XTAL2 SHDN PDOUT DATAOUT V DD5 DSP AC DFFB OPP DSN DFO IFIN2 IFIN1 XTALSEL DVDD DGND MIXOUT IRSEL AGND MIXIN2 MIXIN1 AVDD LNAOUT AGND LNASRC LNAIN AVDD XTAL1 TSSOP TQFN TOP VIEW MAX7033 LNASRC LNAIN AVDD XTAL1 XTAL2 SHDN PDOUT 25 N.C. MIXOUT DGND DVDD AC N.C. XTALSEL IFIN1 16IFIN2 DFO DSN OPP DFFB N.C. DSP VDD5 IRSEL AGND MIXIN2 MIXIN1 AVDD LNAOUT AGND MAX7033 1N.C. 24 DATAOUT Pin Configurations Ordering InformationApplications 19-3273; Rev 3; 9/11 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.Typical Application Circuit appears at end of data sheet. PART TEMP RANGE PIN-PACKAGE MAX7033EUI+ -40 °C to +105°C 28 TSSOP MAX7033ETJ+ -40 °C to +105°C 32 TQFN-EP* Automotive Remote Keyless Entry Security Systems Garage Door Openers Home Automation Remote Controls Local Telemetry Wireless Sensors

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock ABSOLUTE MAXIMUM RATINGS DC ELECTRICAL CHARACTERISTICS (+3.3V OPERATION) (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.0V to +3.6V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. IRSEL, DATAOUT, XTALSEL, DD5 + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin TSSOP (derate 12.8mW/°C above +70°C) ..1025.6mW PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VAVDD, VDVDD +3.3V nominal supply voltage 3.0 3.3 3.6 V fRF = 315MHz 5.2 6.23Supply Current I DD V SHDN = VDVDD fRF = 433MHz 5.7 6.88 mA fRF = 315MHz 2.6Shutdown Supply Current I SHDN V SHDN = 0V, VXTALSEL = 0V fRF = 433MHz 3.5 8.0 μA Input-Voltage Low V IL 0.4 V Input-Voltage High V IH VDVDD - 0.4 V Input Logic Current High I IH 10 μA fRF = 433MHz, VIRSEL = VDD5 VDD5 - 0.4 fRF = 375MHz, VIRSEL = VDD5/2 1.1 VDD5 - 1.0 Image-Reject Select Voltage (Note 2) f RF = 315MHz, VIRSEL = 0V 0.4 V DATAOUT Output-Voltage Low V OL ISINK = 10μA 0.125 V DATAOUT Output-Voltage High V OH ISOURCE = 10μA VDVDD - 0.125 V DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (Typical Application Circuit , VDD5 = +4.5V to +5.5V, no RF signal applied, T A = -40°C to +105°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD5 +5.0V nominal supply voltage 4.5 5.0 5.5 V fRF = 315MHz 5.2 6.4Supply Current I DD V SHDN = VDD5 fRF = 433MHz 5.7 6.76 mA fRF = 315MHz 3.7Shutdown Supply Current I SHDN V SHDN = 0V, VXTALSEL = 0V fRF = 433MHz 4.2 9.8 μA Input-Voltage Low V IL 0.4 V

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (continued) (Typical Application Circuit , VDD5 = +4.5V to +5.5V, no RF signal applied, T A = -40°C to +105°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input-Voltage High V IH VDD5 - 0.4 V Input Logic Current High I IH 15 μA fRF = 433MHz, VIRSEL = VDD5 VDD5 - 0.4 fRF = 375MHz, VIRSEL = VDD5/2 1.1 VDD5 - 1.5 Image-Reject Select Voltage (Note 2) f RF = 315MHz, VIRSEL = 0V 0.4 V DATAOUT Output-Voltage Low V OL ISINK = 10μA 0.125 V DATAOUT Output-Voltage High V OH ISOURCE = 10μA VDD5 - 0.125 V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit , V AVDD = V DVDD = V DD5 = +3.0V to +3.6V, all RF inputs are referenced to 50 Ω, f RF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Startup Time t ON Time for valid signal detection after V SHDN = VDVDD 250 μs Receiver Input Frequency f RF 300 450 MHz Maximum Receiver Input Level Modulation depth >18dB 0 dBm Average carrier power level -120Sensitivity (Note 3) Peak power level -114 dBm LNA gain from low to high 8 dBAGC Hysteresis Switching time from low to high gain 1 ms Manchester coded 33Maximum Data Rate NRZ coded 66 kbps LNA IN HIGH-GAIN MODE fRF = 433MHz 1 - j3.4 fRF = 375MHz 1 - j3.9Input Impedance Z IN_LNA Normalized to 50Ω fRF = 315MHz 1 - j4.7 1dB Compression Point P1dB LNA -22 dBm Input-Referred 3rd-Order Intercept IIP3LNA -12 dBm LO Signal Feedthrough to Antenna -80 dBm Noise Figure NF LNA 3d B

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit , V AVDD = V DVDD = V DD5 = +3.0V to +3.6V, all RF inputs are referenced to 50 Ω, f RF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LNA IN LOW-GAIN MODE fRF = 433MHz 1 - j3.4 fRF = 375MHz 1 - j3.9Input Impedance Z IN_LNA Normalized to 50Ω (Note 4) fRF = 315MHz 1 - j4.7 1dB Compression Point P1dB LNA -10 dBm Input-Referred 3rd-Order Intercept IIP3LNA -7 dBm LO Signal Feedthrough to Antenna -80 dBm Noise Figure NF LNA 3d B Voltage-Gain Reduction AGC enabled (depends on tank Q) 35 dB MIXER Input-Referred 3rd-Order Intercept IIP3MIX -18 dBm Output Impedance Z OUT_MIX 330 Ω Noise Figure NF MIX 16 dB fRF = 433MHz, VIRSEL = VDVDD 42 fRF = 375MHz, VIRSEL = VDVDD/2 44Image Rejection (Not Including LNA Tank) fRF = 315MHz, VIRSEL = 0V 44 dB LNA in high-gain mode 48 LNA/Mixer Voltage Gain 330 Ω IF filter load LNA in low-gain mode 13 dB INTERMEDIATE FREQUENCY (IF) Input Impedance Z IN_IF 330 Ω Operating Frequency f IF Bandpass response 10.7 MHz 3dB Bandwidth 10 MHz RSSI Linearity ±0.5 dB RSSI Dynamic Range 80 dB PRFIN < -120dBm 1.15RSSI Level PRFIN > 0dBm, AGC enabled 2.2 V LNA gain from low to high 1.39AGC Threshold LNA gain from high to low 1.98 V DATA FILTER Maximum Bandwidth 50 kHz DATA SLICER Comparator Bandwidth 100 kHz

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Note 1: 100% tested at TA = +25°C. Guaranteed by design and characterization over temperature. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass to AGND with a 1nF capacitor in a noisy environment. Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration con- nected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = VDD5. AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit , V AVDD = V DVDD = V DD5 = +3.0V to +3.6V, all RF inputs are referenced to 50 Ω, f RF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum Load Capacitance C LOAD 10 pF Output High Voltage VDD5 V Output Low Voltage 0V CRYSTAL OSCILLATOR VXTALSEL = 0V 6.6128fRF = 433MHz VXTALSEL = VDD5 13.2256 VXTALSEL = 0V 4.7547Crystal Frequency (Note 5) f XTAL fRF = 315MHz VXTALSEL = VDD5 9.5094 MHz Crystal Tolerance 50 ppm Input Capacitance From each pin to ground 6.2 pF Typical Operating Characteristics (Typical Application Circuit , VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX7033 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 4.0 3.0 3.6 +85°C +105°C +25°C -40°C SUPPLY CURRENT vs. RF FREQUENCY MAX7033 toc02 RF FREQUENCY (MHz) SUPPLY CURRENT (mA) 450400300 350 3.5 4.0 4.5 5.0 6.0 5.5 6.5 7.0 3.0 250 500 +105°C +85°C -40°C +25°C BIT-ERROR RATE vs. AVERAGE CARRIER POWER MAX7033 toc03 AVERAGE CARRIER POWER (dBm) BIT-ERROR RATE (%) -116-118-120-122-124-126-128 0.1 100 0.01 -130 -114 fRF = 433MHz fRF = 315MHz

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Typical Operating Characteristics (continued) (Typical Application Circuit , VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) SENSITIVITY vs. TEMPERATURE MAX7033 toc04 TEMPERATURE (°C) SENSITIVITY (dBm) 85603510-15 -122 -120 -118 -116 -114 -112 -110 -108 -124 -40 110 AVERAGE CARRIER POWER 0.2% BER IF BANDWIDTH = 280kHz fRF = 433MHz fRF = 315MHz RSSI vs. RF INPUT POWER MAX7033 toc05 RF INPUT POWER (dBm) RSSI (V) 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.0 -140 0 IF BANDWIDTH = 280kHz VAC = VDVDD VAC = 0V RSSI AND DELTA vs. IF INPUT POWER MAX7033 toc06 IF INPUT POWER (dBm) RSSI (V) -10-30-50-70 1.2 1.4 1.6 1.8 2.0 2.2 2.4 DELTA (%) 1.0 -90 10 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 -3.5 DELTA RSSI LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY MAX7033 toc07 IF FREQUENCY (MHz) SYSTEM GAIN (dB) 252015105 03 0 UPPER SIDEBAND 49dB IMAGE REJECTION LOWER SIDEBAND FROM RFIN TO MIXOUT f RF = 315MHz IMAGE REJECTION vs. RF FREQUENCY MAX7033 toc08 RF FREQUENCY (MHz) IMAGE REJECTION (dB) 460440420400380360340320300 280 480 fRF = 375MHz fRF = 315MHz fRF = 433MHz IMAGE REJECTION vs. TEMPERATURE MAX7033 toc09 TEMPERATURE (°C) IMAGE REJECTION (dB) 603510-15 41.0 41.5 42.0 42.5 43.0 43.5 44.0 44.5 45.0 40.5 -40 85 fRF = 375MHz fRF = 315MHz fRF = 433MHz

vs. REGULATOR CURRENT MAX7033 toc13 REGULATOR CURRENT (mA) REGULATOR VOLTAGE (V) 5040302010 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 1.7 06 0 -40°C +25°C +85°C +105°C PHASE NOISE vs. OFFSET FREQUENCY MAX7033 toc14 OFFSET FREQUENCY (Hz) PHASE NOISE (dBc/Hz) 1M100k10k1k100 -120 -100 -80 -60 -40 -20 -140 10 10M fRF = 315MHz PHASE NOISE vs. OFFSET FREQUENCY MAX7033 toc15 OFFSET FREQUENCY (Hz) PHASE NOISE (dBc/Hz) 1M100k10k1k100 -120 -100 -80 -60 -40 -20 -140 10 10M fRF = 433MHz 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock NORMALIZED IF GAIN vs. IF FREQUENCY MAX7033 toc10 IF FREQUENCY (MHz) NORMALIZED IF GAIN (dB) -25 -20 -15 -10 -30 1 100 S11 LOG MAGNITUDE PLOT OF RFIN MAX7033 toc11 FREQUENCY (MHz) S11 MAGNITUDE (dB) 900800600 700200 300 400 500100 -40 -30 -20 -10 -50 0 1000 315MHz -36dB S11 SMITH CHART PLOT OF RFIN MAX7033 toc12 500MHz 200MHz 315MHz WITH INPUT MATCHING Typical Operating Characteristics (continued) (Typical Application Circuit , VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Pin Description PIN TSSOP THIN QFN NAME FUNCTION 1 29 XTAL1 Crystal Input 1 (See the Phase-Locked Loop section) 2, 7 4, 30 AVDD Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V low-dropout regulator, and should be bypassed to AGND with a 0.1μF capacitor as close as possible to the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed to AGND with a 0.01μF capacitor as close as possible to the pin. (See the Voltage Regulator section and the Typical Application Circuit.) 3 31 LNAIN Low-Noise Amplifier Input (See the Low-Noise Amplifier section) 4 32 LNASRC Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set the LNA input impedance (See the Low-Noise Amplifier section). 5, 10 2, 7 AGND Analog Ground 6 3 LNAOUT Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (See the Low- Noise Amplifier section). 8 5 MIXIN1 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT. 9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to V DD3 side of the LC tank. 11 8 IRSEL Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = VDD5 to center image rejection at 433MHz. 12 9 MIXOUT 330 Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter. 13 10 DGND Digital Ground 14 11 DVDD Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01μF capacitor as close as possible to the pin. (See the Typical Application Circuit.) 15 12 AC Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100k Ω resistor. 16 14 XTALSEL Crystal Divider Ratio Select. Drive XTALSEL low to select fLO/fXTAL ratio of 64, or drive XTALSEL high to select fLO/fXTAL ratio of 32. 17 15 IFIN1 1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF capacitor as close to the pin as possible. 18 16 IFIN2 2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz bandpass filter. 19 17 DFO Data Filter Output 20 18 DSN Negative Data Slicer Input 21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter 22 20 DFFB Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. 23 22 DSP Positive Data Slicer Input 24 23 V DD5 +5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin. For +5V operation, V DD5 is the input to an on-chip voltage regulator whose +3.2V output ap p ear s at the p i n 2 AV D D p i n. ( S ee the V ol tag e Reg ul ator secti on and the Typ i cal Ap p l i cati on C i r cui t.) 25 24 DATAOUT Digital Baseband Data Output 26 26 PDOUT Peak-Detector Output 27 27 SHDN Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a 100kΩ resistor.

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Functional Diagram LNAOUT MIXIN1 MIXIN2 90˚ IFIN1MIXOUT IFIN2 RSSI RDF2 100kΩ RDF1 100kΩ DIVIDE BY 64 VCO LOOP FILTER PHASE DETECTOR CRYSTAL DRIVER POWER- DOWN IF LIMITING AMPS LNASRC DATA SLICER DATA FILTER Q I AUTOMATIC GAIN CONTROL IMAGE REJECTION 3.2V REG24 IRSEL 5, 10 AVDD VDD5 DVDD DGND AGND LNAIN 3 XTALSEL XTAL1 XTAL2 SHDN DATAOUT DSN DSP DFO PDOUT OPP DFFB 4 15 6 8 9 11 12 17 18 AC MAX7033 LNA 7AVDD 28-PIN TSSOP PACKAGE Pin Description (continued) PIN TSSOP THIN QFN NAME FUNCTION 28 28 XTAL2 Crystal Input 2. Can also be driven with an external reference oscillator. (See the Crystal Oscillator section.) — 1, 13, 21, 25 N.C No Connection — — EP Exposed Pad (TQFN Only). Connect EP to GND. Detailed Description The MAX7033 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 33kbps Manchester (66kbps NRZ) can be achieved. The MAX7033 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. Voltage Regulator For operation with a single +3.0V to +3.6V supply voltage, connect AVDD, DVDD, and V DD5 to the supply voltage. For operation with a single +4.5V to +5.5V supply voltage, connect VDD5 to the supply voltage. An on-chip voltage regulator drives one of the AVDD pins to approximately +3.2V. For proper operation, DVDD and both the AVDD pins must be connected together. Bypass V DD5, DVDD, and the pin 7 AVDD pin to AGND with 0.01μF capacitors, and the pin 2 AVDD pin to AGND with a 0.1μF capacitor, all placed as close as possible to the pins. Low-Noise Amplifier The LNA is an nMOS cascode amplifier with off-chip inductive degeneration, with a 3.0dB noise figure and an IIP3 of -12dBm. The gain and noise figures are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs.

15nH, but is affected by PCB trace. and C2 to resonate at the desired RF input frequency. mize the center frequency of the tank. 0dBm with modulation depth of 18dB. bringing the AC pin low when SHDN is high. when SHDN is low has no effect. board space, and lower cost. Figure 1. AGC Lock Activation Cycles

sitivity), minimize the tolerance of the reference crystal. Table 1. Component Values for Typical Application Circuit

quency with a 3dB bandwidth of approximately 10MHz. for in the specification of the load capacitance. P is the amount the crystal frequency pulled in ppm. CM is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. CSPEC, the frequency pulling equals zero. couple XTAL1 to ground with a 1000pF capacitor. cies, resulting in an increase in receiver sensitivity. and a rolloff rate of 40dB/decade for the two-pole filter. C is the desired 3dB corner frequency. Figure 2. Sallen-Key Lowpass Data Filter Table 2. Coefficents to Calculate C5 and C6

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Typical Application Circuit 28C13 C11 VDD3 RF INPUT VDD3 VDD C12 MAX7033 DVDD IF FILTER COMPONENT VALUES IN TABLE 1 **SEE THE MIXER SECTION. *SEE PHASE-LOCKED LOOP SECTION. Y1 * GNDIN OUT DGND MIXOUT IRSEL AGND MIXIN2 MIXIN1 AVDD LNAOUT C10 AGND LNASRC LNAIN AVDD XTAL1 XTAL2 TO/FROM μP POWER-DOWN DATA OUT SHDN PDOUT DATAOUT VDD5 DSP AC DFFB FROM μP C6C5 OPP DSN DFO IFIN2 IFIN1 XTALSEL IF VDD IS 3.0V TO 3.6V THEN VDD3 IS CONNECTED TO VDD CREATED BY LDO, AVAILABLE AT AVDD (PIN 2) C15 C14 (SEE TABLE) 4.5V TO 5.5V Layout Considerations A properly designed PCB is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radia- tion. At high frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic induc- tance. Generally, 1in of a PCB trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace con- necting a 100nH inductor adds an extra 10nH of induc- tance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capaci- tors close to all power-supply pins. Control Interface Considerations When operating the MAX7033 with a +4.5V to +5.5V supply voltage, the SHDN and AC pins can be driven by a microcontroller with either 3V or 5V interface logic levels. When operating the MAX7033 with a +3.0V to +3.6V supply, only 3V logic from the microcontroller is allowed.

PROCESS: CMOS 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

28 TSSOP U28+1 21-0066 90-0171

32 TQFN-EP T3255+3 21-0140 90-0001

315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 7/04 Initial release — 1 1/11 Updated Ordering Information, Pin Configurations, Absolute Maximum Ratings, Characteristics, Pin Description, Functional Diagram, Voltage Regulator and Layout Considerations sections, Typical Application Circuit, Chip Information, and Package Information 1–9, 13, 14, 15 2 9/11 Updated input impedance values in AC Electrical Characteristics table; updated TOC3 and TOC4 labels in Typical Operating Characteristics; clarified equations in Pin Description and Phase-Locked Loop and Crystal Oscillator sections; updated components in Table 1; and added new Control Interface Considerations section 3–6, 11–14