MAX500

MAX500 MAXIM | Alldatasheet

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For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 The MAX500 is a quad, 8-bit, voltage-output digital-to- analog converter (DAC) with a cascadable serial inter- face. The IC includes four output buffer amplifiers and input logic for an easy-to-use, two- or three-wire serial interface. In a system with several MAX500s, only one serial data line is required to load all the DACs by cas- cading them. The MAX500 contains double-buffered logic and a 10-bit shift register that allows all four DACs to be updated simultaneously using one control signal. There are three reference inputs so the range of two of the DACs can be independently set while the other two DACs track each other. The MAX500 achieves 8-bit performance over the full operating temperature range without external trimming. Minimum Component Count Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Arbitrary Function Generators Automatic Test Equipment ' Buffered Voltage Outputs ' Double-Buffered Digital Inputs ' Microprocessor and TTL/CMOS Compatible ' Requires No External Adjustments ' Two- or Three-Wire Cascadable Serial Interface ' 16-Pin DIP/SO Package and 20-Pin LCC ' Operates from Single or Dual Supplies MAX500 CMOS, Quad, Serial-Interface 8-Bit DAC TOP VIEW V OUT C VOUT D VDD VREF CVREF A/B VSS VOUT A VOUT B MAX500 VREF D SRO SCL LOADSDA LDAC DGND AGND DIP/SO MAX500 VOUTA DAC A DAC B DAC C DAC D VREFC VREFA/B DAC REG A INPUT REG A DAC REG B INPUT REG B DAC REG C INPUT REG C DAC REG D INPUT REG D 10/11- BIT SHIFT REGISTER CONTROL LOGIC LOAD SCL SDA VOUTB VOUTC VOUTD SRO VDDDGND VSS AGND VREFD DATA BUS LDAC 19-1016; Rev 2; 2/96 PART MAX500ACPE MAX500BCPE MAX500ACWE 0°C to +70°C 0°C to +70°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE

16 Plastic DIP

16 Wide SO

MAX500BCWE 0°C to +70°C 16 Wide SO MAX500BC/D 0°C to +70°C Dice* MAX500AEPE -40°C to +85°C 16 Plastic DIP MAX500BEPE -40°C to +85°C 16 Plastic DIP MAX500AEWE -40°C to +85°C 16 Wide SO MAX500BEWE -40°C to +85°C 16 Wide SO MAX500AEJE -40°C to +85°C 16 CERDIP MAX500BEJE -40°C to +85°C 16 CERDIP MAX500AMJE -55°C to +125°C 16 CERDIP MAX500BMJE -55°C to +125°C 16 CERDIP ERROR (LSB) *Contact factory for dice specifications. Pin Configurations continued on last page. MAX500AMLP -55°C to +125°C 20 LCC ±1 MAX500BMLP -55°C to +125°C 20 LCC ±2

CMOS, Quad, Serial-Interface 8-Bit DAC ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS—Dual Supplies (VDD = +11.4V to +16.5V, VSS = -5V ±10%, AGND = DGND = 0V, VREF = +2V to (VDD - 4V), TA = TMIN to TMAX, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Requirements Power Dissipation (TA= +70°C) Operating Temperature Ranges T A = +25°C (Notes 2, 3) TA = +25°C, code dependent (Note 2) VREFC, VREFD VREF = 10V MAX500A TA = TMIN to TMAX Guaranteed monotonic VDD = 15V ±5%, VREF = 10V MAX500A TA = +25°C CONDITIONS dB-60Channel-to-Channel Isolation pF100Reference Input Capacitance kΩ11Reference Input Resistance V2V DD - 4Reference Input Range µV/°C±30Zero-Code Tempco mV±20Zero-Code Error ±15 Bits8Resolution ppm/°C±5Full-Scale Tempco LSB±1/2Full-Scale Error LSB±1Differential Nonlinearity LSB±1Total Unadjusted Error LSB±1/2Relative Accuracy UNITSMIN TYP MAXSYMBOLPARAMETER AC Feedthrough TA = +25°C (Notes 2, 3) -70 dB Digital Input High Voltage VIH 2.4 5.5 Digital Input Low Voltage VIL 0.8 V Digital Output High Voltage VOH IOUT = -1mA, SRO only VDD - 1 V Digital Output Low Voltage VOL IOUT = 1mA, SRO only 0.4 V 5.5 MAX500A MAX500A MAX500A ±20 ±30 V STATIC PERFORMANCE REFERENCE INPUT DIGITAL INPUTS MAX500B MAX500B MAX500B MAX500B MAX500B Note 1:The outputs may be shorted to AGND, provided that the power dissipation of the package is not exceeded. Typical short-circuit current to AGND is 25mA VREFA/B ±1 µA Digital Input Capacitance TA = +25°C (Note 2) 8 pF Excluding LOAD 30(Note 4)Digital Input Leakage Current LOAD = 0V

CMOS, Quad, Serial-Interface 8-Bit DAC ELECTRICAL CHARACTERISTICS—Dual Supplies (continued) (VDD = +11.4V to +16.5V, VSS = -5V ±10%, AGND = DGND = 0V, VREF = +2V to (VDD - 4V), TA = TMIN to TMAX, unless otherwise noted.) Outputs unloaded VOUT = 10V Outputs unloaded (Note 5) (Note 5) TA = +25°C (Note 2) To ±1/2LSB, VREF = 10V, VDD = +15V, 2kΩ in parallel with 100pF load (Note 2) For specified performance CONDITIONS ns150tLDSLOAD Delay from SCL ns150tLDWLOAD Pulse Width ns350t2SCL Low Time ns350t1SCL High Time ns150tS1SDA Valid to SCL Setup ns150tS1SDA Valid to SCL Setup mA -10 ISSNegative Supply Current mA IDDPositive Supply Current V11.4 16.5VDDPositive Supply Voltage kΩ2Output Load Resistance nV-s50Digital Crosstalk nV-s50Digital Feedthrough 38Voltage Output Slew Rate µs2.5 4.5VOUT Settling Time UNITSMIN TYP MAXSYMBOLPARAMETER LDAC Pulse Width tLDAC 150 ns SRO Output Delay tD1 CLOAD = 50pF 150 ns SCL High Time t1 350 ns SDA Valid to SCL Hold tH 0 ns LDAC Pulse Width tLDAC 150 ns SCL Valid to SDA Setup tS1 Start condition 150 ns SDA Valid to SCL Setup tS2 Stop condition 100 ns TA = +25°C TA = +25°C V/µs SDA Valid to Rising SCL tS3 125 ns SRO Output Delay tD1 CLOAD = 50pF 150 ns SCL High Time t1 350 ns SCL Fall Time (Note 7) 50 µs SCL Rise Time (Note 7) 50 µs SCL Low Time t2 350 ns TA = TMIN to TMAX TA = TMIN to TMAX For specified performance V11.4 16.5VDDPositive Supply Voltage (Note 7) µs50SCL Rise Time (Note 7) µs50SCL Fall Time ns0tHSDA Valid to SCL Hold DYNAMIC PERFORMANCE POWER SUPPLIES SWITCHING CHARACTERISTICS (TA = +25°C, Note 6) 3-Wire Mode 2-Wire Mode

CMOS, Quad, Serial-Interface 8-Bit DAC ELECTRICAL CHARACTERISTICS—Single Supply (VDD = +15V ±5%, VSS = AGND = DGND = 0V, VREF = 10V, TA = TMIN to TMAX, unless otherwise noted.) Outputs unloaded For specified performance Guaranteed monotonic TA = TMIN to TMAX VDD = 15V ±5%, VREF = 10V TA = +25°C CONDITIONS mA12IDDPositive Supply Current 10 V14.25 15.75VDDPositive Supply Voltage µV/°C±30Zero-Code Tempco mV ±30 Zero-Code Error ±20 ±20 ±15 Bits8Resolution ±1/2 LSB±1Differential Nonlinearity LSB±1Relative Accuracy ±1 LSB±2Total Unadjusted Error ±1/2 UNITSMIN TYP MAXSYMBOLPARAMETER Note 2:Guaranteed by design. Not production tested. Note 3:TA = +25°C, V REF = 10kHz, 10V peak-to-peak sine wave. Note 4:LOAD has a weak internal pull-up resistor to VDD. Note 5:DAC switched from all 1s to all 0s, and all 0s to all 1s code. Note 6:Sample tested at +25°C to ensure compliance. Note 7:Slow rise and fall times are allowed on the digital inputs to facilitate the use of opto-couplers. Only timing for SCL is given because the other digital inputs should be stable when SCL transitions. MAX500A MAX500A TA = +25°C MAX500A MAX500B MAX500A VREF = 10V ppm/°C±5Full-Scale Tempco LSB±1Full-Scale Error MAX500A MAX500B MAX500B MAX500B MAX500B TA = TMIN to TMAX STATIC PERFORMANCE REFERENCE INPUT — All specifications are the same as for dual supplies. DIGITAL INPUTS — All specifications are the same as for dual supplies. DYNAMIC PERFORMANCE — All specifications are the same as for dual supplies. POWER SUPPLIES SWITCHING CHARACTERISTICS — All specifications are the same as for dual supplies. 1.0 0.5 MAX500-04 -0.5 6 8 10 12 14 VREF (V) -1.0 RELATIVE ACCURACY (LSB) RELATIVE ACCURACY vs. REFERENCE VOLTAGE TA = +25°C, V SS = -5V VDD = 15V VDD = 12V 1.0 0.5 MAX500-05 -0.5 6 8 10 12 14 VREF (V) -1.0 DIFFERENTIAL NONLINEARITY (LSB) DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE VDD = 15V TA = +25°C, V SS = -5V VDD = 12V

diagram of one of the four DACs is provided in Figure 1. of infinity occurs when the input code is 00000000. unity-gain followers, which slew at greater than 3V/µs. mance of the MAX500 is shown in Figures 2 and 3. Figure 1. Simplified DAC Circuit Diagram

from the shift register to the addressed input register. and LOAD to +5.5V for a logic high. user must be careful of both timing and formatting. MAX500 from decoding the middle data for itself. Table 1. DAC Addressing Table 2. Logic Input Truth Table

for the circuit in Figure 9. codes, it should be driven by a low-impedance source.

2 VOUTA

Figure 10. AGND Bias Circuit Table 3. Unipolar Code Table Table 4. Bipolar Code Table

never be more negative than AGND. MAX500 to most popular microprocessors.

1 VOUTB

Figure 11. AC Reference Input Circuit Figure 12. Generating -5V for VSS Figure 14. Z-80 with Z8420 PIO InterfaceFigure 13. 80C51 Interface

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

6521 PA0

Figure 15. 8085/8088 with Programmable Peripheral Interface Figure 16. 6809/6502 Interface