MAX30009

MAX30009 AD | Alldatasheet

Document overview

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Technical content

The MAX30009 is a complete Bioimpedance (BioZ) Ana - log Front-End (AFE) solution for wearable applications. It offers high performance for fitness, wellness, and clinical applications, and ultra-low power for long battery life. The BioZ receive channel has Electrostatic Discharge (ESD) protection, Electromagnetic Interference (EMI) filtering, in- ternal lead-biasing, DC leads-off detection, DRVN lead- off detection, and ultra-low power lead-on detection during standby mode. The BioZ receive channel also has high in- put impedance, low noise, high Common-Mode Rejection Ratio (CMRR), programmable gain, various low-pass and high-pass filter options, and two high resolution analog-to- digital converters for simultaneous I and Q acquisition. The BioZ transmit channel has a sine-wave current gener- ator to drive AC currents into the body with a wide frequen- cy range of 16Hz to 500kHz and a wide magnitude range of 16nARMS to 1.28mARMS. The transmit channel can al- so operate in the sine-wave voltage and H-bridge modes. The flexible input/output MUX allows for both bipolar and tetrapolar measurements with multiple sets of electrodes. For measurements requiring high absolute impedance ac- curacy such as Bioimpedance Analysis/Spectroscopy (BIA/BIS) and Automated External Defibrillator (AED) body impedance, the MAX30009 offers several calibration options. An external precision resistor can be connected to the four-wire calibration port for the highest accuracy. Internal trimmed resistors also provide high accuracy. The PLL-based timing subsystem allows for a wide range of fine-tuned stimulus and sampling frequencies, and can be synchronized with other Analog Devices biosensors for simultaneous data collection. The MAX30009 is available in a 2.03mm x 2.03mm, 25-bump Wafer-Level Package (WLP), operating over the -40ºC to +85ºC temperature range.

Applications

• Wearable Fitness, Wellness, and Medical Devices
• Multifrequency Body Composition Analyzers
• Non-Invasive Hemodynamic Monitors
• Automatic External Defibrillators
• Optimized Performance to Accurately Detect:
• Respiration Rate
• Galvanic Skin Response/Electrodermal Activity
• Bioimpedance Spectroscopy
• Body Composition and Fluid Analysis
• Impedance Cardiography and Plethysmography Benefits and Features BIOZ
• Complete High-Performance BioZ AFE
• Simultaneous I and Q Measurement Capability
• Four-Electrode (Tetrapolar) and Two-Electrode (Bipolar) Configurations
• Ultra-Low Power Operation
• 250 μW at 1.8V AVDD
• High-Resolution, 20-Bit Sigma Delta Analog-to-Digital Converters (ADCs)
• Wide Range of Sample Rates from 16sps to 4ksps
• Flexible and Programmable Input/Output MUX
• Low-Noise, High-Resolution Receive Channel
• 17 Bits Effective Resolution with 1.1µVP-P Noise
• High Input Impedance > 1GΩ for Extremely Low Common to Differential-Mode Conversion
• Programmable Sine-Wave Stimulus
• Low Frequency, Low Current Options for Galvanic Skin Response (GSR)/Electrodermal Activity (EDA) Starting from 16Hz and 16nARMS
• Wide Range of Bioelectrical Impedance Analysis/ Spectroscopy (BIA/BIS) Frequencies from 1kHz to 500kHz
• High Currents at High Frequencies for Impedance Cardiography (ICG) Applications (e.g.,1.28mARMS at 100kHz) with Lockout for Lower Frequencies for Conformance with 60601-1
• High Input AC Dynamic Range of >1000mVP-P
• 4-Pin In-Situ Calibration Port (4-Wire Precision Resistor) Enables High-Quality Absolute Impedance Measurements
• DC Leads-Off Detect Capability
• Ultra-Low Power Lead-On Detection with Interrupt for System Wake-Up.
• Lead-On Detect Current: 0.7µA (typ) SYSTEM
• Shutdown Current of 0.6µA (Typ)
• 256 Word FIFO
• Flexible PLL-Based Timing Subsystem with Internal or External Clock Source
• PLL can be Synchronized with Adjacent Biosensor AFEs (such as the MAX86176 Photoplethsymography (PPG)/Electrocardiography (ECG) AFE)
• Configurable Interrupts Reduce µC Wake-Up Time and Save Power
• High-Speed Serial Peripheral Interface (SPI) and I2C Digital Interface Click here to ask an associate for production status of specific part numbers. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End Ordering Information appears at end of data sheet. 19-101213; Rev 2; 8/23 © 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

CSB/I2C_SEL AVDD DVDD DGND FCLK PHASE LOCKED LOOP TRIGD4 AGNDC3 AAF -40dB/dec 20-BIT SD ADC 20-BITAAF -40dB/dec EL1 A1 SINE WAVE DDS CURRENT OR VOLTAGE SOURCE +90O VREF BIP BIN EL2AA2 EL2BA3 CAL1A4 CAL2A5 EL3A B3EL3B EL4 B1 CAL3B5 CAL4B4 VTHH VTHL BIP VTLH VTLL BIN AVDD-0.2V 0.2V DRVN LEAD MONITORS BIP BIN LEAD BIAS ULTRA LOW POWER LEADS ON DETECT AHPFR LOADS EMI FILTER REF DDS I DAC VDRV DRVXC DRVSJ DRVXR DRVPDRVN VMID_RX VMID_TX DEMODULATION CLOCK STIMULUS DAC[9:0] BIN GUARD AMP BIP GUARD AMP IDRV DECIMATION FILTER PGA PGA BIOZ_VDRV_MAG[1:0] MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 2

MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 3

TABLE OF CONTENTS (CONTINUED) MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 4

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Information

Land Pattern Number Refer to Application Note 1891 Thermal Resistance, Four-Layer Board: Junction-to-Ambient (θJA) 52.43°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/ thermal-tutorial.

Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BIOZ Characteristics / Receive Path ADC Resolution 20 bits ENOB BIOZ_ADC_OSR = 128 16.3 bits BIOZ_ADC_OSR = 8 9.6 ADC Sample Rate Programmable, see Timing Subsystem 16 to 4546 sps Phase Measurement Accuracy at 50kHz Cole Impedance (324Ω || ( 232Ω + 22nF)) load at 50kHz after calibration, TA = +25°C. (Note 2, Note 3) -0.15 +0.15 deg Cole Impedance (800Ω || ( 2500Ω + 1nF)) load at 50kHz after calibration, TA = +25°C. (Note 2, Note 3) -0.1 +0.1 Phase Measurement Accuracy at 16Hz 453kΩ in series with 22nF load at 16Hz after calibration (Note 2), TA = +25°C. BIOZ_DC_RESTORE feedback resistance enabled in parallel with the load. ±1 deg MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 7

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Phase Measurement Accuracy at 500kHz 316Ω in series with 1nF load at 500kHz after calibration (Note 2), TA = +25°C. ±1 deg Phase Measurement Drift Drift of impedance phase at 50kHz after calibration (Note 2), drift relative to TA = +25°C. ±0.003 deg/°C Magnitude Measurement Accuracy at 50kHz Cole Impedance (324Ω || ( 232Ω + 22nF)) load at 50kHz after calibration, TA = +25°C. (Note 2, Note 3) -0.1 +0.1 Cole Impedance (800Ω || ( 2500Ω + 1nF)) load at 50kHz after calibration, TA = +25°C. (Note 2, Note 3) -0.1 +0.1 Magnitude Measurement Accuracy at 16Hz 453kΩ in series with 22nF load at 16Hz after calibration (Note 2), TA = +25°C. BIOZ_DC_RESTORE feedback resistance enabled in parallel with the load. ±1 % Magnitude Measurement Accuracy at 500kHz 316Ω in series with 1nF load at 500kHz after calibration (Note 2), TA = +25°C. ±1 % Magnitude Measurement Drift Drift of impedance magnitude at 50kHz after calibration (Note 2), drift relative to TA = +25°C ±0.017 %/°C Impedance Repeatability RBODY = 100kΩ, conditions for GSR (Note 4) 2.53 ΩRMS RBODY = 680Ω, conditions for respiration (Note 4) 8.94 mΩRMS RBODY = 25Ω, conditions for ICG/AED body impedance (Note 4) 0.80 DC Power Supply Rejection PSRR IDRV = 64μARMS, F_BIOZ = 1kHz, BIOZ_GAIN = 10V/V, RBODY = 1kΩ, VAVDD = VDVDD = 1.7V to 2.0V 900 7000 LSB/V VDRV = 100mVP-P, F_BIOZ = 64Hz, BIOZ_GAIN = 10V/V, VAVDD = VDVDD = 1.7V to 2.0V 150 1800 Channel Gain Selected by BIOZ_GAIN 1 to 10 V/V I vs. Q Channel Gain Matching 3σ with Cole Impedance (324Ω || 232Ω-22nF) load at 50kHz after calibration, TA = +25°C. (Note 2) 0.2 % AC Differential Input Signal Shift from small-signal gain < 0.6%, BIOZ_GAIN = 1V/V, fIN = 1kHz 1000 mVP-P Input Referred Voltage Noise (BIP, BIN) Integrated Noise BW = 0.05 to 100Hz, Gain = 10x, Current Drive Off, BIN = BIP = VCM 1.0 μVRMS Input Referred Current Noise DRVP and DRVN Disconnected, BIOZ_GAIN = 10V/V, F_BIOZ = 65.5kHz, SR_BIOZ = 256sps, BIOZ_DLPF = 64Hz, 200MΩ Lead Bias, BIOZ_AHPF = 5kHz 300 fA/√Hz MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 8

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Referred Offset Voltage RBODY = 0Ω, BIOZ_GAIN = 10V/V, BIOZ_AHPF = Bypass, Demodulation Disabled -6 +6 mV Differential Input Impedance Lead bias disabled, BIOZ_AHPF = 100Hz 48 MΩ Lead bias disabled, BIOZ_AHPF = bypass 10GΩ//2 pF Common-Mode Input Impedance Lead bias disabled, BIOZ_AHPF = bypass 3GΩ/2pF Input Analog High-Pass Filter Programmable, see Register Map. 100 to 10,000 Hz Input Analog High-Pass Filter Variation -50 +100 % Input Analog High-Pass Filter Resistor BIOZ_AHPF[3:0] = 1000 14 24 36 MΩ BIOZ_AHPF[3:0] = 1001 7 12 18 BIOZ_AHPF[3:0] = 1010 2.6 4.8 7 BIOZ_AHPF[3:0] = 1011 1.3 2.4 3.3 BIOZ_AHPF[3:0] = 1100 0.75 1.1 1.5 BIOZ_AHPF[3:0] = 1101 or 1110 0.3 0.47 0.65 Input Analog High-Pass Filter Bias Voltage VMID_RX 0.79 0.81 0.83 V Input Leakage Current BIP, BIN = VAVDD - 0.2V or AGND + I/Q Gain Matching 1kHz input, I/Q correlated with same phase, TA = +25°C, 1σ 0.2 % BIOZ Characteristics / Transmit Path DDS Sine-Wave Resolution 10 bits Current-Drive Amplitude Resolution See BIOZ_VDRV_MAG[1:0] and BIOZ_IDRV_RGE[1:0] 4 bits Current-Drive Range 0 BIOZ_IDRV_RGE[1:0] = 0x0, sine-wave drive with amplitude = 16nARMS, 32nARMS, 80nARMS, 160nARMS 16 160 nARMS Current-Drive Range 1 BIOZ_IDRV_RGE[1:0] = 0x1, sine-wave drive with amplitude = 320nARMS, 640nARMS, 1.6μARMS, 3.2μARMS 0.32 3.2 μARMS Current-Drive Range 2 BIOZ_IDRV_RGE[1:0] = 0x2, sine-wave drive with amplitude = 6.4μARMS, 12.8μARMS, 32μARMS, 64μARMS 6.4 64 μARMS Current-Drive Range 3 BIOZ_IDRV_RGE[1:0] = 0x3, sine-wave with amplitude = 128μARMS, 256μARMS, 640μARMS, 1.28mARMS 0.128 1.28 mARMS Short-Circuit Current BIOZ_DRV_MODE[1:0] = Voltage Mode, DRVP, DRVN shorted to AVDD, AGND 0.8 1.5 3 mA BIOZ_DRV_MODE[1:0] = H-Bridge Mode, DRVP, DRVN shorted to AVDD, AGND 2.0 3.5 6.0 MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 9

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current-Drive Accuracy IDRV ≥ 32nARMS -6 +6 IDRV = 16nARMS -10 +10 Current-Drive Total Harmonic Distortion (THD) IDRV = 64μARMS, fSTIM = 50kHz, RBODY = 1kΩ. Include odd harmonics h3, h5, and h7. 0.07 0.3 % Current-Drive Temperature Coefficient 128 ppm/°C Current-Drive Power Supply Rejection IDRV = 64μA, DC test mode 0.1 %/V Compliance Voltage BIOZ_DRV_MODE[1:0] = current mode, current accuracy ±1% 0.2 VAVDD - 0.2 V Compliance Monitor Thresholds EN_DRV_OOR = 1 0.27 VAVDD - 0.35 V Drive Frequency Range Programmable, see Timing Subsystem 0.016 to 500 kHz Drive Common-Mode Voltage VMID_TX Voltage at DRVSJ in current mode 0.79 0.81 0.83 V BIOZ Characteristics / Digital Filter Output Digital Low-Pass Filter BIOZ_DLPF[2:0] = 0x1 0.005 x SR_BIO Z Hz BIOZ_DLPF[2:0] = 0x2 0.02 x SR_BIO Z BIOZ_DLPF[2:0] = 0x3 0.08 x SR_BIO Z BIOZ_DLPF[2:0] ≥ 0x4 0.25 x SR_BIO Z Output Digital High-Pass Filter BIOZ_DHPF[1:0] = 0x1 0.00025 x SR_BIO Z Hz BIOZ_DHPF[1:0] ≥ 0x2 0.002 x SR_BIO Z BIOZ I/O Mux / DC Leads Off Full-Scale Current Selected by LOFF_IMAG[2:0] 5.5, 11.3, 22.5, 55, 110 nA Full-Scale Current Accuracy LOFF_IMAG = 110nA -40 +40 % Comparator Threshold VTHH, VTHL Selectable by DC_LOFF_THRESH[3:0] VMID ±200 VMID ±695 mV MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 10

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Comparator Threshold Accuracy LOFF_THRESH = VMID_RX ± 425mV -5 +5 % Full-Scale Electrode Resistance LOFF_IMAG = 100nA, LOFF_THRESH = VMID_RX ± 210mV 4 MΩ LOFF_IMAG = 10nA, LOFF_THRESH = VMID_RX ± 660mV 100 BIOZ I/O Mux / Lead Bias Lead Bias Impedance Lead bias enabled. RBIAS_VALUE = 0x0 50 MΩ RBIAS_VALUE = 0x1 100 RBIAS_VALUE = 0x2 200 Lead Bias Voltage Lead bias enabled 0.76 0.81 0.84 V BIOZ I/O Mux / Internal Resisitive Loads Internal BIA Resistive Load Nominal Value RVAL Selected by BMUX_RSEL 280, 600, 900, 5100 Ω Internal GSR Resistive Load Nominal Value RGSR Selected by BMUX_GSR_RSEL 25.7, 101, 505,100 kΩ Timing Subsystem PLL Lock Time Change in FCLK to FREQ_LOCK asserted, MDIV = 0x328 2 5 ms FCLK Input Frequency Must match CLK_FREQ_SEL 32.0 or 32.768 kHz Maximum FCLK Rise Time (10% to 90%) tRISE TA = +25°C, VIN = 0V or 1.8V, CLOAD = 15pF 100 ns Maximum FCLK Fall Time (90% to 10%) tFALL TA = +25°C, VIN = 0V or 1.8V, CLOAD = 15pF 100 ns PLL External Reference Jitter Cycle-to-cycle period, PLL_LOCK_WNDW = 0 3 nsRMS Internal FCLK FCLKINT CLK_FREQ_SEL = 32.0kHz TA = -40°C to FLCKINT CLK_FREQ_SEL = 32.768kHz TA = -40°C to Internal Reference Reference Output Voltage VREF TA = +25°C 0.985 1 1.015 V Reference Temperature Coefficient TCREF 42 ppm/°C MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 11

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BIA Supply Current VAVDD Supply Voltage VAVDD Verified during Power-Supply Rejection Ratio (PSRR) tests 1.7 1.8 2.0 V VDVDD Supply Voltage VDVDD Verified during Power-Supply Rejection Ratio (PSRR) tests 1.7 1.8 2.0 V BIA Supply Current (BIA/BIS Example at 1KHz) IAVDD + IDVDD PLL_CLK = 16.384MHz, F_BIOZ = 1kHz (KDIV = 64, M = 500, FCLK = 32768Hz, BIOZ_DAC_OSR = 256); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low power; BIOZ_GAIN = 10V/V; SR_BIOZ = 62.5sps (NDIV = 512, BIOZ_ADC_OSR = 512); IMAG = 32µA; I and Q ADCs enabled; Digital filters bypassed 926 µA BIA Supply Current (BIA/BIS Example at 50KHz) IAVDD + IDVDD PLL_CLK = 25.591808MHz, F_BIOZ = 49.984kHz (KDIV = 2, M = 781, FCLK = 32768Hz, BIOZ_DAC_OSR = 256); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low noise; BIOZ_GAIN = 10V/V; SR_BIOZ = 48.8125sps (NDIV = 1024, BIOZ_ADC_OSR = 512); IMAG = 32µA; I and Q ADCs enabled; Digital filters bypassed 1222 2700 μA BIA Supply Current (BIA/BIS Example at 100KHz) IAVDD + IDVDD PLL_CLK = 25.591808MHz, F_BIOZ = 99.968kHz (KDIV=2, M = 781, FCLK = 32768Hz, BIOZ_DAC_OSR = 128); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low noise; BIOZ_GAIN = 10V/V; SR_BIOZ = 48.8125sps (NDIV = 1024, BIOZ_ADC_OSR = 512); IMAG = 32µA; I and Q ADCs enabled; Digital filters bypassed 1227 μA BIA Supply Current (BIA/BIS Example at 250KHz) IAVDD + IDVDD PLL_CLK = 15.990784MHz, F_BIOZ = 249.856kHz (KDIV = 1, M = 488, FCLK = 32768Hz, BIOZ_DAC_OSR = 64); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low noise; BIOZ_GAIN = 10V/V; SR_BIOZ = 61sps (NDIV = 512, BIOZ_ADC_OSR = 512); IMAG = 32µA; I and Q ADCs enabled; Digital filters bypassed 1148 2700 µA BIA Supply Current (BIA/BIS Example at 500KHz) IAVDD + IDVDD PLL_CLK = 15.990784MHz, F_BIOZ = 499.712kHz (KDIV = 1, M = 488, FCLK = 32768Hz, BIOZ_DAC_OSR = 32); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low noise; BIOZ_GAIN = 10V/V; SR_BIOZ = 61sps (NDIV = 512, BIOZ_ADC_OSR = 512); IMAG = 32µA; I and Q ADCs enabled; Digital filters bypassed 1192 µA MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 12

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BIA Supply Current (Respiration Current Drive Example) IAVDD + IDVDD PLL_CLK = 16.384MHz, F_BIOZ = 32kHz (KDIV = 2, M = 500, FCLK = 32768HZ, BIOZ_DAC_OSR = 256); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low power; BIOZ_GAIN = 10V/V; SR_BIOZ = 62.5sps (NDIV = 512, BIOZ_ADC_OSR = 512); IMAG = 32µA; In-phase ADC only; BIOZ_DHPF = bypass, BIOZ_DLPF = 0.08 x SR_BIOZ 943 2300 µA BIA Supply Current (Respiration H-Bridge Example) IAVDD + IDVDD PLL_CLK = 16.384MHz, F_BIOZ = 32kHz (KDIV = 2, M = 500, FCLK = 32768Hz, BIOZ_DAC_OSR = 256); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low power; BIOZ_GAIN = 10V/V; SR_BIOZ = 62.5sps (NDIV = 512, BIOZ_ADC_OSR = 512); No load; In-phase ADC only; BIOZ_DHPF = bypass, BIOZ_DLPF = 0.08 x SR_BIOZ 328 µA BIA Supply Current (ICG Example) IAVDD + IDVDD PLL_CLK = 25.591808MHz, F_BIOZ = 99.968kHz (KDIV = 1, M = 781, FCLK = 32768Hz, BIOZ_DAC_OSR = 256); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low noise; BIOZ_GAIN = 10V/V; SR_BIOZ = 97.625sps (NDIV = 1024, BIOZ_ADC_OSR = 256); IMAG = 1.28mA; In-phase ADC only; BIOZ_DHPF = 0.002 x SR_BIOZ, BIOZ_DLPF = 0.25 x SR_BIOZ 2280 µA BIA Supply Current (GSR/EDA Example) IAVDD + IDVDD PLL_CLK = 14.024704MHz, F_BIOZ = 53.5Hz (KDIV = 1024, M = 428, FCLK = 32768Hz, BIOZ_DAC_OSR = 256); BIOZ_DRV_MODE = current; BIOZ_INA_MODE = low power; BIOZ_GAIN = 1V/V; SR_BIOZ = 53.5sps (NDIV = 512, BIOZ_ADC_OSR = 512); IMAG = 320nA; In-phase ADC only; Digital filters bypassed 353 680 µA Shutdown Current IAVDD + IDVDD TA = +25°C 1.0 3 μA Digital I/O Characteristics Input Voltage Low VIL SDI/SDA, SCLK/SCL, TRIG, CSB/ I2C_SEL, FCLK 0.4 V Input Voltage High VIH SDI/SDA, SCLK/SCL, TRIG, CSB/ I2C_SEL, FCLK 1.4 V Input Hysteresis VHYS SDI/SDA, SCLK/SCL, TRIG, CSB/ I2C_SEL, FCLK 430 mV Input Capacitance CIN SDI/SDA, SCLK/SCL, TRIG, CSB/ I2C_SEL, FCLK 10 pF MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 13

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage Current IIN SDI/SDA, SCLK/ SCL, TRIG, CSB/ I2C_SEL, FCLK TA = +25°C, VIN = 0V or 1.8V -0.1 0.01 +0.1 μA Output Voltage Low VOL SDO/ADDR, INT ISINK = 4mA 0.4 V Output Voltage High VOH SDO/ADDR, INT ISOURCE = 4mA VDVDD - 0.4 V Open-Drain Output Voltage Low VOL_OD INT_OCFG = 0x0 ISINK = 4mA 0.4 V I2C Timing Characteristics (Note 3) I2C Write Address SDO/ADDR = 0 D0 Hex SDO/ADDR = 1 D2 I2C Read Address SDO/ADDR = 0 D1 Hex SDO/ADDR = 1 D3 Serial Clock Frequency fSCL 0 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Hold Time START and Repeat START Condition tHD,STA 0.6 µs SCL Pulse-Width Low tLOW 1.3 µs SCL Pulse-Width High tHIGH 0.6 µs Setup Time for a Repeated START Condition tSU,STA 0.6 µs Data Hold Time tHD,DAT 0 900 ns Data Setup Time tSU,DAT 100 ns Setup Time for STOP Condition tSU,STO 0.6 µs Pulse-Width of Suppressed Spike tSP 0 50 ns Bus Capacitance CB 400 pF SDA and SCL Receiving Rise Time tR CB = bus capacitance in pF 20 + 0.1 x CB 300 ns SDA and SCL Receiving Fall Time tF CB = bus capacitance in pF 20 + 0.1 x CB 300 ns SDA Transmitting Fall Time tTF CB = bus capacitance in pF 20 + 0.1 x CB 300 ns SPI Timing Characteristics (Note 3) SCLK Frequency fSCLK 0.1 24 MHz SCLK Period tCP 40 ns SCLK Pulse-Width High tCH 18 ns SCLK Pulse-Width Low tCL 18 ns MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 14

Electrical Characteristics (continued) (AVDD = 1.8V, DVDD = 1.8V, FCLK = 32.768Hz, TA = +25°C, min/max are from TA = -40°C to +85°C, unless otherwise noted, Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CSB Fall to SCLK Rise Setup Time tCSS0 Applies to first SCLK rising edge after CSB goes low. 20 ns CSB Fall to SCLK Rise Hold Time tCSH0 Applies to inactive rising edge preceding first rising edge. 5 ns Last SCLK Rise to CSB Rise tCSH1 Applies to last SCLK rising edge in a transaction. 20 ns Last SCLK Rise to Next CSB Fall tCSF Applies to last SCLK rising edge to next CSB falling edge (new transaction). 60 ns CSB Pulse-Width High tCSPW 40 ns SDI to SCLK Rise Setup Time tDS 5 ns SDI to SCLK Rise Hold Time tDH 5 ns SCLK Fall to SDO Transition tDOT CLOAD = 30pF 15 ns CSB Fall to SDO Enabled tDOE CLOAD = 0pF 10 ns CSB Rise to SDO Hi-Z tDOZ Disable Time 5 ns TRIG Pulse-Width tTRIG 1 x tFCLK s ESD PROTECTION E1, E2A, E2B, C1, C2, C3, C4, E3A, E3B, E4 IEC61000-4-2 Contact Discharge ±8 kV Air Discharge ±6 Note 1: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. All register settings use default values, unless otherwise noted in specific EC conditions. Note 2: Overall accuracy must include calibration resistor accuracy and overall calibration accuracy. Calibration uses an external 32.768kHz, 2.5nsRMS jitter, ±5ppm TC oscillator with a 680Ω external calibration resistor. The calibration resistor and Cole impedance are measured to within 0.05% magnitude and 0.1° phase accuracy using a calibrated Zurich Instruments MFIA. Note 3: Guaranteed by design and characterization. Not tested in production. Note 4: a. BIOZ_DRV_MODE = 0x0, IDRV = 160nARMS, F_BIOZ = 16Hz, SR_BIOZ = 16sps, BIOZ_GAIN = 10V/V, BIOZ_DLPF = 0x4, BIOZ_AHPF = 24MΩ with external 47nF BIP and BIN capacitors. Effective signal band = DC to 4Hz. b. BIOZ_DRV_MODE = 0x0, IDRV = 32µARMS, F_BIOZ = 32kHz, SR_BIOZ = 31.25sps, BIOZ_GAIN = 10V/V, BIOZ_DLPF = 0x3, BIOZ_AHPF = 2kHz. Effective signal band = DC to 2.5Hz. c. BIOZ_DRV_MODE = 0x0, IDRV = 1.28mARMS, F_BIOZ = 64kHz, SR_BIOZ = 250sps, BIOZ_GAIN = 10V/V, BIOZ_AHPF = 5kHz. Effective signal band = DC to 62.5Hz. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 15

Typical Operating Characteristics (VDVDD = VAVDD = +1.8V, TA = +25°C, unless otherwise noted.) MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 16

Typical Operating Characteristics (continued) (VDVDD = VAVDD = +1.8V, TA = +25°C, unless otherwise noted.) MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 17

Typical Operating Characteristics (continued) (VDVDD = VAVDD = +1.8V, TA = +25°C, unless otherwise noted.) MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 18

Typical Operating Characteristics (continued) (VDVDD = VAVDD = +1.8V, TA = +25°C, unless otherwise noted.) 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 -50050100 VREF(V) TEMPERATURE (°C) VREFvs. TEMPERATUREtoc31 MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 19

25 WLP (5x5)

2.03mm x 2.03mm, 0.4mm PITCH CAL3 1 2 4 5 EL1 EL2B CAL2 E D C B A AVDD CAL4 DRVXR DVDD INTDGND CSB/I2C_SEL AGND TRIG EL2A DRVSJ SDO/ADDR DRVXCFCLK SDI/SDA EL3BEL4 EL3A VREF SCLK/SCL CAL1 TOP VIEW (BUMP SIDE DOWN) Pin Description PIN NAME FUNCTION Power C1 AVDD Analog Core Supply Voltage. Bypass to AGND with a 0.1µF and a 10µF X5R 0603 capacitor or equivalent effective capacitance. D1 DVDD Digital Core Supply Voltage. Bypass to DGND with a 0.1µF and a 10µF X5R 0603 capacitor or equivalent effective capacitance. Recommend driving AVDD and DVDD from the same voltage rail so that AVDD and DVDD come up together. C3 AGND Analog Power and Reference Ground. Connect to the PCB ground plane. E1 DGND Digital Ground for both Digital Core and I/O Pad Drivers. Recommended to connect to AGND plane. Electrode Connections A1 EL1 Electrode 1 Connection. EL1 is normally connected to the DRVP current generator output, but can be switched to the receive channel’s BIP input under program control. A2 EL2A Electrode 2A Connection. EL2A or EL2B are normally connected to the receive channel’s BIP input, but can be switched to connect to the DRVP current generator output under program control. Two EL2 inputs are provided to use the device for both GSR/EDA applications that require an external AC-coupling capacitor and BIA/BIS applications that use the internal AHPF, and thus do not require an external AC-coupling capacitor. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 20

Pin Description (continued) PIN NAME FUNCTION A3 EL2B Electrode 2B Connection. See description for EL2A. B1 EL4 Electrode 4 Connection. EL4 is normally connected to the DRVN current generator output, but can be switched to the receive channel’s BIN input under program control. B2 EL3A Electrode 3A Connection. EL3A or EL3B are normally connected to the receive channel’s BIN input, but can be switched to connect to the DRVN current generator output under program control. Two EL3 inputs are provided to use the device for both GSR/EDA applications that require an external AC-coupling capacitor and BIA/BIS applications that use the internal AHPF, and thus do not require an external AC-coupling capacitor. B3 EL3B Electrode 3B Connection. See description for EL3A. Calibration Support A4 CAL1 Calibration Port 1. Connects the internal DRVP node to an external reference resistor when calibration is enabled. A5 CAL2 Calibration Port 2. Connects the internal BIP node to an external reference resistor when calibration is enabled. B5 CAL3 Calibration Port 3. Connects the internal BIN node to an external reference resistor when calibration is enabled. B4 CAL4 Calibration Port 4. Connects the internal DRVN node to an external reference resistor when calibration is enabled. PLL D3 FCLK External Clock Input. Connect to a 32.0kHz or 32.768kHz external clock source (optional). When not used, it can be left unconnected. Control Interface E4 SCLK/SCL SPI Clock in SPI Mode or I2C Clock in I2C Mode. E3 SDI/SDA SPI Data Input in SPI Mode or I2C Data Input and Output in I2C Mode. E2 SDO/ADDR SPI Data Output in SPI Mode or I2C Address Select in I2C Mode. Do not leave unconnected. D2 CSB/ I2C_SEL Active-Low Chip Select Input in SPI Mode. Pull high or connect to DVDD to select I2C Mode. Do not leave unconnected. E5 INT Interrupt Output. INT is a programmable active-high/active-low/open-drain status output. It can be used to interrupt an external device. When not used, it can be left unconnected. D4 TRIG PLL Synchronization Input. When not used, connect to DGND. Reference C2 VREF ADC Reference Buffer Output. Connect a 1μF X5R ceramic capacitor between VREF and AGND. C4 DRVSJ Drive Summing Junction Connection. Virtual AC ground in current mode. C5 DRVXR Drive Amplifier External Resistor. Connect a precision resistor between DRVXR and DRVXC if setting the BioZ drive current externally. Leave unconnected if using internal current settings. D5 DRVXC Drive Amplifier External Capacitor. Connect a 47nF capacitor between DRVXC and DRVSJ to AC- couple the VDRV and IDRV amplifiers in sine-wave current-drive applications. Otherwise, short DRVXC to DRVSJ. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 21

The MAX30009 is a complete, integrated data acquisition system ideal for respiration, Galvanic Skin Response (GSR) and Electrodermal Activity (EDA), Bioimpedance Analysis/Spectroscopy (BIA/BIS), Impedance Cardiography (ICG), and numerous other applications. It is designed for the demanding requirements of medical, mobile, and wearable devices, and requires minimal external hardware components for integration. The BioZ transmit channel has an independent current stimulus circuit to provide injected body currents. The stimulus current generation circuit can be supplied in a four-electrode (tetrapolar) as well as two-electrode (bipolar) manner. This injected current is programmable and available over a wide frequency range (16Hz to 500kHz) and a wide range of stimulus current magnitudes (16nA RMS, up to 1.28mA RMS maximum). These ranges support Galvanic Skin Response (GSR) and Electrodermal Activity (EDA) measurements, Bioimpedance Analysis/Spectroscopy (BIA/BIS) applications, and Impedance Cardiography (ICG) measurements such as cardiac output and stroke volume, or Impedance Plethysmography (IPG) measurements. The BioZ receive channel also has high input impedance, low noise, high Common-Mode Rejection Ratio (CMRR), programmable gain, various low-pass and high-pass filter options, two high-resolution analog-to-digital converters, and simultaneous I and Q measurement capability to provide resistance and reactance measurements for BIA/BIS applications. It also includes DC lead-off detection, drive lead-off detection, ultra-low-power lead-on detection during standby mode, and extensive calibration features and programmable resistive loads for built-in self-test. Soft power-up sequencing ensures no large transients are injected into the electrodes. The MAX30009 provides a calibration port for a four-wire external precision reference resistance to use during calibration. This calibration is required when using the MAX30009 for bioimpedance measurements needing absolute accuracy such as BIA/BIS or Automated External Defibrillator (AED) body-impedance. The four-wire calibration port can also be used to support multiple calibration resistances. Alternatively, there are trimmed load resistors internal to the device that can be used for calibration, but they are not as accurate as using an external reference resistor. The MAX30009 is fully adjustable through software registers and the digital output data is stored in a 256-word FIFO. The FIFO allows the MAX30009 to be connected to a microcontroller or processor on a shared I 2C or Serial Peripheral Interface (SPI) bus. The MAX30009 operates in fully autonomous mode for low-power battery applications. The MAX30009 operates on a 1.8V main supply voltage, and can be configured for low-power consumption, enabling long battery life. Timing Subsystem The MAX30009 timing subsystem is shown in Timing Subsystem, which includes all the register bits and formulas needed for setting the BioZ sample rate and stimulus frequency. REF_CLK is sourced either from an external oscillator on the FCLK or from the internal slow oscillator clock INT_FCLK, depending on the REF_CLK_SEL6 setting. The MAX30009 timing system offers a great deal of flexibility. However, certain considerations must be taken into account when configuring the timing system. The following sections describe these considerations in detail. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 22

PLL_EN REF_CLK_SEL MDIV[9:0] CLK_FREQ_SELCLK_FINE_TUNE[4:0] BIOZ_ADC_OSR[2:0] NDIV 512,1024 KDIV[3:0]

1 TO 8192

BIOZ_DAC_OSR[1:0] 32,64,128,256 32768Hz 32000Hz 0 REF_CLK

0 BIOZ

BIOZ_ADC_CLK BIOZ_SYNTH_CLK PLL_CLK REGISTER BIT SIGNAL NAME C_BIOZ REPRESENTS THE NUMBER OF STIMULUS CYCLES INTEGRATED PER ADC SAMPLE AND MUST BE 0.5 OR AN INTEGER. M = MDIV + 1 14MHz < PLL_CLK < 28MHz M = 438 TO 875 FOR REF_CLK = 32.0kHz M = 427 TO 854 FOR REF_CLK = 32.768kHz INT_FCLK 16.0kHz TO 36.375kHz 4096Hz TO 28MHz N x BIOZ_ADC_OSR K x BIOZ_DAC_OSR F_BIOZ SR_BIOZ =C_BIOZ = F_BIOZ = PLL_CLK K x BIOZ_DAC_OSRSR_BIOZ = PLL_CLK N x BIOZ_ADC_OSR MUST MATCH FCLK IF REF_CLK_SEL = 1 NOTE: BITFIELD NAMES IN THE ABOVE EQUATIONS REPRESENT DECODED VALUES, NOT BINARY VALUES. SEE THE REGISTER MAP FOR DECODE INFORMATION. Clock Sources The MAX30009 timing system incorporates two internal slow oscillators, 32.0kHz and 32.768kHz, and the oscillator with the desired frequency can be selected by setting CLK_FREQ_SEL5. If REF_CLK_SEL6 = 0, the internal slow oscillator selected by CLK_FREQ_SEL provides the reference clock to the PLL circuit used as the time base for the BioZ channel. If REF_CLK_SEL = 1, the oscillator on the FCLK (either 32.0kHz or 32.768kHz) becomes the source of REF_CLK. Even when using the external oscillator on FCLK, the CLK_FREQ_SEL must be set according to the frequency of the external clock source. Use a low-jitter external oscillator with < 347ppm of frequency accuracy to meet IEC60601-2-47 timing accuracy compliance. The FCLK source must be an active-drive clock, not only a crystal. The two internal slow oscillators, 32.0kHz and 32.768kHz in MAX30009, are factory trimmed and exhibit a drift with temperature (primary cause of drift) of less than ±1% over the temperature range of 0°C to +50°C. If this level of stability is inadequate, then the MAX30009 offers a fine adjust register CLK_FINE_TUNE4:0, which can be used in combination with a highly stable crystal based Real-Time Clock (RTC) oscillator in the host microcontroller to trim out the drift of the on-chip slow oscillator. By counting the time between the MAX30009 generated interrupts using the microcontroller-based RTC, it is possible to compute the error in the slow oscillator frequency and trim it to within ±0.1% (typ) of the microcontroller-based RTC. Using this approach, it is possible to achieve accuracy near that of a crystal oscillator as the phase noise of the MAX30009 slow oscillator is low and the drift is primarily due to temperature. Phase-Locked Loop (PLL) and PLL Synchronization The MAX30009 timing subsystem in Timing Subsystem allows the use of an internal PLL synchronized to either an internal or external clock source used by the BioZ channel. The PLL generates an output clock (PLL_CLK) that operates over a 14MHz to 28MHz frequency range. The frequency of PLL_CLK is selected by the frequency of REF_CLK and the M divider value, which is set in MDIV[9:0](0x17, 0x18), MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 23

where M = MDIV + 1. The 10-bit MDIV register field must be set such that the PLL output frequency (PLL_CLK) is between 14MHz and 28MHz. For a reference clock of 32.768kHz, this means a valid MDIV range is 426 to 853 (M = 427 to 854). For a reference clock of 32.0kHz, this means a valid MDIV range of 437 to 874 (M = 438 to 875). Soft-reset using RESET0 is not allowed when PLL is enabled (PLL_EN0 = 1). The BioZ reference must be enabled (BIOZ_BG_EN2 = 1) before PLL_EN is set to 1, and can take up to 6ms to settle. Sequence of Operation When PLL is Used When enabling or disabling PLL, the proper sequence of operations must be followed. This section describes the recommended sequence of operations for various scenarios when PLL is used. Enabling and Disabling the PLL The following sequence is recommended when enabling and disabling the PLL.

• Disable BioZ, if enabled.
• Enable PLL by setting PLL_EN to 1.
• Wait for PLL to lock using either the FREQ_LOCK3 or PHASE_LOCK2 status bits.
• Enable BioZ I and Q, as needed.
• Disable BioZ when data collection is done.
• Disable PLL by setting PLL_EN to 0. Entering and Exiting Shutdown The following sequence is recommended when putting the device into a shutdown state and to exit it.
• Disable BioZ, if enabled.
• Disable PLL by setting PLL_EN to 0, if enabled.
• Set SHDN to 1, to enter the shutdown mode.
• ...
• Set SHDN to 0 to enter the normal mode.
• Enable PLL by setting PLL_EN to 1.
• Enable BioZ I and Q as needed.
• ... Soft-Reset Sequence The following sequence is required when resetting the device using the RESET bit. Failure to follow this sequence may result in registers becoming unresponsive until a power-on reset is performed.
• Set BIOZ_BG_EN = 1.
• Set SHDN = 0.
• Set REF_CLK_SEL = 0.
• Set PLL_EN = 0.
• Wait for 1ms.
• Set RESET = 1 to reset all registers.
• Enable PLL by setting PLL_EN to 1.
• ... PLL Synchronization The MAX30009 provides a PLL synchronization feature for use with multiple MAX30009, MAX86176, MAX30005, or MAX86178 AFEs in a system. This allows the PLLs of the multiple AFEs to remain synchronized and output synchronized samples. PLL synchronization uses either the TRIG pin or the broadcast feature. Both options are discussed as following. PLL Synchronization Using the TRIG Pin When the TRIG pin is used for PLL synchronization, one AFE is set up to act as a controller and initiates the PLL and timing subsystem synchronization process, while the other(s) act(s) as a target(s). Alternatively, all the AFEs together act as targets and the microcontroller acts as the controller of this process. In either case, all AFEs should use the same MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 24

Figure 2. Timing System Synchronization with MAX30009 as a Target the same address in all the devices, and if all the PLLs use the same external reference clock for their PLLs. FCLK after TIMING_SYS_RESET bit is set to 1; thus, synchronizing all the PLLs.

• Disable BioZ by setting BIOZ_BG_EN2, BIOZ_Q_EN1, and BIOZ_I_EN0 to 0, if enabled.
• Reset the part and flush the FIFO by setting SHDN1 to 1.
• Then set SHDN = 0 on all the parts.
• Wait for 6ms.
• Program the configuration registers for BioZ as needed:
• To synchronize multiple devices, the BioZ sample rate should be the same on all the parts.
• The broadcast feature can be used to program the common registers.
• Program FIFO_A_FULL7:0 as desired, and A_FULL_EN17 = 1 on one of the parts, which becomes the primary part (other parts are secondary parts).
• Enable PLL by setting PLL_EN0 to 1 on all the devices (using the broadcast feature or separately).
• Wait for PLL to lock on all devices.
• Enable BioZ by setting BIOZ_BG_EN to 1, and BIOZ_Q_EN and BIOZ_I_EN as needed using the broadcast feature.
• Using the broadcast feature, set TIMING_SYS_RESET to 1 on all the devices.
• All the devices reset the N-divider, and restart the state machines within the current clock cycle.
• Disable BioZ when data collection is done. Note: TIMING_SYS_RESET can be set to 1 before or after enabling BioZ.
• Disable PLL by setting PLL_EN to 0. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 26

Figure 3. Timing System Synchronization for MAX30009 Using the Broadcast Feature

• MDIV[9:0](0x17, 0x18)
• NDIV7
• KDIV4:1
• BIOZ_ADC_OSR5:3
• BIOZ_DAC_OSR7:6
• CLK_FREQ_SEL5
• REF_CLK_SEL6 The BioZ sample rate is calculated as follows.
• SR_BIOZ = PLL_CLK NDIVxBIOZ_ADC_OSR
• BIOZ_ADC_CLK = PLL_CLK NDIV (must be between 16.0kHz and 36.375kHz)
• PLL_CLK = MxREF_CLK (must be between 14MHz and 28MHz) REF_CLK is either 32.0kHz or 32.768kHz depending on the state of the CLK_FREQ_SEL and REF_CLK_SEL bits, and M = MDIV +1. The BioZ stimulus frequency is set by the following equation.
• F_BIOZ = PLL_CLK KDIVxBIOZ_DAC_OSR
• BIOZ_SYNTH_CLK = PLL_CLK KDIV (must be between 4096Hz and 28MHz) The ratio of F_BIOZ to SR_BIOZ must be 0.5 or an integer, so that each BioZ sample is integrated over a given number of stimulus cycles. This ratio, C_BIOZ, is calculated by the following equation.
• C_BIOZ = F_BIOZ SR_BIOZ = NDIVxBIOZ_ADC_OSR KDIVxBIOZ_DAC_OSR The procedure for setting the BioZ timing parameters is as follows: First decide the target stimulus frequency (F_BIOZ) for the BioZ measurement. If F_BIOZ < 54,668Hz: 1. Set BIOZ_DAC_OSR = 256. 2. Set KDIV to get PLL_CLK in range. 3. Calculate MDIV + 1 = ROUND(PLL_CLK / REF_CLK). 4. Set NDIV to get BIOZ_ADC_CLK in range. 5. Set BIOZ_ADC_OSR so that C is an integer. 6. If F_BIOZ = BIOZ_ADC_CLK / 8, set BIOZ_CH_FSEL = 1, otherwise set to 0. 7. If F_BIOZ = BIOZ_ADC_CLK / 2, set BIOZ_INA_CHOP_EN = 0, otherwise set to 1. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 27

1. Set BIOZ_DAC_OSR to get PLL_CLK in range.
2. Calculate MDIV + 1 = ROUND(PLL_CLK / REF_CLK).
3. Set NDIV to get BIOZ_ADC_CLK in range.
4. Set BIOZ_ADC_OSR so that C is an integer.
5. Set BIOZ_INA_CHOP_EN = 1.

Table 1. Example Calculations of BioZ Configuration Parameters for F_BIOZ < Table 2. Example Calculations of BioZ Configuration Parameters for F_BIOZ >

channel, the demodulation is done at the same frequency as the stimulus. Table 3. Common BioZ Stimulus Frequencies and Sample Rates with REF_CLK =

Table 4. FIFO Data Format FIFO_DATA_RDY or A_FULL interrupt.

and sample rate are determined by the timing subsystem (see the Timing Subsystem section). magnitudes, as shown in Figure 5. Each type of stimulus can operate over frequencies between 16Hz and 806kHz. Figure 4. BioZ System Block Diagram

being driven through the body. A 47nF capacitor is recommended for all applications. at the lowest value for other applications. options available for MAX30009.

1. To ensure patient safety, some current amplitude and frequency combinations are not allowed (see Table 5 ). If

auxiliary current limitations.

1. When using stimulus currents greater than 640µA RMS, EL1 and EL4 must be used for DRVP and DRVN,

respectively. Electrode pins EL2A, EL2B, EL3A, and EL3B are not designed to support currents above 640µA RMS.

1. The current amplitude should be chosen to not exceed 1000mV P-P at the BIP and BIN pins based on the network

impedance at the current injection frequency. Table 5. Stimulus Current Options

10 BIT DDS

Figure 6. Bioimpedance Stimulus Generator — Sine-Wave Current Mode The sine-wave current generates a voltage between the ELx pins connected to DRVP and DRVN. where: ZEDRVP and ZEDRVN = Electrode impedance at DRVP and DRVN. this issue, either use a lower drive current or reduce the electrode impedance. EL2B, EL3A, and EL3B are not available for voltage mode stimulation.

Figure 7. Bioimpedance Stimulus Generator — Sine-Wave Voltage Mode electrode impedance, body impedance with its variable component, a second electrode impedance, and R SERIES_EL4. assigned to EL1 and DRVN must be assigned to EL4.

Figure 9. BioZ Receive Channel implement High-Pass Filter (HPF) and Low-Pass Filter (LPF) selections. or bypassed using BIOZ_LPF5:3. corner frequency. The decimation filter in the ADC has a bandwidth of approximately 0.26 x SR_BIOZ. demodulation applies a scaling factor of 2 / π to the DC component, as shown in Figure 10. stimulus mode according to the following equation. BIOZ_GAIN = Options1V/V, 2V/V, 5V/V, and 10V/V. IMAG = Stimulus current in APK set by BIOZ_VDRV_MAG5:4 and BIOZ_IDRV_RGE3:2. The input-referred voltage amplitude can likewise be calculated with the following equations.

For voltage stimulus modes, the impedance can be calculated from an impedance divider with the series resistors. be performed for these applications, but these conversions are not strictly necessary. Figure 10. Square-Wave Demodulation for a Sine-Wave Stimulus (INA and PGA Gain Not Shown) frequency settings shown in Table 7 and BIOZ_AHPF7:4 = 5kHz. Table 6. BioZ Receive Channel Input-Referred Noise, 256sps

Table 6. BioZ Receive Channel Input-Referred Noise, 256sps (continued) Table 7. Input-Referred Noise Frequency Settings more precision external resistors with more details shown in Figure 16.

Figure 11. BioZ Input/Output MUX bandwidth, and the common-mode pole is set at least a decade below the AM radio band (535kHz).

• ±8kV using the Contact Discharge method specified in IEC61000-4-2 ESD.
• ±6kV using the Air-Gap Discharge method specified in IEC61000-4-2 ESD. BioZ Lead Bias The MAX30009 limits the BIP and BIN DC input range to 0.5V to V AVDD - 0.75V. This range can be maintained either through external or internal lead biasing. Internal DC lead biasing consists of 50MΩ, 100MΩ, or 200MΩ selectable resistors from BIP and BIN to V MID_RX that MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 41

EN_RBIAS_BIN0 to enable lead bias. GSR_LOAD_EN5 to set the resistor value. The BIA/BIA resistive loads can also be used as internal calibration resistors. See BIST_R_ERROR7:0 for details. Figure 12. Programmable Resistor Load circuit. The relevant techniques depend on the electrode configuration (bipolar or tetrapolar) and which electrode is off. digital circuitry after the receive channel ADC. with the lead-off circuit functionality. The DC lead-off detection circuit provides matched source and sink currents injected into the BIP and BIN electrodes.

DC lead-off circuitry provides two sets of dual comparators to test if the differential voltage is too high. impedance of the specific electrodes used in the application. BIOZ_LOFF_THRESH3:0. See Figure 13 for an example of the threshold and timing behavior. enabled in addition to EN_LOFF_DET. CLK_FREQ_SEL5, before the DRV_OOR status bit is asserted. is suitable for stimulus frequencies above 1kHz, and external capacitors are need for stimulus frequencies under 1kHz. Table 8. BioZ Lead-Off Cases

Table 8. BioZ Lead-Off Cases (continued) Figure 13. BioZ DC Lead-Off Behavior

• The total impedance between BIP and BIN is below 40MΩ (typ) due to both electrodes contacting the body.
• The total impedance between BIP and AGND is below 45MΩ (typ) due to the the BIP electrode contacting a body that is coupled to AGND. For example, if the MAX30009 system is coupled to earth ground through a power or data cable, and the body is also coupled to earth ground, then a low-impedance path can pull the BIP electrode low.
• The BIP electrode is contacting the body and has a large half-cell potential. The half-cell potential can push the BIP voltage below the threshold. If the LON interrupt is enabled by LON_EN17, an interrupt is generated to alert the host microcontroller of the lead-on condition. This interrupt allows the microcontroller to sleep when the system is not in use, and only wake up when the device electrodes are touched. Upon receiving an interrupt and waking up, the microcontroller should read the LON status register to determine if a lead-on condition occurred. Because of the bit's clear-on-read behavior, read the status register a second time to determine if the lead-on condition persists. BioZ Calibration The MAX30009 can be calibrated, and can achieve impedance magnitude errors of 0.1% and impedance phase errors of 0.1°. The calibration can be performed at the factory by applying a precision resistor to the device electrodes, or on- board by connecting a precision resistor to the CALx pins. To achieve 0.1% accuracy, the calibration resistor(s) must have 0.05% tolerance, or be measured by an external reference with 0.05% accuracy. If using an on-board calibration, the reference resistor (RCAL) should have a low temperature coefficient and should be connected to the calibration port, as shown in Figure 16. To connect the on-board RCAL, assert MUX_EN1 and CAL_EN0. The calibration consists of measuring the I and Q offsets, and magnitude and phase coefficients at each measurement frequency, according to the following steps. Registers not mentioned in the following steps should be set to the values intended for use during measurement. 1. Set the synthesis frequency to the desired frequency. 2. Measure the I and Q offsets: 1. Set the stimulus current magnitude to the minimum 16nA RMS by setting BIOZ_VDRV_MAG5:4 and BIOZ_IDRV_RGE3:2 to 0x0. 2. Enable BIOZ_DRV_RESET5 to apply a short circuit across the load. 3. Set BIOZ_I_EN0 and BIOZ_Q_EN1 to 1 to enable measurement. 4. Record data until the impedance signal is settled, and then record the average impedance in Ω (I_offset [Ω], Q_offset[Ω]). Settling time varies with sample rate, filter selections, and other settings. 5. Note: I_offset and Q_offset should be calculated using the intended measurement current magnitude, not the minimum 16nARMS. 3. Measure the calibration resistor with both channels set to in-phase: 1. Set the stimulus current to the desired value by adjusting BIOZ_VDRV_MAG5:4 and BIOZ_IDRV_RGE3:2. 2. Disable BIOZ_DRV_RESET5. 3. Set BIOZ_Q_CLK_PHASE3 to 1, which shifts the Q-channel's demodulation clock to in-phase. 4. Set BIOZ_I_EN0 and BIOZ_Q_EN1 to 1 to enable measurement. 5. Record data until the impedance signal is settled, and then record the average impedance in Ω (I_rcal_in [Ω], Q_rcal_in [Ω]). 4. Measure the calibration resistor with both channels set to quadrature-phase: 1. Set BIOZ_Q_CLK_PHASE3 to 0. 2. Set BIOZ_I_CLK_PHASE2 to 1, which shifts the I-channel's demodulation clock to quadrature phase. 3. Set BIOZ_I_EN0 and BIOZ_Q_EN1 to 1 to enable measurement. 4. Record data until the impedance signal is settled, and then record the average impedance in Ω (I_rcal_quad [Ω], Q_rcal_quad [Ω]). 5. Subtract the offsets from the resistor measurements: 1. I_cal_in [Ω] = I_rcal_in - I_offset 2. Q_cal_in [Ω] = Q_rcal_in - Q_offset 3. I_cal_quad [Ω] = I_rcal_quad - I_offset 4. Q_cal_quad [Ω] = Q_rcal_quad - Q_offset 6. Calculate the calibration magnitude and phase delay coefficients for each channel: MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 46

1. I_coef = √(I_cal_in2 + I_cal_quad2) / RCAL 2. Q_coef = √(Q_cal_in2 + Q_cal_quad2) / RCAL 3. I_phase_coef [°] = arctan(I_cal_quad / I_cal_in) x 180° / π 4. Q_phase_coef [°] = arctan(-Q_cal_quad / -Q_cal_in) x 180° / π To apply the calibration coefficients to a measured impedance, follow these steps. 1. Measure I and Q load impedances (I_load [Ω] and Q_load [Ω]). 2. Subtract the offsets from the load impedances: 1. I_load_offset [Ω] = I_load - I_offset 2. Q_load_offset [Ω] = Q_load - Q_offset 3. Apply I and Q coefficients to correct magnitude and phase delay of each channel: 1. I_cal_real [Ω] = (I_load_offset / I_coef) x cos(I_phase_coef x π / 180) 2. I_cal_imag [Ω] = (I_load_offset / I_coef) x sin(I_phase_coef x π / 180) 3. Q_cal_real [Ω] = (Q_load_offset / Q_coef) x sin(Q_phase_coef x π / 180) 4. Q_cal_imag [Ω] = (Q_load_offset / Q_coef) x cos(Q_phase_coef x π / 180) 4. Calculate the corrected load impedance: 1. Load_real [Ω] = I_cal_real - Q_cal_real 2. Load_imag [Ω] = I_cal_imag + Q_cal_imag 3. Load_mag [Ω] = √(Load_real2 + Load_imag2) 4. Load_angle [°] = arctan(Load_imag / Load_real) x 180 / π MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 47

Figure 16. Calibration Port Connections MAX30009 has two features to minimize the effect of these receive-channel parasitic capacitances. more phase lag than the BIN side, creating a potential source of inaccuracy.

which enables an inverse capacitive load on each input. protocols for both interfaces. by a single-byte data word either written to or read from the register location provided in the first byte. Figure 17. Detailed SPI Timing Diagram 24th rising edge of SCLK by tCSA, as shown in Figure 17, results in the transaction being aborted. are provided, the device reads back zeros.

Figure 20. SPI FIFO Burst Mode Read Transaction controller reading data from the MAX30009 transmits the proper target address, followed by a series of nine SCL pulses. and undershoot of the bus signals.

Figure 21. Detailed I2C Timing Diagram SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). the same as a START condition (high-to-low transition with SCL high), but it is sent after a START condition. high pulse as the START condition.

Figure 22. I2C START, STOP, and REPEATED START Conditions high, the target address is 0xD2 (write) and 0xD3 (read), or 0b1101001 + R/W. Table 9. I2C Addresses for MAX30009 followed by a STOP condition.

Figure 27. I2C Multibyte Read Transaction I2C_BCAST_EN[0[(0x14) must be set to 1.

1. Synchronizing PLLs on multiple devices using the TIMING_SYS_RESET7 bit; thereby, avoiding any external
2. Programming the same configuration to multiple devices at the same time.

address, the device responds with a NACK.

0x00 Status 1[7:0] A_FULL – FIFO_D ATA_RD Y FREQ_U NLOCK FREQ_L OCK PHASE_ UNLOCK PHASE_ LOCK PWR_R DY 0x01 Status 2[7:0] LON BIOZ_O VER BIOZ_U NDR DRV_O OR DC_LOF F_PH DC_LOF F_PL DC_LOF F_NH DC_LOF F_NL FIFO 0x08 FIFO Write Pointer[7:0] FIFO_WR_PTR[7:0] 0x09 FIFO Read Pointer[7:0] FIFO_RD_PTR[7:0] 0x0A FIFO Counter 1[7:0] FIFO_D ATA_CO UNT[8] OVF_COUNTER[6:0] 0x0B FIFO Counter 2[7:0] FIFO_DATA_COUNT[7:0] 0x0C FIFO Data Register[7:0] FIFO_DATA[7:0] 0x0D FIFO Configuration 1[7:0] FIFO_A_FULL[7:0] 0x0E FIFO Configuration 2[7:0] – – FIFO_M ARK FLUSH_ FIFO FIFO_ST AT_CLR A_FULL _TYPE FIFO_R O – System Control 0x10 System Sync[7:0] TIMING_ SYS_RE SET 0x11 System Configuration 1[7:0] MASTER DISABL 0x12 Pin Functional Configuration[7:0] – – – – INT_FCFG[1:0] – TRIG_IC FG 0x13 Output Pin Configuration[7:0] – – – – INT_OCFG[1:0] TRIG_OCFG[1:0] 0x14 I2C Broadcast Address[7:0] I2C_BCAST_ADDR[6:0] I2C_BCA ST_EN PLL 0x17 PLL Configuration 1[7:0] MDIV[9:8] NDIV KDIV[3:0] PLL_EN 0x18 PLL Configuration 2[7:0] MDIV[7:0] 0x19 PLL Configuration 3[7:0] – – – – – – – PLL_LO CK_WN DW 0x1A PLL Configuration 4[7:0] – REF_CL K_SEL CLK_FR EQ_SEL CLK_FINE_TUNE[4:0] BioZ Setup 0x20 BioZ Configuration 1[7:0] BIOZ_DAC_OSR[1: 0] BIOZ_ADC_OSR[2:0] BIOZ_B G_EN BIOZ_Q _EN BIOZ_I_ EN 0x21 BioZ Configuration 2[7:0] BIOZ_DHPF[1:0] BIOZ_DLPF[2:0] BIOZ_CMP[1:0] EN_BIO Z_THRE SH MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 58

3[7:0] BIOZ_E XT_RES LOFF_R APID BIOZ_VDRV_MAG[1 :0] BIOZ_IDRV_RGE[1: BIOZ_DRV_MODE[ 1:0] 0x23 BioZ Configuration BIOZ_FA ST_MAN UAL BIOZ_FA ST_STA RT_EN 0x24 BioZ Configuration 5[7:0] BIOZ_AHPF[3:0] BIOZ_IN A_MOD E BIOZ_D M_DIS BIOZ_GAIN[1:0] 0x25 BioZ Configuration 6[7:0] BIOZ_E XT_CAP BIOZ_D C_REST ORE BIOZ_D RV_RES ET BIOZ_D AC_RES ET BIOZ_AMP_RGE[1: 0] BIOZ_AMP_BW[1:0] 0x26 BIOZ Low Threshold[7:0] BIOZ_LO_THRESH[7:0] 0x27 BIOZ High Threshold[7:0] BIOZ_HI_THRESH[7:0] 0x28 BioZ Configuration 7[7:0] – – – BIOZ_ST BYON BIOZ_Q _CLK_P HASE BIOZ_I_ CLK_PH ASE BIOZ_IN A_CHOP _EN BIOZ_C H_FSEL BioZ Calibration 0x41 BioZ Mux Configuration 1[7:0] BMUX_RSEL[1:0] BMUX_B IST_EN – – CONNE CT_CAL _ONLY MUX_EN CAL_EN 0x42 BioZ Mux Configuration 2[7:0] BMUX_GSR_RSEL[ 1:0] GSR_LO AD_EN – – – EN_EXT _INLOA D EN_INT_ INLOAD 0x43 BioZ Mux Configuration 3[7:0] BIP_ASSIGN[1:0] BIN_ASSIGN[1:0] DRVP_ASSIGN[1:0] DRVN_ASSIGN[1:0] 0x44 BioZ Mux Configuration 4[7:0] BIST_R_ERR[7:0] DC Leads Setup 0x50 DC Leads Configuration[7:0] EN_LON _DET EN_LOF F_DET EN_EXT _LOFF EN_DRV _OOR LOFF_IP OL LOFF_IMAG[2:0] 0x51 DC Lead Detect Threshold[7:0] – – – – LOFF_THRESH[3:0] Lead Bias 0x58 Lead Bias Configuration 1[7:0] – – – – RBIAS_VALUE[1:0] EN_RBI AS_BIP EN_RBI AS_BIN Interrupt Enables 0x80 Interrupt Enable 1[7:0] A_FULL _EN – FIFO_D ATA_RD Y_EN FREQ_U NLOCK_ EN FREQ_L OCK_EN PHASE_ UNLOCK _EN PHASE_ LOCK_E N 0x81 Interrupt Enable 2[7:0] LON_EN BIOZ_O VER_EN BIOZ_U NDR_EN DRV_O OR_EN DC_LOF F_PH_E N DC_LOF F_PL_E N DC_LOF F_NH_E N DC_LOF F_NL_E N Part ID 0xFF Part ID[7:0] PART_ID[7:0] MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 59

Status 1 (0x00) BIT 7 6 5 4 3 2 1 0 Field A_FULL – FIFO_DATA _RDY FREQ_UNL OCK FREQ_LOC K PHASE_UN LOCK PHASE_LO CK PWR_RDY Reset 0 – 0 0 0b0 0 0 1 Access Type Read Only – Read Only Read Only Read Only Read Only Read Only Read Only A_FULL: FIFO is almost full A_FULL is set to 1 when the FIFO reaches the threshold programmed in the FIFO_A_FULL7:0. This is a read- only bit and is cleared when the Status 1 Register is read. It is also cleared when the FIFO Data Register(0x0C) is read if FIFO_STAT_CLR3 = 1. A_FULL DECODE

0 Normal operation

1 Indicates the FIFO buffer reached the threshold set by FIFO_A_FULL7:0. FIFO_DATA_RDY: New FIFO Data Ready FIFO_DATA_RDY bit is set to 1 when new data is available in the FIFO. This is a read-only bit and is cleared by reading the Status 1 register. It is also cleared by reading the FIFO Data Register(0x0C) if FIFO_STAT_CLR3 = FIFO_DATA_RDY DECODE

1 New data is available in the FIFO

FREQ_UNLOCK: PLL Frequency is unlocked FREQ_UNLOCK is set to 1 when the PLL loses the frequency lock. This is a read-only bit and is cleared by reading the Status 1 register. If the frequency unlock state persists, the FREQ_UNLOCK bit is set again. FREQ_UNLOCK DECODE 0 The PLL is frequency locked. 1 The PLL is frequency unlocked. FREQ_LOCK: PLL Frequency is Locked FREQ_LOCK bit is set to 1 when the PLL frequency gets locked. This is a read-only bit and is cleared by reading the Status 1 register. If the PLL remains locked, the FREQ_LOCK bit continues to be asserted. FREQ_LOCK 0 The PLL is frequency unlocked. 1 The PLL is frequency locked. PHASE_UNLOCK: PLL is unlocked PHASE_UNLOCK is set to 1 when the PLL phase is locked and then loses its phase lock. This is a read-only bit and cleared by reading the Status 1 register. If the PLL remains phase unlocked, the PHASE_UNLOCK bit is set again. This bit can give inconsistent results when using the internal oscillator or a high-jitter external oscillator. If the bits FREQ_LOCK = 1, PHASE_LOCK = 1 and FREQ_UNLOCK = 0 then the PLL is operating correctly. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 60

PHASE_UNLOCK DECODE 0 The PLL is phase locked. 1 The PLL is phase unlocked. PHASE_LOCK: PLL is Locked PHASE_LOCK is set to 1 when the PLL achieves phase lock. This is a read-only bit and cleared by reading the Status 1 register. If the PLL remains in phase lock, the PHASE_LOCK bit is set again. PHASE_LOCK DECODE 0 The PLL is phase unlocked. 1 The PLL is phase locked. PWR_RDY: VDD goes below UVLO Threshold PWR_RDY is set to 1 when VDVDD goes below the Undervoltage Lockout (UVLO) threshold, which is nominally 1.3V. If this condition occurs, all registers are reset to their POR state. This bit is not triggered by a soft-reset. This is a read- only bit and is cleared when Status 1 register is read, or by setting SHDN1 bit to 1. PWR_RDY is a non-maskable interrupt, so it gets asserted on INT. Value Decode 1 Indicates that VDVDD goes below the UVLO threshold. Status 2 (0x01) BIT 7 6 5 4 3 2 1 0 Field LON BIOZ_OVE R BIOZ_UND R DRV_OOR DC_LOFF_ PH DC_LOFF_ PL DC_LOFF_ NH DC_LOFF_ NL Reset 0 0 0 0 0 0 0 0 Access Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only LON: DC Leads On Detected LON is set to 1 when a BioZ lead-on condition is detected. This is a read-only bit and is cleared by reading the Status 2 register. If the BioZ lead-on condition persists, the LON bit is set again. For the LON status bit to work when PLL is not enabled, set REF_CLK_SEL to 0 to enable the on-chip oscillator. LON DECODE 0 BioZ lead-on condition is not detected. 1 BioZ lead-on condition is detected. BIOZ_OVER: BIOZ Over Range BIOZ_OVER is set to 1 when the absolute value of the BioZ ADC reading exceeds the BioZ high threshold set by register BIOZ_HI_THRESH7:0 for more than 128ms if CLK_FREQ_SEL = 0, or 125ms if CLK_FREQ_SEL = 1. This bit is cleared when the Status 2 register is read. If the BIOZ_OVER condition persists at the end of next BioZ sample, the bit is set to 1 again. This status bit is recommended for use in two-electrode and four-electrode BioZ Lead-Off detection. BIOZ_OVER DECODE MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 61

BIOZ_OVER DECODE 1 BIOZ_HI_THRESH is exceeded. BIOZ_UNDR: BIOZ Under Range BIOZ_UNDR is set to 1 when the absolute value of the BioZ ADC reading is below the BIOZ Low Threshold set by register BIOZ_LO_THRESH7:0 for more than 128ms if CLK_FREQ_SEL = 0, or 125ms if CLK_FREQ_SEL = 1. This bit is cleared when the Status 2 register is read. If the BIOZ_UNDR condition persists at the end of the next BioZ sample, the bit is set to 1 again. This status bit is recommended for use in four-electrode BioZ Lead-Off detection. BIOZ_UNDER DECODE 1 BIOZ_LO_THRESH is exceeded. DRV_OOR: BIOZ Current Generator Indicates Leads Off DRV_OOR is set to 1 when the BioZ DRVN voltage peaks are out of range (< 0.2V or > (VAVDD - 0.2V)) for more than 128ms if CLK_FREQ_SEL = 0, or 125ms if CLK_FREQ_SEL = 1. This bit is cleared when the Status 2 register is read. If the BioZ drive out-of-range condition persists, this bit continues to remain asserted. DRV_OOR DECODE 1 DRVN is out of range. DC_LOFF_PH: BIOZP is above High Threshold DC_LOFF_PH is set to 1 when the BIP voltage is greater than VBIOZ_TH_H for more than 128ms if CLK_FREQ_SEL = 0, or 125ms if CLK_FREQ_SEL = 1. VBIOZ_TH_H is set by LOFF_THRESH3:0. This is a read-only bit and it is cleared by reading the Status 2 register. If the lead-off condition for DC_LOFF_PH persists, this bit is set again. DC_LOFF_PH DECODE 1 The BIP voltage is greater than VBIOZ_TH_H. DC_LOFF_PL: BIOZP is below LowThreshold DC_LOFF_PL is set to 1 when the BIP voltage is less than VBIOZ_TH_L for more than 128ms if CLK_FREQ_SEL = 0, or125ms if CLK_FREQ_SEL = 1. VBIOZ_TH_L is set by LOFF_THRESH3:0. This is a read-only bit and it is cleared by reading the Status 2 register. If the lead-off condition for DC_LOFF_PL persists, this bit is set again. DC_LOFF_PL DECODE 1 The BIP voltage is lower than VBIOZ_TH_L. DC_LOFF_NH: BIOZN is above High Threshold DC_LOFF_NH is set to 1 when the BIN voltage is greater than VBIOZ_TH_H for more than 128ms if CLK_FREQ_SEL = 0, or 125ms if CLK_FREQ_SEL = 1. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 62

VBIOZ_TH_H is set by LOFF_THRESH3:0. This is a read-only bit and it is cleared by reading the Status 2 register. If the lead-off condition for DC_LOFF_NH persists, this bit is set again. DC_LOFF_NH DECODE 1 The BIN voltage is higher than VBIOZ_TH_H. DC_LOFF_NL: BIOZN is below Low Threshold DC_LOFF_NL is set to 1 when the BIN voltage is less than VBIOZ_TH_L for more than 128ms if CLK_FREQ_SEL = 0, or 125ms if CLK_FREQ_SEL = 1. VBIOZ_TH_L is set by LOFF_THRESH3:0. This is a read-only bit and it is cleared by reading the Status 2 register. If the lead-off condition for DC_LOFF_NL persists, this bit is set again. DC_LOFF_NL DECODE 1 The BIN voltage is lower than VBIOZ_TH_L. FIFO Write Pointer (0x08) BIT 7 6 5 4 3 2 1 0 Field FIFO_WR_PTR[7:0] Reset 0x00 Access Type Read Only FIFO_WR_PTR: FIFO Write Pointer FIFO_WR_PTR points to the FIFO location where the next sample is written. This pointer advances for each sample pushed on to the circular FIFO. The write pointer wraps around to count 0x00 as the next FIFO location after count 0xFF. FIFO Read Pointer (0x09) BIT 7 6 5 4 3 2 1 0 Field FIFO_RD_PTR[7:0] Reset 0x00 Access Type Write, Read, Dual FIFO_RD_PTR: FIFO Read Pointer FIFO_RD_PTR points to the FIFO location from which the next sample is to be read through the serial interface. This pointer advances each time a sample is read from the circular FIFO. If the PLL is enabled, the read pointer can also be written to. This allows rereading (or retrying) samples from the FIFO. However, writing to FIFO_RD_PTR can have adverse effects if it results in the FIFO being almost full. The read pointer wraps around to count 0x00 after count 0xFF. If the PLL is disabled, writing to FIFO_RD_PTR register is not allowed. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 63

FIFO Counter 1 (0x0A) BIT 7 6 5 4 3 2 1 0 Field FIFO_DATA _COUNT[8] OVF_COUNTER[6:0] Reset 0 0x00 Access Type Read Only Read Only FIFO_DATA_COUNT: FIFO Data Count MSB FIFO_DATA_COUNT8 is a read-only bit that holds the most significant bit of the number of items available in the FIFO for the host to read. The lower 8 bits are in the FIFO_DATA_COUNT7:0 register. FIFO_DATA_COUNT[8:0] increments when a new item is pushed to the FIFO, and decrements when the host reads an item from the FIFO. FIFO_DATA_COUNT[8:0] is useful for debug. OVF_COUNTER: FIFO Overflow Counter The overflow counter OVF_COUNTER logs the number of samples lost if the FIFO is not read in a timely fashion. When the FIFO is full, any new sample results in either new or old sample getting lost depending on the FIFO_RO1 setting. This is a read-only register. When a complete sample is read from FIFO and the read pointer advances, the OVF_COUNTER is reset to zero. It should be read immediately before reading the FIFO to check if an overflow condition occurred. This counter saturates at count value 0x7F. FIFO Counter 2 (0x0B) BIT 7 6 5 4 3 2 1 0 Field FIFO_DATA_COUNT[7:0] Reset 0x00 Access Type Read Only FIFO_DATA_COUNT: FIFO Data Count LSB FIFO_DATA_COUNT[7:0] is a read-only register that holds the lower 8 bits of the number of items available in the FIFO for the host to read. See the FIFO_DATA_COUNT8 description for details. FIFO Data Register (0x0C) BIT 7 6 5 4 3 2 1 0 Field FIFO_DATA[7:0] Reset 0xFF Access Type Read Only FIFO_DATA: FIFO Data Register FIFO_DATA is used to get data from the FIFO using burst reads only. When burst reading from this register, the register address pointer does not auto-increment, and the FIFO_RD_PTR7:0 advances to provide subsequent samples. Each sample is three bytes. So, burst reading three bytes in the FIFO_DATA register through the serial MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 64

interface advances the FIFO_RD_PTR by one count. The format and data type of the data stored in the FIFO is determined by the tag associated with the data. For details and examples of various data types in some use cases, see the FIFO Description section. This is a read-only register. FIFO Configuration 1 (0x0D) BIT 7 6 5 4 3 2 1 0 Field FIFO_A_FULL[7:0] Reset 0x7F Access Type Write, Read FIFO_A_FULL: FIFO Almost Full Threshold FIFO_A_FULL sets the high-water mark for the FIFO and determines when status bit A_FULL7 is asserted. The A_FULL bit is asserted when the FIFO holds (256 - FIFO_A_FULL) samples. For example, if set to 0x0F, A_FULL is asserted when there are 15 empty spaces left (241 samples in FIFO). If A_FULL_EN7, then A_FULL being asserted results in an interrupt on the INT pin. This condition should prompt the processor to read samples from the FIFO before it fills and overflows. The A_FULL bit is cleared and the interrupt is deasserted when the Status 1 register (0x00) is read. FIFO_A_FULL Free Spaces Before Interrupt is Asserted Number of Samples in FIFO 0x00 0 256 0x01 1 255 0x02 2 254 0x03 3 253 ---- ---- ---- 0xFE 254 2 0xFF 255 1 FIFO Configuration 2 (0x0E) BIT 7 6 5 4 3 2 1 0 Field – – FIFO_MAR K FLUSH_FIF O FIFO_STAT _CLR A_FULL_TY PE FIFO_RO – Reset – – 0 0 1 0 1 – Access Type – – Write, Read Write, Read Write, Read Write, Read Write, Read – FIFO_MARK: Push Marker to FIFO When the FIFO_MARK is set to 1, a marker tag is pushed to the FIFO. FIFO_MARK is a self-clearing bit. The marker tag is useful for differentiating the data in the FIFO before and after the tag. See the FIFO Description section for the marker tag information. FLUSH_FIFO: Manual FIFO Flush When the FLUSH_FIFO bit is set to 1, the FIFO is flushed, and FIFO_WR_PTR7:0, FIFO_RD_PTR7:0, FIFO_DATA_COUNT[8:0](0x0A, 0x0B), and OVF_COUNTER6:0 are reset to zero. The contents of the FIFO are lost. FLUSH_FIFO is a self-clearing bit. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 65

FIFO_STAT_CLR: FIFO Status and Interrupt Clear Type FIFO_STAT_CLR determines if a FIFO_DATA7:0 register read clears the status bits A_FULL7 and FIFO_DATA_RDY5, and their corresponding interrupts. FIFO_STAT_CLR DECODE

0 A_FULL and FIFO_DATA_RDY status and interrupts do not get cleared by a FIFO_DATA7:0 register

read. They get cleared by a Status 1 register read.

1 A_FULL and FIFO_DATA_RDY status and interrupts get cleared by a FIFO_DATA7:0 register read or

a Status 1 register read. A_FULL_TYPE: A_FULL Interrupt Type A_FULL_TYPE defines the behavior of status bit A_FULL7 and its corresponding interrupt. When A_FULL_TYPE is set to 0, A_FULL is asserted every time the FIFO almost-full condition is detected. When A_FULL_TYPE is set to 1, A_FULL is asserted only for any new almost-full condition. A_FULL_TYPE DECODE 0 A_FULL interrupt gets asserted when the almost full condition is detected. It is cleared by a Status 1 register read, but reasserts for every sample if the almost-full condition persists. 1 A_FULL interrupt gets asserted when the almost-full condition is detected. The interrupt gets cleared by a Status 1 register read, and does not reassert until the FIFO is read and then a new almost-full condition is detected. FIFO_RO: FIFO Push enable when full FIFO_RO controls the behavior of the FIFO when the FIFO becomes completely filled with data. Push to FIFO is enabled when FIFO is full if FIFO_RO is set to 1 and old samples are lost. Both FIFO Write Pointer (0x08) and FIFO Read Pointer (0x09) increment for each sample after the FIFO is full. If FIFO_RO is set to 0, new samples are lost and the FIFO is not updated. FIFO Write Pointer and FIFO Read Pointer do not increment until a sample is read from the FIFO. FIFO_RO DECODE 0 The FIFO stops on full. 1 The FIFO automatically rolls over on full. System Sync (0x10) BIT 7 6 5 4 3 2 1 0 Field TIMING_SY Access TIMING_SYS_RESET: Generate Timing Reset Signal TIMING_SYS_RESET bit works together with the MASTER bit to synchronize the timing sub systems of multiple AFEs. Writing a one to the TIMING_SYS_RESET bits resets the NDIV divider. This should only be done when BIOZ_BG_EN2, BIOZ_I_EN0 and BIOZ_Q_EN1 are set to 0. TIMING_SYS_RESET is ignored when BIOZ_BG_EN, BIOZ_I_EN or BIOZ_Q_EN are set to 1. If MASTER = 1, then a sync pulse also appears on the TRIG pin. If MASTER = 0, writing 1 to the TIMING_SYS_RESET bit has no effect, but any sync pulse on the TRIG pin resets the NDIV divider. TIMING_SYS_RESET is a self-clearing bit. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 66

0x1 Controller Target Mode System Configuration 1 (0x11) BIT 7 6 5 4 3 2 1 0 Field MASTER DISABLE_I 2C – – – – SHDN RESET Reset 0b0 0 – – – – 0 0 Access Type Write, Read Write, Read – – – – Write, Read Write, Read MASTER: Master for Timing System Reset The MASTER bit works together with the TIMING_SYS_RESET bit to synchronize the timing sub systems of mulitple AFEs. When set to 1b'1, this bit causes this device to behave as a controller. If MASTER is set to 1'b0, the device is a target for timing subsystem synchronization. See TIMING_SYS_RESET for more information. Value Enumeration Decode 0x0 Target Mode. TRIG pin configured as input by TRIG_ICFG 0x1 Controller Mode. TRIG configured as ouput by TRIG_OCFG<1:0> DISABLE_I2C: Disable I2C When DISABLE_I2C is set to 0 (default), the part uses the I2C interface or SPI depending on the state of the CSB/ I2C_SEL pin. When DISABLE_I2C is set to 1, the part uses the SPI. For SPI, set this DISABLE_I2C to 1 during initialization after power-up. See the Digital Interface section for more information. DISABLE_I2C DECODE

0 CSB/I2C_SEL pin selects interface

1 Part uses SPI interface only

SHDN: Shutdown Control Setting SHDN to 1 puts the MAX30009 into shutdown mode. While in shutdown mode, all configuration registers retain their values and write/read operations function normally. All interrupts are cleared to zero in this mode. Also, in this mode, the oscillator is shut down and the part draws minimum current. If this bit is asserted during an active conversion, then the conversion is aborted. Set SHDN to 0 to put the part back in normal mode. See the Shutdown Sequence section for more details. SHDN DECODE

0 Normal mode

1 Shutdown mode

RESET: Soft Reset The RESET bit is used to force a power-on-reset sequence. The sequence in Soft-Reset Sequence must be followed when asserting this bit, or registers may become unresponsive until a power-on reset is performed. This is a self- clearing bit and resets to 0 after the reset sequence is completed. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 67

0 NORMAL The part is in normal operation. No action is taken.

1 RESET

The MAX30009 undergoes a forced power-on-reset sequence. All configuration, threshold, and data registers are reset to their power-on-state. This bit then automatically becomes ‘0’ after the reset sequence is completed. Pin Functional Configuration (0x12) BIT 7 6 5 4 3 2 1 0 Field – – – – INT_FCFG[1:0] – TRIG_ICFG Access Type – – – – Write, Read – Write, Read INT_FCFG: Functional Configuration on INT Pin INT_FCFG controls the function and behavior of the INT pin. INT_FCFG DECODE 0x0 Disabled 0x1 INT is enabled and is cleared upon reading of any status register or FIFO. 0x2 INT is enabled and is self-clearing after 30µs to 60µs (depending on PLL_CLK). 0x3 INT is enabled and is self-clearing after 240µs to 480µs (depending on PLL_CLK). TRIG_ICFG: TRIG Input Pin Configuration TRIG_ICFG bit sets the input active edge of the TRIG pin. TRIG_ICFG DECODE 0 The TRIG pin active edge is falling. 1 The TRIG pin active edge is rising. Output Pin Configuration (0x13) BIT 7 6 5 4 3 2 1 0 Field – – – – INT_OCFG[1:0] TRIG_OCFG[1:0] Reset – – – – 0x0 0x0 Access Type – – – – Write, Read Write, Read INT_OCFG: Output Pin Configuration for INT INT_OCFG[1:0] selects the output drive type for the INT pin. INT_OCFG INT OUTPUT DRIVE TYPE 0x0 Open-drain, active-low output. 0x1 Active drive to DVDD and DGND; the active level is a high output. 0x2 Active drive to DVDD and DGND; the active level is a low output. 0x3 Do not use. TRIG_OCFG: Output Pin Configuration for TRIG TRIG_OCFG selects the output drive type for the TRIG pin. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 68

TRIG_OCFG TRIG OUTPUT DRIVE TYPE 0x0 Open-drain, active-low output. 0x1 Active drive to DVDD and DGND; the active level is a high output. 0x2 Active drive to DVDD and DGND; the active level is a low output. 0x3 Do not use. I2C Broadcast Address (0x14) BIT 7 6 5 4 3 2 1 0 Field I2C_BCAST_ADDR[6:0] I2C_BCAST _EN Reset 0x00 0 Access Type Write, Read Write, Read I2C_BCAST_ADDR: Broadcast Address for I2C Write I2C_BCAST_ADDR is used to define the upper 7 bits of the I2C address in I2C broadcast mode (I2C_BCAST_EN = 1) when writing to multiple devices simultaneously using the I2C serial interface. I2C_BCAST_ADDR is ignored in SPI mode. See the I2C Broadcast section for more details. I2C_BCAST_EN: Enable Broadcast Address I2C_BCAST_EN enables write transactions to multiple devices using the broadcast address programmed in I2C_BCAST_ADDR in I2C mode. I2C read transactions are not supported when I2C_BCAST_ADDR is used. Note that for devices using SPI, broadcast write transactions can be achieved by driving the CSB pins low on multiple devices at the same time. I2C_BCAST_EN DECODE 0 Normal mode. I2C transactions are for one device only. 1 I2C broadcast mode. Write transactions to multiple devices are enabled. PLL Configuration 1 (0x17) BIT 7 6 5 4 3 2 1 0 Field MDIV[9:8] NDIV KDIV[3:0] PLL_EN Reset 0x1 0 0x0 0 Access Type Write, Read, Dual Write, Read Write, Read Write, Read MDIV: MS bits of MDIV[9:0] MDIV[9:0] multiplies the REF_CLK by MDIV + 1 to set the frequency of the PLL. MDIV[9:8] are the 2 MSBs of MDIV[9:0]. The lower 8 bits are in MDIV7:0. MDIV must be set such that PLL_CLK is between 14.0MHz and 28.0MHz. For information on how to set MDIV[9:0], see the Timing Subsystem section. NDIV: N-divider for BIOZ ADC Clock NDIV divides down the PLL clock as shown in the following table and sets the clock for the BioZ ADC. For information on how to set BIOZ_NDIV, see the Timing Subsystem section. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 69

KDIV: K-divider for Synthesis Frequency KDIV divides down the PLL clock as shown in the following table and sets the clock for the DDS DAC. For information on how to set KDIV, see the Timing Subsystem section. KDIV BIOZ K DIVIDER 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 0x5 32 0x6 64 0x7 128 0x8 256 0x9 512 0xA 1024 0xB 2048 0xC 4096 0xD 8192 0xE 8192 0xF 8192 PLL_EN: Enable PLL PLL_EN enables the internal PLL, which multiplies the reference clock to a frequency between 14MHz and 28MHz. For details on the PLL, see the Timing Subsystem section. PLL_EN must be set to 1 before enabling BioZ measurements. PLL_EN DECODE

0 PLL is disabled

1 PLL is enabled

PLL Configuration 2 (0x18) BIT 7 6 5 4 3 2 1 0 Field MDIV[7:0] Reset 0xBB Access Type Write, Read, Dual MDIV: Lower Byte of MDIV[9:0] MDIV[7:0] are the 8 LSBs of MDIV[9:0]. See MDIV9:8 register for details. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 70

PLL Configuration 3 (0x19) BIT 7 6 5 4 3 2 1 0 _WNDW Access PLL_LOCK_WNDW: PLL_LOCK_WNDW PLL_LOCK_WNDW selects the time window for the PLL phase lock detector. The PLL lock detector compares the rising edges of FCLK and the output of the M divider, and determines the PLL to be locked if the difference between the two is less than PLL_LOCK_WNDW. Setting PLL_LOCK_WNDW = 1 helps to avoid false PHASE_UNLOCK interrupts when the FCLK reference has high jitter. PLL_LOCK_WNDW PLL PHASE LOCK WINDOW 0 1 PLL clock period 1 2 PLL clock periods (recommended when using high-jitter FCLK input) PLL Configuration 4 (0x1A) BIT 7 6 5 4 3 2 1 0 Field – REF_CLK_ SEL CLK_FREQ _SEL CLK_FINE_TUNE[4:0] Reset – 0 0 0x00 Access Type – Write, Read Write, Read Write, Read REF_CLK_SEL: Reference Clock Select for PLL REF_CLK_SEL DECODE 0 Internal 32.0kHz or 32.768kHz oscillator used for REF_CLK

1 External oscillator used for REF_CLK

CLK_FREQ_SEL: Frequency select for PLL Reference Clock CLK_FREQ_SEL selects the PLL reference-clock frequency. When using the internal oscillator (REF_CLK_SEL = 0), this bit sets the frequency of the internal oscillator. When using an external clock on the FCLK pin (REF_CLK_SEL = 1), this bit must match the frequency of the external clock. This bit sets the internal timing durations according to the clock frequency. CLK_FREQ_SEL DECODE 0 PLL reference clock is 32.0kHz 1 PLL reference clock is 32.768kHz CLK_FINE_TUNE: Fine Tune PLL Reference Clock CLK_FINE_TUNE is used to fine-tune the internal slow oscillator. This is accomplished by measuring the time between interrupts using a microcontroller, crystal-based real-time oscillator as a reference, and computing the error in the time between interrupts. CLK_FINE_TUNE is a 2's complement code with a resolution of 0.2% per LSB. The total range is +3.0% to -3.2% around the factory trimmed value. CLK_FINE_TUNE SHIFT IN FREQUENCY (%) CLK_FINE_TUNE SHIFT IN FREQUENCY(%) 0x00 0.0 0x10 -3.2 MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 71

CLK_FINE_TUNE SHIFT IN FREQUENCY (%) CLK_FINE_TUNE SHIFT IN FREQUENCY(%) 0x01 0.2 0x11 -3.0 0x02 0.4 0x12 -2.8 0x03 0.6 0x13 -2.6 0x04 0.8 0x14 -2.4 0x05 1.0 0x15 -2.2 0x06 1.2 0x16 -2.0 0x07 1.4 0x17 -1.8 0x08 1.6 0x18 -1.6 0x09 1.8 0x19 -1.4 0x0A 2.0 0x1A -1.2 0x0B 2.2 0x1B -1.0 0x0C 2.4 0x1C -0.8 0x0D 2.6 0x1D -0.6 0x0E 2.8 0x1E -0.4 0x0F 3.0 0x1F -0.2 BioZ Configuration 1 (0x20) BIT 7 6 5 4 3 2 1 0 Field BIOZ_DAC_OSR[1:0] BIOZ_ADC_OSR[2:0] BIOZ_BG_ EN BIOZ_Q_E N BIOZ_I_EN Reset 0x0 0x0 0 0 0 Access Type Write, Read Write, Read Write, Read Write, Read Write, Read BIOZ_DAC_OSR: BioZ DAC Over Sampling Ratio BIOZ_DAC_OSR[1:0] sets the over sample ratio of the BioZ DDS DAC. For information on how to set BIOZ_DAC_OSR[1:0], see Timing Subsystem. BIOZ_DAC_OSR DAC OVER SAMPLING RATIO 0x0 32 0x1 64 0x2 128 0x3 256 BIOZ_ADC_OSR: BioZ ADC Over Sampling Ratio BIOZ_ADC_OSR[2:0] sets the over sample ratio of the BioZ I and Q ADCs. For information on how to set BIOZ_ADC_OSR[2:0], see Timing Subsystem. BIOZ_ADC_OSR ADC OVER SAMPLING RATIO 0x0 8 0x1 16 0x2 32 0x3 64 0x4 128 0x5 256 MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 72

BIOZ_ADC_OSR ADC OVER SAMPLING RATIO 0x6 512 0x7 1024 BIOZ_BG_EN: BIOZ_BG_EN BIOZ_BG_EN enables the BioZ bandgap bias required for all functions except the ULP LON. The bias power-up time is approximately 200ms and should be kept on between subsequent measurements. BIOZ_BG_EN DECODE

0 BioZ bandgap bias disabled

1 BioZ bandgap bias enabled

BIOZ_Q_EN: Enable BIOZ ADC Conversions for Quadrature-phase component BIOZ_Q_EN enables the bioimpedance drive and receive channels for the quadrature-phase (Q) component when set to 1. When set to 0, the Q receive channel is disabled. BIOZ_Q_EN will also enable PLL and BG. It is recommended to set PLL_ENABLE and BG_ENABLE = 1 before setting BIOZ_Q_EN. BIOZ_I_EN: Enable BIOZ ADC Conversions for In-phase component BIOZ_I_EN enables the bioimpedance drive and receive channels for the in-phase (I) component when set to 1. When set to 0, the I receive channel is disabled. BIOZ_I_EN will also enable PLL and BG. It is recommended to set PLL_ENABLE and BG_ENABLE = 1 before setting BIOZ_I_EN. BioZ Configuration 2 (0x21) BIT 7 6 5 4 3 2 1 0 Field BIOZ_DHPF[1:0] BIOZ_DLPF[2:0] BIOZ_CMP[1:0] EN_BIOZ_T HRESH Reset 0x0 0x0 0x0 0 Access Type Write, Read Write, Read Write, Read Write, Read BIOZ_DHPF: Enable Digital High Pass Filter BIOZ_DHPF sets the BioZ channel digital high-pass filter cutoff frequency. BIOZ_DHPF[1:0] CUTOFF FREQUENCY (Hz) 0x0 Bypass 0x1 0.00025 x SR_BIOZ 0x2 0.002 x SR_BIOZ 0x3 0.002 x SR_BIOZ BIOZ_DLPF: Enable Digital Low Pass Filter BIOZ_DLPF sets the BioZ channel digital low-pass filter cutoff frequency. BIOZ_DLPF[2:0] CUTOFF FREQUENCY (Hz) 0x0 Bypass 0x1 0.005 x SR_BIOZ 0x2 0.02 x SR_BIOZ 0x3 0.08 x SR_BIOZ 0x4 to 0x7 0.25 x SR_BIOZ MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 73

BIOZ_CMP: BIOZ Data Select for Threshold Compare BIOZ_CMP selects which component of the BioZ measurement is used to compare with the thresholds programmed at BIOZ_HI_THRESH7:0 and BIOZ_LO_THRESH7:0. If only one of I and Q channels is enabled, the disabled channel data is zero, and the magnitude of Z is same as the magnitude of the enabled channel data. BIOZ_CMP[1:0] COMPONENT 0x0 Magnitude of In-phase component, I only 0x2 Magnitude of Quadrature-phase component, Q only 0x2 Magnitude of Z, where Z = SQRT(I2 + Q2) 0x3 Reserved. Do not use EN_BIOZ_THRESH: Enable AC Leads Off Detect When EN_BIOZ_THRESH bit is set to 1, the BioZ data I, Q, or Z (see BIOZ_CMP2:1) is compared with the thresholds programmed in the BIOZ_HI_THRESH7:0 and BIOZ_LO_THRESH7:0 registers. The BioZ high threshold can be used for AC lead-off detection in two-electrode systems, and the BioZ low threshold can be used for AC lead-off detection in four-electrode systems. The status is reflected in BIOZ_OVER6 and BIOZ_UNDR5. When EN_BIOZ_THRESH is set to 0, threshold detection is disabled. BioZ Configuration 3 (0x22) BIT 7 6 5 4 3 2 1 0 Field BIOZ_EXT_ RES LOFF_RAPI D BIOZ_VDRV_MAG[1:0] BIOZ_IDRV_RGE[1:0] BIOZ_DRV_MODE[1:0] Reset 0 0 0x0 0x0 0x0 Access Type Write, Read Write, Read Write, Read, Dual Write, Read, Dual Write, Read BIOZ_EXT_RES: External Resistor Select BIOZ_EXT_RES selects the external REXT resistor or the internal range settings resistors. When BIOZ_EXT_RES is set to 0, the internal range resistors are used and the current magnitude is set by both BIOZ_VDRV_MAG5:4 and BIOZ_IDRV_RGE3:2. BIOZ_VDRV_MAG and BIOZ_IDRV_RGE can be automatically overwritten depending on the stimulus frequency according to patient safety requirements. Note that REXT is not disconnected, so the DRVXR pin should be unconnected. If DRVXR is connected, REXT is connected in parallel with the internal range resistor, which results in a larger current magnitude. When BIOZ_EXT_RES is set to 1, BIOZ_VDRV_MAG and the value of REXT set the current magnitude. BIOZ_VDRV_MAG is not automatically overwritten. Value Enumeration Decode 0x0 Normal, no ext-res 0x1 Use external res LOFF_RAPID: Disable Timers for Leads Off Detection LOFF_RAPID bypasses the approximately 128ms window delay for DC lead-off detection. The delay is beneficial in most cases to ignore unintended voltage spikes caused by line noise or electrode movement. LOFF_RAPID DECODE

0 A lead off condition must be sustained for approximately 128ms to trigger a DC

lead-off status. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 74

LOFF_RAPID DECODE 1 A lead-off condition immediately triggers a DC lead off status. BIOZ_VDRV_MAG: BIOZ VDrive Magnitude In voltage drive mode, BIOZ_VDRV_MAG sets the voltage amplitude at DRVR, which is connected to EL1. BIOZ_IDRV_RGE is ignored. In current drive mode, BIOZ_VDRV_MAG and BIOZ_IDRV_RGE set the current magnitude. See BIOZ_IDRV_RGE for details. BIOZ_VDRV_MAG[1:0] VOLTAGE MAGNITUDE (mVPK) VOLTAGE MAGNITUDE (mVRMS) 0x0 50 35.4 0x1 100 70.7 0x2 250 177 0x3 500 354 BIOZ_IDRV_RGE: BIOZ Current Drive Range Select BIOZ_IDRV_RGE[1:0] sets the value of the internal current-range resistor, which determines the current magnitude when BIOZ_EXT_RES = 0. BIOZ_IDRV_RGE[1:0] INTERNAL RANGE RESISTOR VALUE 0x0 552.5kΩ (VDRV resistor reduced by 4x) 0x1 110.5kΩ 0x2 5.525kΩ 0x3 276.25Ω When BIOZ_EXT_RES = 1, the external resistor connected between DRVXR and DRVXC determines the drive current amplitude: Drive Current (APK) = DRVR (VPK) / REXT. BIOZ_VDRV_MAG and BIOZ_IDRV_RGE together select the magnitude of the stimulus current. When BIOZ_IDRV_RGE = 0x0, the drive voltage at DRVR is reduced by a factor of four to support smaller current magnitudes. BIOZ_IDRV_RGE[1:0] BIOZ_VDRV_MAG[1:0] AMPLITUDE OF VDRVR (mVPK) AMPLITUDE OF VDRVR (mVRMS) AMPLITUDE OF CURRENT (PEAK) AMPLITUDE OF CURRENT (RMS) 0x0 0x0 12.5 8.8 23nA 16nA 0x0 0x1 25 17.7 45nA 32nA 0x0 0x2 62.5 44.2 113nA 80nA 0x0 0x3 125 88.4 226nA 160nA 0x1 0x0 50 35.4 452nA 320nA 0x1 0x1 100 70.7 905nA 640nA 0x1 0x2 250 177 2.262μA 1.6μA 0x1 0x3 500 354 4.525μA 3.2μA 0x2 0x0 50 35.4 9.05μA 6.4μA 0x2 0x1 100 70.7 18.10μA 12.8μA 0x2 0x2 250 177 45.25μA 32μA 0x2 0x3 500 354 90.50μA 64μA 0x3 0x0 50 35.4 181μA 128μA MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 75

BIOZ_IDRV_RGE[1:0] BIOZ_VDRV_MAG[1:0] AMPLITUDE OF VDRVR (mVPK) AMPLITUDE OF VDRVR (mVRMS) AMPLITUDE OF CURRENT (PEAK) AMPLITUDE OF CURRENT (RMS) 0x3 0x1 100 70.7 362μA 256μA 0x3 0x2 250 177 905μA 640μA 0x3 0x3 500 354 1.81mA 1.28mA BIOZ_DRV_MODE: Select Drive Type for BIOZ BIOZ_DRV_MODE selects the stimulus type of the BioZ transmit channel. BIOZ_DRV_MODE[1:0] DRIVE TYPE 0x0 Current Drive. A sine-wave current is driven into the body through selectable electrode pins. 0x1 Voltage Drive. A sine-wave voltage is applied to EL1 while EL4 is driven to VMID_TX. 0x2 H-Bridge Drive. EL1 and EL4 are alternately switched between AVDD and AGND. 0x3 Standby. The transmit channel is reset and held in a low-power state, driving the electrodes to VMID_TX. BioZ Configuration 4 (0x23) BIT 7 6 5 4 3 2 1 0 _MANUAL BIOZ_FAST _START_E N Access Type – – – – – – Write, Read Write, Read BIOZ_FAST_MANUAL: Enable Manual BIOZ Fast Start Together with BIOZ_FAST_START_EN, BIOZ_FAST_MANUAL is used to turn on the fast-start mode manually. The fast-start mode is kept until the register BIOZ_FAST_MANUAL is set back to 0. See BIOZ_FAST_START_EN. BIOZ_FAST_START_EN: Enable BIOZ Fast Start BIOZ_FAST_START_EN enables the fast-start mode, which connects the BIP and BIN inputs to VMID_RX through 10kΩ resistors after enabling the I or Q channel. This quickly establishes a DC bias on the input electrodes. Normally, the fast-start mode is turned on at the very beginning when BioZ is enabled. The turn-on time is about ~200ms, which is automatically set. However, the fast mode can also be kept manually by programming the value of register BIOZ_FAST_MANUAL. Three cases are listed as follows: 1. When BIOZ_FAST_START_EN is set to 0, fast-start is disabled. 2. When BIOZ_FAST_START_EN is set to 1 and BIOZ_FAST_MANUAL is set to 0, fast-start is enabled automatically for 200ms at the very beginning when BIOZ_E_EN or BIOZ_Q_EN are enabled. 3. When BIOZ_FAST_START_EN is set to 1 and BIOZ_FAST_MANUAL is set to 1, fast-start is kept enabled until BIOZ_FAST_MANUAL is set to 0. BIOZ_FAST_START_EN BIOZ_FAST_MANUAL DECODE 0 x Fast start is disabled 1 0 Fast start is enabled for approximately 200ms after BioZ is enabled. 1 1 Fast start is enabled until BIOZ_FAST_MANUAL is set to 0. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 76

BioZ Configuration 5 (0x24) BIT 7 6 5 4 3 2 1 0 Field BIOZ_AHPF[3:0] BIOZ_INA_ MODE BIOZ_DM_ DIS BIOZ_GAIN[1:0] Reset 0x0 0 0 0x0 Access Type Write, Read Write, Read Write, Read Write, Read BIOZ_AHPF: Enable Analog High Pass Filter BIOZ_AHPF sets the corner frequency of the internal analog high-pass filter, or sets the filter resistance when using external capacitors on BIP and BIN. The resistance is center tapped with the midpoint connected to VMID_RX. When using external capacitors, the analog HPF corner frequency is set by the series capacitance and the selected common- mode resistance according to the following equation:

• f-3dB = 1/(2 x π x RAHPF x CSERIES) where CSERIES is the series combination of the external capacitors on BIP and BIN:
• CSERIES = (CBIP x CBIN) / (CBIP + CBIN) BIOZ_AHPF[3:0] DECODE 0x0 100Hz 0x1 200Hz 0x2 500Hz 0x3 1,000Hz 0x4 2,000Hz 0x5 5,000Hz 0x6 10,000Hz 0x7 Resistor opened, internal capacitors shorted (AHPF bypassed) 0x8 42.4MΩ, internal capacitors shorted 0x9 21.2MΩ, internal capacitors shorted 0xA 8.4MΩ, internal capacitors shorted 0xB 4.2MΩ, internal capacitors shorted 0xC 2.2MΩ, internal capacitors shorted 0xD 848kΩ, internal capacitors shorted 0xE 848kΩ, internal capacitors shorted 0xF Resistor opened, internal capacitor shorted (AHPF bypassed) BIOZ_INA_MODE: BIOZ Instrumentation Amplifier Mode Select BIOZ_INA_MODE sets BioZ receive channel's Instrumentation Amplifier (INA) power mode. BIOZ_INA_MODE DECODE

0 BioZ INA is in high power mode (low noise mode)

1 BioZ INA is in low power mode

BIOZ_DM_DIS: BIOZ PGA Demodulation Disable BIOZ_DM_DIS disables the BioZ receive channel demodulators to allow a direct conversion of the differential input voltage across BIP and BIN. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 77

BIOZ_DM_DIS DECODE

0 BioZ demodulation clock enabled

1 BioZ demodulation clock disabled

BIOZ_GAIN: BIOZ Gain Select BIOZ_GAIN sets the combined gain of the BioZ receive channel's INA and PGAs. BIOZ_GAIN[1:0] TOTAL GAIN (V/V) INA GAIN (V/V) PGA GAIN (V/V) 0x0 1 1 1 0x1 2 2 1 0x2 5 2 2.5 0x3 10 2 5 BioZ Configuration 6 (0x25) BIT 7 6 5 4 3 2 1 0 Field BIOZ_EXT_ CAP BIOZ_DC_ RESTORE BIOZ_DRV _RESET BIOZ_DAC _RESET BIOZ_AMP_RGE[1:0] BIOZ_AMP_BW[1:0] Reset 1 0 0 0 0x0 0x0 Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read BIOZ_EXT_CAP: External Capcitor Select BIOZ_EXT_CAP selects the external capacitor CEXT connected between DRVXC and DRVSJ, which AC-couples the stimulus current in the current mode, thus preventing DC current from passing into the patient stimulus electrodes. When not using an external capacitor, short DRVXC and DRVSJ. BIOZ_EXT_CAP DECODE 0 No external capacitor used. The internal switch shorts the DRVXC and DRVSJ pins together with a drain to source resistance of approximately 100Ω. 1 External capacitor used. The internal switch is open, and AC current is coupled through the external capacitor. BIOZ_DC_RESTORE: DC Restore for BIOZ Drive Amp BIOZ_DC_RESTORE closes the DC_RESTORE switch in the current-generator amplifier circuit, which applies a feedback resistance of approximately 10MΩ to the current-drive amplifier. This maintains the DC bias of the drive electrodes during a lead-off event, which reduces the amplifier setting time when the lead is reconnected. When using external AC-coupling capacitors on the pins assigned to DRVP or DRVN, set DC_RESTORE to 1 to absorb any DC offset currents and prevent amplifier saturation. BIOZ_DC_RESTORE DECODE 0 DC_RESTORE switch is open. No feedback resistance is applied to the current drive amplifier. 1 DC_RESTORE switch is closed. A 10MΩ feedback resistance is applied to the current-drive amplifier. BIOZ_DRV_RESET: RESET BIOZ Drive Amp BIOZ_DRV_RESET places the BioZ transmit channel in a reset state by disabling the DDS DAC and closing the RESET switch of the current-drive amplifier. This shorts the feedback network of the amplifier, configuring it as a unity gain buffer and driving both drive electrodes to VMID_TX. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 78

BIOZ_DRV_RESET DECODE 0 Normal Operation. The RESET switch is open. 1 Reset Condition. The DDC DAC is disabled and the RESET switch is closed, shorting the current drive amplifier feedback. BIOZ_DAC_RESET: RESET BIOZ DDS DAC BIOZ_DAC_RESET forces the DDS DAC output to zero. The human body load is driven by the reference voltage VMID_TX, and the AC current going through the human body load is zero. BIOZ_AMP_RGE: AMP Drive Strength Select BIOZ_AMP_RGE selects the output stage option for the voltage-drive amplifier and current-drive amplifier within the BioZ transmit channel. Higher strength is recommended for higher output current loading. Higher settings increase supply-current consumption. Match these settings with the BIOZ_IDRV_RGE setting. BIOZ_AMP_RGE[1:0] BIOZ AMPLIFIER RANGE 0x0 Low 0x1 Medium-Low 0x2 Medium-High 0x3 High BIOZ_AMP_BW: BIOZ AMP Bandwidth Select BIOZ_DRV_BW sets the gain bandwidth of the voltage-drive amplifier and current-drive amplifier within the BioZ transmit channel. Higher bandwidth is recommended for high-frequency applications including Bioimpedance Analysis and Impedance Cardiography. Low bandwidth is recommended for low-frequency applications including Galvanic Skin Response to reduce power consumption. BIOZ_AMP_BW[1:0] BIOZ AMPLIFIER BANDWIDTH 0x0 Low 0x1 Medium-Low 0x2 Medium-High 0x3 High BIOZ Low Threshold (0x26) BIT 7 6 5 4 3 2 1 0 Field BIOZ_LO_THRESH[7:0] Reset 0x00 Access Type Write, Read BIOZ_LO_THRESH: BIOZ Low Threshold BIOZ_LO_THRESH sets the BioZ under-range threshold. If the BioZ measurement selected by BIOZ_CMP is within the symmetric thresholds defined by ±32 x BIOZ_LO_THRESH for longer than approximately 128ms, the BIOZ_UNDR status bit is asserted. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 79

BIOZ High Threshold (0x27) BIT 7 6 5 4 3 2 1 0 Field BIOZ_HI_THRESH[7:0] Reset 0xFF Access Type Write, Read BIOZ_HI_THRESH: BIOZ High Threshold BIOZ_HI_THRESH sets the BioZ over-range threshold. If the BioZ measurement selected by BIOZ_CMP is outside of the symmetric thresholds defined by ±2048 x BIOZ_HI_THRESH for longer than approximately 128ms, the BIOZ_OVER status bit is asserted. The default value (BIOZ_HI_THRESH= 0xFF) corresponds to a BioZ output upper threshold of 0x7F800, or about 99.6% of the full-scale range. BioZ Configuration 7 (0x28) BIT 7 6 5 4 3 2 1 0 Field – – – BIOZ_STBY ON BIOZ_Q_CL K_PHASE BIOZ_I_CL K_PHASE BIOZ_INA_ CHOP_EN BIOZ_CH_F SEL Reset – – – 0 0 0 0 0 Access Type – – – Write, Read Write, Read Write, Read Write, Read Write, Read BIOZ_STBYON: BIOZ STANDBY ON BIOZ_STBYON selects the BioZ receive channel's behavior when the transmit channel is in standby mode (BIOZ_DRV_MODE = 0x3). When in standby mode, the transmit channel does not generate a stimulus. So, the receive channel can be powered down in most cases. BIOZ_STBYON RECEIVE CHANNEL BEHAVIOR IN STANDBY MODE 0 Disabled. The receive channel's amplifiers, demodulators, and ADCs are disabled. 1 Enabled. The BioZ receive channel's amplifiers, demodulators, and ADCs remain enabled. BIOZ_Q_CLK_PHASE: BIOZ Q Clock Phase Control Bit BIOZ_Q_CLK_PHASE controls the phase of the Q channel's demodulator. Changing the phase of the demodulator can be used to compare the I and Q channel gains. BIOZ_Q_CLK_PHASE DECODE 0 Normal Operation. The Q channel demodulator's clock is in quadrature phase to the stimulus signal. 1 I Phase. The Q channel demodulator's clock is in phase with the stimulus signal. BIOZ_I_CLK_PHASE: BIOZ I Clock Phase Control Bit BIOZ_I_CLK_PHASE controls the phase of the I channel's demodulator. Changing the phase of the demodulator can be used to compare the I and Q channel gains. BIOZ_I_CLK_PHASE DECODE 0 Normal Operation. The I channel demodulator's clock is in phase to the stimulus signal. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 80

BIOZ_I_CLK_PHASE DECODE 1 Q Phase. The I channel demodulator's clock is in quadrature phase with the stimulus signal. BIOZ_INA_CHOP_EN: BIOZ Instrumentation Amplifier Mode BIOZ_INA_CHOP_EN enables chopping in the BioZ receive channel's instrumentation amplifier. The chopping frequency is BIOZ_ADC_CLK / 2. INA chopping is recommended except when F_BIOZ = BIOZ_ADC_CLK / 2. BIOZ_INA_CHOP_EN DECODE

0 BIOZ_ADC_CLK / 2 chopping disabled

1 BIOZ_ADC_CLK / 2 chopping enabled

BIOZ_CH_FSEL: BIOZ PGA Chopping Frequency Select BIOZ_CH_FSEL selects the chopping frequency of the BioZ receive channel PGA and AAF. Set to 1 if the F_BIOZ is equal to BIOZ_ADC_CLK / 8. Otherwise, set to 0.Note: The synthesis frequency must not equal the PGA chopping frequency or the correlator does not work. Use BIOZ_CH_FSEL to ensure they are not equal. BIOZ_CH_FSEL DECODE

0 BioZ PGA chopping frequency is fBIOZ_ADC_CLK / 8

1 BioZ PGA chopping frequency is fBIOZ_ADC_CLK / 4

BioZ Mux Configuration 1 (0x41) BIT 7 6 5 4 3 2 1 0 Field BMUX_RSEL[1:0] BMUX_BIS T_EN – – CONNECT_ CAL_ONLY MUX_EN CAL_EN Reset 0x0 0 – – 0 0 0 Access Type Write, Read Write, Read – – Write, Read Write, Read Write, Read BMUX_RSEL: BIOZ Resistive Load Select for non-GSR Applications BMUX_RSEL selects the value of the resistive calibration load applied across DRVP/BIP and DRVN/BIN for non-GSR applications. This load is only applied when BMUX_BIST_EN = 1. The resistor error is measured during factory test, and the error value is saved in BIST_R_ERR7:0. BMUX_RSEL[1:0] CALIBRATION RESISTANCE (Ω) 0x0 5100 0x1 900 0x2 600 0x3 280 BMUX_BIST_EN: BIOZ Resistance Built-In-Self-Test (R BIST) Mode Enable BMUX_BIST_EN enables the built-in self-test resistor between DRVP/BIP and DRVN/BIN for non-GSR applications. To avoid external interference, disable both MUX_EN and CAL_EN when using BMUX_BIST_EN. The resistive value is selected by BMUX_RSEL. BMUX_BIST_EN DECODE 0 Disabled. The internal resistive load is disconnected. 1 Enabled. The internal resistive load is connected between DRVP and BIP, and DRVN and BIN. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 81

CONNECT_CAL_ONLY: CONNECT_CAL_ONLY When both MUX_EN and CAL_EN are set to 1, enabling CONNECT_CAL_ONLY connects only the CAL1 to CAL4 pins, and disconnects the ELx pins. See MUX_EN for details. CAL CONNECT_CAL_ONLY Use Case 0 0 EL1-EL4 connected only 0 1 EL1-EL4 connected only 1 0 CAL + EL1-EL4 connected 1 1 CAL connected only MUX_EN: Enable MUX MUX_EN enables the BioZ input/output MUX connections to the ELx pins and/or CALx pins selected by DRVP_ASSIGN, DRVN_ASSIGN, BIP_ASSIGN, BIN_ASSIGN, CAL_EN, and CONNECT_CAL_ONLY. MUX_EN CAL_EN CONNECT_CAL_ONLY DECODE 0 X X MUX Disabled. All ELx and CALx pins are disconnected. 1 0 X ELx pins are connected according to BIP_ASSIGN, BIN_ASSIGN, DRVP_ASSIGN, and DRVN_ASSIGN. CALx pins are disconnected. 1 1 0 ELx pins are connected according to BIP_ASSIGN, BIN_ASSIGN, DRVP_ASSIGN, and DRVN_ASSIGN. CALx pins are also connected. 1 1 1 ELx pins are disconnected. CALx pins are connected only. CAL_EN: Enable Calibration CAL_EN connects the calibration pins (CAL1 to CAL4) of the BioZ input/output MUX to measure the external calibration resistor when MUX_EN = 1. See MUX_EN for details. CAL_EN DECODE 0 Calibration pins are disconnected. 1 Calibration pins are connected. CAL1 = DRVP, CAL2 = BIP, CAL3 = BIN, and CAL4 = DRVN. Electrode pins E1, E2A, E2B, E3A, E3B, and E4 are disconnected. BioZ Mux Configuration 2 (0x42) BIT 7 6 5 4 3 2 1 0 Field BMUX_GSR_RSEL[1:0] GSR_LOAD LOAD EN_INT_IN LOAD Reset 0x0 0 – – – 0 0 Access Type Write, Read Write, Read – – – Write, Read Write, Read BMUX_GSR_RSEL: BIOZ Resistive Load Select for GSR Applications BMUX_GSR_RSEL selects the value of the resistive calibration load applied across DRVP/BIP and DRVN/BIN for GSR applications. This load is only applied when GSR_LOAD_EN = 1. BMUX_GSR_RSEL[1:0] LOAD RESISTANCE (kΩ) 0x0 25.7 0x1 101 0x2 505 0x3 1000 MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 82

GSR_LOAD_EN: Enable Load for GSR Applications GSR_LOAD_EN enables the built in GSR load resistor between DRVP/BIP and DRVN/BIN. To avoid external interference, disable both MUX_EN and CAL_EN when using GSR_LOAD_EN. The resistive value is selected by BMUX_GSR_RSEL. GSR_LOAD_EN DECODE 0 Disabled. The internal resistive load is disconnected. 1 Enabled. The internal resistive load is connected between DRVP and BIP, and DRVN and BIN. EN_EXT_INLOAD: EN_EXT_INLOAD EN_EXT_INLOAD enables the external guard-trace-drive circuit, which outputs the buffered voltage from BIP and BIN onto the EL2A and EL3A pins. EN_EXT_INLOAD DECODE 0 External guard-drive circuit disabled. 1 External guard-drive circuit enabled. EN_INT_INLOAD: EN_INT_INLOAD EN_INT_INLOAD enables the circuit that compensates for input capacitive loading on BIN and BIP. EN_INT_INLOAD DECODE 0 Input capacitive loading compensation circuit disabled. 1 Input capacitive loading compensation circuit enabled. BioZ Mux Configuration 3 (0x43) BIT 7 6 5 4 3 2 1 0 Field BIP_ASSIGN[1:0] BIN_ASSIGN[1:0] DRVP_ASSIGN[1:0] DRVN_ASSIGN[1:0] Reset 0x0 0x0 0x0 0x0 Access Type Write, Read Write, Read Write, Read Write, Read BIP_ASSIGN: BIP Assignment BIP_ASSIGN selects the electrode pin used for the BioZ positive input (BIP) when MUX_EN = 1. When CAL_EN = 1, this selection is ignored and the electrode pins are disconnected. BIP_ASSIGN[1:0] ASSIGNED ELECTRODE PIN 0x0 EL1 0x1 EL2A 0x2 EL2B 0x3 Do not use. BIN_ASSIGN: BIN Assignment BIN_ASSIGN selects the electrode pin used for the BioZ negative input (BIN) when MUX_EN = 1. When CAL_EN = 1, this selection is ignored and the electrode pins are disconnected. BIN_ASSIGN[1:0] ASSIGNED ELECTRODE PIN 0x0 EL4 0x1 EL3A 0x2 EL3B MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 83

BIN_ASSIGN[1:0] ASSIGNED ELECTRODE PIN 0x3 Do not use. DRVP_ASSIGN: DRVP Assignment DRVP_ASSIGN selects the electrode pin used for the BioZ positive drive (DRVP) in the current mode when MUX_EN = 1. When CAL_EN = 1, this selection is ignored and the electrode pins are disconnected. In voltage or H-bridge mode, the BioZ positive drive only connects to EL1. The EL1 MUX switch has lower on-resistance than EL2A and EL2B. So, assign DRVP to EL1 when using currents or 64μA or greater. BIOZ_DRV_MODE[1:0] DRVP_ASSIGN[1:0] ASSIGNED ELECTRODE PIN 0x0 or 0x3 0x0 EL1 (low resistance) 0x0 or 0x3 0x1 EL2A 0x0 or 0x3 0x2 EL2B 0x0 or 0x3 0x3 Do not use. 0x1 X EL1 0x2 X EL1 DRVN_ASSIGN: DRVN Assignment DRVN_ASSIGN selects the electrode pin used for the BioZ negative drive (DRVN) in the current mode when MUX_EN = 1. When CAL_EN = 1, this selection is ignored and the electrode pins are disconnected. In voltage or H-bridge mode, the BioZ negative drive only connects to EL4. The EL4 MUX switch has lower on-resistance than EL3A and EL3B. So, assign DRVN to EL4 when using currents or 64μA or greater. BIOZ_DRV_MODE[1:0] DRVN_ASSIGN[1:0] ASSIGNED ELECTRODE PIN 0x0 or 0x3 0x0 EL4 (low resistance) 0x0 or 0x3 0x1 EL3A 0x0 or 0x3 0x2 EL3B 0x0 or 0x3 0x3 Do not use. 0x1 X EL4 0x2 X EL4 BioZ Mux Configuration 4 (0x44) BIT 7 6 5 4 3 2 1 0 Field BIST_R_ERR[7:0] Reset 0x00 Access Type Read Only BIST_R_ERR: BIST_R_ERR The on-chip Built-In Self-Test (BIST) resistors are available to calibrate the BioZ channel magnitude/phase error. 5.1kΩ, 900Ω, 600Ω, or 280Ω of resistors can be chosen by BMUX_RSEL. Due to process variations, the actual resistances vary by up to ±25%. During factory test, the actual resistance of the 600Ω resistor is measured with an accuracy of ±1.5%, and the error stored in the BIST_R_ERR field. The actual resistance (to within ±1.5%) can be calculated with the following equation, where BIST_R_ERR is a 2's complement representation. The other values (5.1kΩ, 900Ω, and 280Ω) are process-matched to the 600Ω resistor with approximately 2% precision. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 84

RACTUAL = RNOMINAL x (1 + BIST_R_ERR / 512) For example, when BIST_R_ERR = 64 and BMUX_RSEL = 0x2, RACTUAL = 600Ω x (1 + 64 / 512) = 675Ω ±1.5%. BIST_R_ERR is a read-only register. DC Leads Configuration (0x50) BIT 7 6 5 4 3 2 1 0 Field EN_LON_D ET EN_LOFF_ DET EN_EXT_L OFF EN_DRV_O OR LOFF_IPOL LOFF_IMAG[2:0] Reset 0 0 0 0 0 0x0 Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read EN_LON_DET: Leads On Detect Enable EN_LOT_DET enables Ultra-Low-Power (ULP) DC lead-on detection on the BIP and BIN inputs. ULP mode only functions when BioZ is not enabled (BIOZ_I_EN = BIOZ_Q_EN = 0). EN_LON_DET DECODE 0 ULP lead-on detection is disabled. 1 ULP lead-on detection is enabled. EN_LOFF_DET: Leads Off Detect Enable EN_LOFF_DET enables DC lead-off detection on the BIP and BIN inputs, and only functions when BioZ is enabled (BIOZ_I_EN or BIOZ_Q_EN = 1). When enabled, the lead-off status is reported by the DC_LOFF_PH, DC_LOFF_PL, DC_LOFF_NH, and DC_LOFF_NL status bits and interrupts. EN_LOFF_DET DECODE 0 BioZ DC lead-off detection is disabled. 1 BioZ DC lead-off detection is enabled. EN_EXT_LOFF: EN_EXT_LOFF EN_EXT_LOFF enables DC lead-off detection on the EL2B and EL3B pins when the EL2A and EL3A pins are being used as AC-coupled BioZ inputs. EL2B and EL3B must be connected externally to the electrode side of the AC-coupling capacitors for this feature to function. EN_EXT_LOFF DECODE 0 DC lead-off detection is applied to the internal BIP and BIN nodes.

1 DC lead-off detection is applied externally through EL2B and EL3B for AC-

coupled applications. EN_DRV_OOR: EN_DRV_OOR EN_DRV_OOR enables the voltage monitor on DRVN to detect drive electrode lead-off conditions. If the total impedance between DRVP and DRVN is high, due to either the DRVP or DRVN electrode being disconnected, the AC voltage at DRVN is large, and triggers a DRV_OOR status and interrupt. EN_DRV_OOR DECODE 0 Drive voltage out-of-range detection is disabled. 1 Drive voltage out-of-range detection is enabled. LOFF_IPOL: LOFF_IPOL LOFF_IPOL sets the polarity of the matched DC current sources used for DC lead-off detection. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 85

LOFF_IPOL LEAD-OFF CURRENT POLARITY 0 Non-inverted. BIP sources current, BIN sinks current. 1 Inverted. BIP sinks current, BIN sources current. LOFF_IMAG: LOFF_IMAG LOFF_IMAG selects the DC lead-off current amplitude. LOFF_IMAG[2:0] DC CURRENT MAGNITUDE (nA) 0x0 0 (Current sources disabled) 0x1 5 0x2 10 0x3 20 0x4 50 0x5 100 0x6 100 0x7 100 DC Lead Detect Threshold (0x51) BIT 7 6 5 4 3 2 1 0 Field – – – – LOFF_THRESH[3:0] Reset – – – – 0x0 Access Type – – – – Write, Read LOFF_THRESH: DC Lead Off Threshold LOFF_THRESH selects the voltage threshold for the DC lead-off window comparators, which are centered at VMID_RX. If the voltage of either BIP or BIN goes above the high threshold or below the low threshold for approximately 128ms, the corresponding DC_LOFF status bit is set to 1 in register 0x01. If LOFF_RAPID = 1, the 128ms delay is bypassed and the status asserts immediately. LOFF_THRESH[3:0] DC LEAD-OFF THRESHOLD 0x0 VMID_RX ± 215mV 0x1 VMID_RX ± 245mV 0x2 VMID_RX ± 275mV 0x3 VMID_RX ± 305mV 0x4 VMID_RX ± 335mV 0x5 VMID_RX ± 365mV 0x6 VMID_RX ± 395mV 0x7 VMID_RX ± 425mV 0x8 VMID_RX ± 455mV 0x9 VMID_RX ± 485mV 0xA VMID_RX ± 515mV 0xB VMID_RX ± 545mV 0xC VMID_RX ± 575mV 0xD VMID_RX ± 605mV 0xE VMID_RX ± 635mV MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 86

LOFF_THRESH[3:0] DC LEAD-OFF THRESHOLD 0x0 VMID_RX ± 215mV 0x1 VMID_RX ± 245mV 0x2 VMID_RX ± 275mV 0x3 VMID_RX ± 305mV 0x4 VMID_RX ± 335mV 0x5 VMID_RX ± 365mV 0x6 VMID_RX ± 395mV 0x7 VMID_RX ± 425mV 0x8 VMID_RX ± 455mV 0x9 VMID_RX ± 485mV 0xA VMID_RX ± 515mV 0xB VMID_RX ± 545mV 0xF VMID_RX ± 665mV Lead Bias Configuration 1 (0x58) BIT 7 6 5 4 3 2 1 0 Field – – – – RBIAS_VALUE[1:0] EN_RBIAS_ BIP EN_RBIAS_ BIN Reset – – – – 0x0 0 0 Access Type – – – – Write, Read Write, Read Write, Read RBIAS_VALUE: Bias Resistance Selection RBIAS_VALUE selects the BioZ input lead bias resistance, which is between BIP and VMID_RX (EN_RBIAS_BIP = 1), and BIN and VMID_RX (EN_RBIAS_BIN = 1). RBIAS_VALUE[1:0] BIAS RESISTANCE (MΩ) 0x0 50 0x1 100 0x2 200 0x3 Do not use. EN_RBIAS_BIP: Enable Resistive Bias on Positive Input EN_RBIAS_BIP enables lead bias on BIP. The resistor connecting BIP to VMID_RX is selected in RBIAS_VALUE. EN_RBIAS_BIP DECODE 0 BIP is not resistively connected to VMID_RX. 1 BIP is connected to VMID_RX through a resistor (selected by RBIAS_VALUE). EN_RBIAS_BIN: Enable Resistive Bias on Negative Input EN_RBIAS_BIN enables lead bias on BIN. The resistor connecting BIN to VMID_RX is selected in RBIAS_VALUE. EN_RBIAS_BIN DECODE 0 BIN is not resistively connected to VMID_RX. 1 BIN is connected to VMID_RX through a resistor (selected by RBIAS_VALUE). MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 87

Interrupt Enable 1 (0x80) BIT 7 6 5 4 3 2 1 0 Field A_FULL_E N – FIFO_DATA _RDY_EN FREQ_UNL OCK_EN FREQ_LOC K_EN PHASE_UN LOCK_EN PHASE_LO CK_EN – Reset 0 – 0 0 0 0 0 – Access Type Write, Read – Write, Read Write, Read Write, Read Write, Read Write, Read – A_FULL_EN: Enable A_FULL Interrupt on INT Enables the A_FULL7 status bit to be output to the INT output pin. FIFO_DATA_RDY_EN: Enable FIFO_DATA_RDY Interrupt on INT Enables the FIFO_DATA_RDY5 status bit to be output to the INT output pin. FREQ_UNLOCK_EN: Enable FREQ_UNLOCK Interrupt on INT Enables the FREQ_UNLOCK4 status bit to be output to the INT output pin. FREQ_LOCK_EN: Enable FREQ_LOCK Interrupt on INT Enables the FREQ_LOCK3 status bit to be output to the INT output pin. PHASE_UNLOCK_EN: Enable PLL_UNLOCK Interrupt on INT Enables the PHASE_UNLOCK2 status bit to be output to the INT output pin. PHASE_LOCK_EN: Enable PLL_LOCK Interrupt on INT Enables the PHASE_LOCK1 status bit to be output to the INT output pin. Interrupt Enable 2 (0x81) BIT 7 6 5 4 3 2 1 0 Field LON_EN BIOZ_OVE R_EN BIOZ_UND R_EN DRV_OOR_ EN DC_LOFF_ PH_EN DC_LOFF_ PL_EN DC_LOFF_ NH_EN DC_LOFF_ NL_EN Reset 0 0 0 0 0 0 0 0 Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read LON_EN: Enable LON Interrupt on INT Enables the LON7 status bit to be output to the INT output pin. BIOZ_OVER_EN: Enable BIOZ_OVER Interrupt on INT Enables the BIOZ_OVER6 status bit to be output to the INT output pin. BIOZ_UNDR_EN: Enable BIOZ_UNDR Interrupt on INT Enables the BIOZ_UNDR5 status bit to be output to the INT output pin. DRV_OOR_EN: Enable DRVP_OFF Interrupt on INT Enables the DRV_OOR4 status bit to be output to the INT output pin. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 88

DC_LOFF_PH_EN: Enable DC_LOFF_PH Interrupt on INT Enables the DC_LOFF_PH3 status bit to be output to the INT output pin. DC_LOFF_PL_EN: Enable DC_LOFF_PL Interrupt on INT Enables the DC_LOFF_PL2 status bit to be output to the INT output pin. DC_LOFF_NH_EN: Enable DC_LOFF_NH Interrupt on INT Enables the DC_LOFF_NH1 status bit to be output to the INT output pin. DC_LOFF_NL_EN: Enable DC_LOFF_NL Interrupt on INT Enables the DC_LOFF_NL0 status bit to be output to the INT output pin. Part ID (0xFF) BIT 7 6 5 4 3 2 1 0 Field PART_ID[7:0] Reset 0x42 Access Type Read Only PART_ID: Part Identifier MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 89

to set the current magnitude, this lockout feature does not apply. Table 10. Allowed Current Magnitudes vs. Frequency

Typical Application Circuits 4-Electrode Device Supporting BIA/BIS, Respiration, or ICG EL1 (DRVP) EL2B (BIP) EL3B (BIN) EL4 (DRVN) 1µF AGND DGND AVDD DVDD VREF DRVSJ 10µF0.1µF 0.1µF MAX30009MAX30009 DRVXC DRVXR EL2AN.C. EL3AN.C. ELECTRODES 47nF REXT (OPTIONAL) +1.8V 47nF (OPTIONAL) 47nF 40.2kΩ 40.2kΩ IEC 60601-1 SINGLE-FAULT PATIENT PROTECTION SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT FCLK HOST MCU FCLK INT MISO MOSI SCLK CSB N.C. NOTES:

• FOR IEC 60601-1 SINGLE FAULT PATIENT SAFETY COMPLIANCE, EACH ELECTRODE PIN SHOULD HAVE A SERIES RESISTOR OR CAPACITOR TO LIMIT DC CURRENT INTO THE ELECTRODE IN THE CASE OF A SHORT OF THE ELx PIN TO A NEARBY POWER SUPPLY VOLTAGE OR GND. TO LIMIT THE DC CURRENT TO 50µA, THE SERIES RESISTANCE SHOULD BE ≥ (VSUPPLY / 50µA), WHERE VSUPPLY IS THE HIGHEST NEARBY VOLTAGE.
• THE DIGITAL INTERFACE IS SHOWN IN SPI CONFIGURATION. I2C CONFIGURATION CAN BE SELECTED BY TYING CSB/I2C_SEL HIGH, TYING SDO/ ADDR LOW OR HIGH, AND ADDING PULLUP RESISTORS TO SDI/SDA AND SCLK/SCL.
• THE INT OUTPUT IS SHOWN IN PUSH-PULL CONFIGURATION, WHICH IS PROGRAMMED BY INT_OCFG3:2. FOR OPEN-DRAIN CONFIGURATION, ADD A PULLUP RESISTOR. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 91

Typical Application Circuits (continued) 2-Electrode Device Supporting GSR/EDA EL1 (DRVP) EL2B (BIP) EL3B (BIN) EL4 (DRVN) 1µF AGND DGND AVDD DVDD SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT FCLK VREF DRVSJ 10µF0.1µF 0.1µF FCLK INT MISO MOSI SCLK CSB HOST MCU MAX30009MAX30009 DRVXC DRVXR EL2A N.C. EL3A N.C.ELECTRODES 47nF REXT (OPTIONAL) N.C. +1.8V 47nF (OPTIONAL) 47nF IEC 60601-1 SINGLE-FAULT PATIENT PROTECTION 47nF 47nF NOTES:

• FOR IEC 60601-1 SINGLE FAULT PATIENT SAFETY COMPLIANCE, EACH ELECTRODE PIN SHOULD HAVE A SERIES RESISTOR OR CAPACITOR TO LIMIT DC CURRENT INTO THE ELECTRODE IN THE CASE OF A SHORT OF THE ELx PIN TO A NEARBY POWER SUPPLY VOLTAGE OR GND. TO LIMIT THE DC CURRENT TO 50µA, THE SERIES RESISTANCE SHOULD BE ≥ (VSUPPLY / 50µA), WHERE VSUPPLY IS THE HIGHEST NEARBY VOLTAGE.
• THE DIGITAL INTERFACE IS SHOWN IN SPI CONFIGURATION. I2C CONFIGURATION CAN BE SELECTED BY TYING CSB/I2C_SEL HIGH, TYING SDO/ ADDR LOW OR HIGH, AND ADDING PULLUP RESISTORS TO SDI/SDA AND SCLK/SCL.
• THE INT OUTPUT IS SHOWN IN PUSH-PULL CONFIGURATION, WHICH IS PROGRAMMED BY INT_OCFG3:2. FOR OPEN-DRAIN CONFIGURATION, ADD A PULLUP RESISTOR. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 92

Typical Application Circuits (continued) 4-Electrode Wrist Device Supporting BIA and GSR EL2B (DRVP_BIA) EL3B (BIN_BIA) EL1 (DRVP_GSR) EL4 (DRVN) EL2A (BIP) EL3A (BIN_GSR) 1µF SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT FCLKVREF FCLK INT MISO MOSI SCLK CSB HOST MCU MAX30009MAX30009 BIOIMPEDANCEBIOIMPEDANCE AFEAFE ELECTRODES NOTES:

• FOR IEC 60601-1 SINGLE FAULT PATIENT SAFETY COMPLIANCE, EACH ELECTRODE PIN SHOULD HAVE A SERIES RESISTOR OR CAPACITOR TO LIMIT DC CURRENT INTO THE ELECTRODE IN THE CASE OF A SHORT OF THE ELx PIN TO A NEARBY POWER SUPPLY VOLTAGE OR GND. TO LIMIT THE DC CURRENT TO 50µA, THE SERIES RESISTANCE SHOULD BE ≥ (VSUPPLY / 50µA), WHERE VSUPPLY IS THE HIGHEST NEARBY VOLTAGE.
• THE DIGITAL INTERFACE IS SHOWN IN SPI CONFIGURATION. I2C CONFIGURATION CAN BE SELECTED BY TYING CSB/I2C_SEL HIGH, TYING SDO/ ADDR LOW OR HIGH, AND ADDING PULLUP RESISTORS TO SDI/SDA AND SCLK/SCL.
• THE INT OUTPUT IS SHOWN IN PUSH-PULL CONFIGURATION, WHICH IS PROGRAMMED BY INT_OCFG3:2. FOR OPEN-DRAIN CONFIGURATION, ADD A PULLUP RESISTOR. N.C. AGND DGND 47nF 47nF 47nF 47nF 47nF 47nF BEZEL 1 ELECTRODE WRIST 2 ELECTRODE WRIST 1 ELECTRODE BEZEL 2 ELECTRODE DRVSJ DRVXC DRVXR REXT (OPTIONAL) 47nF (OPTIONAL) AVDD DVDD 10µF0.1µF 0.1µF +1.8V MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 93

Typical Application Circuits (continued) 2-Electrode Chest Device Supporting Respiration with ECG and PPG LA/LLLA/LL RARA EL1 (DRVP) EL2B (BIP) EL3B (BIN) EL4 (DRVN) 1µF AGND DGND SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT FCLKVREF FCLK INT MISO MOSI SCLK CSB0 HOST MCU MAX30009MAX30009 BIOIMPEDANCEBIOIMPEDANCE AFEAFE EL2AN.C. EL3A AGND DGND SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT1 INT2 MAXIMMAXIM BIOPOTENTIALBIOPOTENTIAL AND PPGAND PPG AFEAFE CSB1 FCLK N.C. ECGP ECGN CAPP CAPN VMID_ECG VREF_ECG 1µF10µF RLD RLD_INVN.C. 40.2kΩ OPTIONALOPTIONAL RLRL ELECTRODES CHPF 47nF BIOZ H-BRIDGE MODE CONFIGURATION CURRENT IS LIMITED TO AVDD / (2 x RSERIES) LED1_DRV LED2_DRV LED3_DRV PGND VLED VLED 10µF 0.1µF PD1_IN PD_GND PLL SYNC INPUT DGND PGND DGND 40.2kΩ 0.1% 40.2kΩ 0.1% 18.2kΩ 0.1% 47nF18.2kΩ 0.1% N.C. PLL SYNC OUTPUT NOTES:

• FOR IEC 60601-1 SINGLE FAULT PATIENT SAFETY COMPLIANCE, EACH ELECTRODE PIN SHOULD HAVE A SERIES RESISTOR OR CAPACITOR TO LIMIT DC CURRENT INTO THE ELECTRODE IN THE CASE OF A SHORT OF THE ELx PIN TO A NEARBY POWER SUPPLY VOLTAGE OR GND. TO LIMIT THE DC CURRENT TO 50µA, THE SERIES RESISTANCE SHOULD BE ≥ (VSUPPLY / 50µA), WHERE VSUPPLY IS THE HIGHEST NEARBY VOLTAGE.
• THE DIGITAL INTERFACE IS SHOWN IN SPI CONFIGURATION. TO AVOID FALSE I2C START CONDITIONS ON THE SHARED BUS, SET DISABLE_I2C6 = 1. I2C CONFIGURATION CAN BE SELECTED BY TYING CSB/I2C_SEL HIGH, TYING SDO/ADDR LOW OR HIGH, AND ADDING PULLUP RESISTORS TO SDI/SDA AND SCLK/SCL.
• THE INT OUTPUT IS SHOWN IN PUSH-PULL CONFIGURATION, WHICH IS PROGRAMMED BY INT_OCFG3:2. FOR OPEN-DRAIN CONFIGURATION, ADD A PULLUP RESISTOR. DRVSJ DRVXCDRVXR AVDD DVDD 10µF0.1µF 0.1µF +1.8V AVDD DVDD 10uF0.1uF 0.1uF +1.8V MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 94

Typical Application Circuits (continued) 2-Electrode Chest Device Supporting Respiration with ECG and Defibrillation Protection ¼ MAX30034 ¼ MAX30034 USE DEFIB ENERGY RATED RESISTORS FOR RLIM RLIM 20kΩ RLIM 20kΩ ¼ MAX30034 RLIM LA/LLLA/LL RARA EL1 (DRVP) EL2B (BIP) EL3B (BIN) EL4 (DRVN) 1µF AGND DGND SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT FCLK VREF FCLK INT MISO MOSI SCLK CSB0 HOST MCU MAX30009MAX30009 BIOIMPEDANCEBIOIMPEDANCE AFEAFE EL2AN.C. EL3A AGND DGND SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT1 INT2 MAXIMMAXIM BIOPOTENTIALBIOPOTENTIAL AFEAFE CSB1 FCLK N.C. ECGP ECGN CAPP CAPN VMID_ECG VREF_ECG 1µF10µF RLD RLD_INVN.C. 40.2kΩ OPTIONALOPTIONAL RLRL ELECTRODES CHPF 47nF BIOZ H-BRIDGE MODE CONFIGURATION CURRENT IS LIMITED TO AVDD / (2 x RSERIES) PLL SYNC INPUT DGND DGND RSEC 20kΩ 18.2kΩ 0.1% 47nF18.2kΩ 0.1% N.C. PLL SYNC OUTPUT RSEC 20kΩ NOTES:

• FOR IEC 60601-1 SINGLE FAULT PATIENT SAFETY COMPLIANCE, EACH ELECTRODE PIN SHOULD HAVE A SERIES RESISTOR OR CAPACITOR TO LIMIT DC CURRENT INTO THE ELECTRODE IN THE CASE OF A SHORT OF THE ELx PIN TO A NEARBY POWER SUPPLY VOLTAGE OR GND. TO LIMIT THE DC CURRENT TO 50µA, THE SERIES RESISTANCE SHOULD BE ≥ (VSUPPLY / 50µA), WHERE VSUPPLY IS THE HIGHEST NEARBY VOLTAGE.
• THE DIGITAL INTERFACE IS SHOWN IN SPI CONFIGURATION. TO AVOID FALSE I2C START CONDITIONS ON THE SHARED BUS, SET DISABLE_I2C6 = 1. I2C CONFIGURATION CAN BE SELECTED BY TYING CSB/I2C_SEL HIGH, TYING SDO/ADDR LOW OR HIGH, AND ADDING PULLUP RESISTORS TO SDI/SDA AND SCLK/SCL.
• THE INT OUTPUT IS SHOWN IN PUSH-PULL CONFIGURATION, WHICH IS PROGRAMMED BY INT_OCFG3:2. FOR OPEN-DRAIN CONFIGURATION, ADD A PULLUP RESISTOR. AVDD DVDD 10µF0.1µF 0.1µF +1.8V AVDD DVDD 10µF0.1µF 0.1µF +1.8V DRVSJ DRVXC DRVXR MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 95

Typical Application Circuits (continued) 6-Electrode Device Supporting Multiple Measurement Vectors EL2A(DRVP/BIP) EL3A(DRVN/BIN) EL1(DRVP/BIP) EL4(DRVN/BIN) EL2B(DRVP/BIP) EL3B(DRVN/BIN) 1µF SDI/SDA SDO/ADDR CSB/I2C_SEL SCLK/SCL TRIG INT FCLKVREF FCLK INT MISO MOSI SCLK CSB HOST MCU MAX30009MAX30009 BIOIMPEDANCEBIOIMPEDANCE AFEAFE ELECTRODES 47nF 47nF 47nF 47nF 47nF 47nF AGND DGND N.C. NOTES:

• FOR IEC 60601-1 SINGLE FAULT PATIENT SAFETY COMPLIANCE, EACH ELECTRODE PIN SHOULD HAVE A SERIES RESISTOR OR CAPACITOR TO LIMIT DC CURRENT INTO THE ELECTRODE IN THE CASE OF A SHORT OF THE ELx PIN TO A NEARBY POWER SUPPLY VOLTAGE OR GND. TO LIMIT THE DC CURRENT TO 50µA, THE SERIES RESISTANCE SHOULD BE ≥ (VSUPPLY / 50µA), WHERE VSUPPLY IS THE HIGHEST NEARBY VOLTAGE.
• THE DIGITAL INTERFACE IS SHOWN IN SPI CONFIGURATION. I2C CONFIGURATION CAN BE SELECTED BY TYING CSB/I2C_SEL HIGH, TYING SDO/ ADDR LOW OR HIGH, AND ADDING PULLUP RESISTORS TO SDI/SDA AND SCLK/SCL.
• THE INT OUTPUT IS SHOWN IN PUSH-PULL CONFIGURATION, WHICH IS PROGRAMMED BY INT_OCFG3:2. FOR OPEN-DRAIN CONFIGURATION, ADD A PULLUP RESISTOR. DRVSJ DRVXC DRVXR REXT (OPTIONAL) 47nF (OPTIONAL) AVDD DVDD 10µF0.1µF 0.1µF +1.8V

Ordering Information

PART NUMBER TEMP RANGE PIN-PACKAGE MAX30009ENA+ -40°C to +85°C 25 WLP MAX30009ENA+T -40°C to +85°C 25 WLP + Denotes a lead(Pb)-free/RoHS-compliant package. T Denotes tape-and-reel. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End www.analog.com Analog Devices | 96

Revision History

0 12/21 Initial release — 1 1/22 Updated General Description, Simplified Block Diagram, I2C Timing Characteristics, Pin Configuration 1, 2, 14, 20 2 8/23 Updated General Description, Benefits and Features, Simplified Block Diagram, Electrical Characteristics table, Pin Description, Detailed Description, figure 01, figure 25, figure 26, figure 27, figure 28, and Register Details Sections. Added Sine- Wave Current Stimulus Compliance Voltage Section. 1, 2, 10, 20–27, 31, 35, 38, 39, 50–57, 60, 67, and 73 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. MAX30009 Low-Power, High-Performance Bioimpedance Analog Front-End w w w . a n a l o g . c o m Analog Devices | 97