MAX1039

MAX1036 MAXIM | Alldatasheet

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Technical content

Features

o High-Speed I2C-Compatible Serial Interface 400kHz Fast Mode 1.7MHz High-Speed Mode o Single Supply 2.7V to 3.6V (MAX1037/MAX1039) 4.5V to 5.5V (MAX1036/MAX1038) o Internal Reference 2.048V (MAX1037/MAX1039) 4.096V (MAX1036/MAX1038) o External Reference: 1V to VDD o Internal Clock o 4-Channel Single-Ended or 2-Channel Pseudo- Differential (MAX1036/MAX1037) o 12-Channel Single-Ended or 6-Channel Pseudo- Differential (MAX1038/MAX1039) o Internal FIFO with Channel-Scan Mode o Low Power 350µA at 188ksps 110µA at 75ksps 8µA at 10ksps 1µA in Power-Down Mode o Software Configurable Unipolar/Bipolar o Small Packages 8-Pin SOT23 (MAX1036/MAX1037) 16-Pin QSOP (MAX1038/MAX1039) MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs

Ordering Information

19-2442; Rev 1; 10/02 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE TUE (LSB) INPUT CHANNELS INTERNAL REFERENCE (V) TOP MARK MAX1036EKA-T -40°C to +85°C 8 SOT23-8 ±2 4 4.096 AAJE MAX1037EKA-T -40°C to +85°C 8 SOT23-8 ±2 4 2.048 AAJG MAX1038AEEE -40°C to +85°C 16 QSOP ±1 12 4.096 — MAX1039AEEE -40°C to +85°C 16 QSOP ±1 12 2.048 — AutoShutdown is a trademark of Maxim Integrated Products, Inc. Pin Configurations and Typical Operating Circuit appear at end of data sheet.

MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(MAX1037/MAX1039), V REF = 4.096V (MAX1036/MAX1038). External clock, f SCL = 1.7MHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AIN0–AIN11, REF to Continuous Power Dissipation (T A = +70°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution 8 Bits Relative Accuracy INL (Note 2) ±1 LSB Differential Nonlinearity DNL No missing codes over temperature ±1 LSB Offset Error ±1.5 LSB Offset Error Temperature Coefficient 3 ppm/°C Gain Error (Note 3) ±1 LSB Gain Temperature Coefficient ±1 ppm/°C MAX1036/MAX1037 ±0.5 ±2Total Unadjusted Error TUE MAX1038A/MAX1039A ±0.5 ±1 LSB Channel-to-Channel Offset Matching ±0.1 LSB Channel-to-Channel Gain Matching ±0.5 LSB Input Common-Mode Rejection Ratio CMRR Pseudo-differential input mode 75 dB DYNAMIC PERFORMANCE (fIN(sine wave) = 25kHz, VIN = VREF(P-P), fSAMPLE = 188ksps, RIN = 100Ω) Signal-to-Noise Plus Distortion SINAD 49 dB Total Harmonic Distortion THD Up to the 5th harmonic -69 dB Spurious-Free Dynamic Range SFDR 69 dB Channel-to-Channel Crosstalk (Note 4) 75 dB Full-Power Bandwidth -3dB point 2.0 MHz Full-Linear Bandwidth SINAD > 49dB 200 kHz CONVERSION RATE Internal clock 6.1Conversion Time (Note 5) tCONV External clock 4.7 µs

MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (MAX1037/MAX1039), V REF = 4.096V (MAX1036/MAX1038). External clock, f SCL = 1.7MHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Internal clock, SCAN[1:0] = 01 (MAX1036/MAX1037) 76 Internal clock, SCAN[1:0] = 00 CS[3:0] = 1011 (MAX1038/MAX1039) 77Throughput Rate fSAMPLE External clock 188 ksps Track/Hold Acquisition Time 588 ns Internal Clock Frequency 2.25 MHz External clock, fast mode 45Aperture Delay t AD External clock, high-speed mode 30 ns ANALOG INPUT (AIN0–AIN11) Unipolar 0 VREFInput Voltage Range, Single Ended and Differential (Note 6) Bipolar ±VREF / 2 V Input Multiplexer Leakage Current On/off-leakage current, VAIN_= 0 or VDD, no clock, fSCL = 0 ±0.01 ±1µ A Input Capacitance C IN 18 pF INTERNAL REFERENCE (Note 7) MAX1037/MAX1039 1.925 2.048 2.171Reference Voltage V REF TA = +25°C MAX1036/MAX1038 3.850 4.096 4.342 V Reference Temperature Coefficient TCREF 120 ppm/°C Reference Short-Circuit Current 10 mA Reference Source Impedance (Note 8) 675 Ω EXTERNAL REFERENCE Reference Input Voltage Range V REF (Note 9) 1.0 VDD V REF Input Current I REF fSAMPLE = 188ksps 14 30 µA DIGITAL INPUTS/OUTPUTS (SCL, SDA) Input High Voltage V IH 0.7 x VDD V Input Low Voltage V IL 0.3 x VDD V Input Hysteresis VHYST 0.1 x VDD V Input Current I IN VIN = 0 to VDD ±10 µA Input Capacitance C IN 15 pF Output Low Voltage V OL ISINK = 3mA 0.4 V

MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (MAX1037/MAX1039), V REF = 4.096V (MAX1036/MAX1038). External clock, f SCL = 1.7MHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS MAX1037/MAX1039 2.7 3.6Supply Voltage (Note 10) V DD MAX1036/MAX1038 4.5 5.5 V Internal REF, external clock 350 650fSAMPLE = 188ksps External REF, external clock 250 External REF, external clock 110fSAMPLE = 75ksps External REF, internal clock 150 External REF, external clock 8fSAMPLE = 10ksps External REF, internal clock 10 External REF, external clock 2fSAMPLE = 1ksps External REF, internal clock 2.5 Supply Current I DD Power-down 1 10 µA Power-Supply Rejection Ratio PSRR (Note 11) ±0.25 ±1 LSB/V TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1A and 2) Serial Clock Frequency f SCL 400 kHz Bus Free Time Between a STOP and a START Condition tBUF 1.3 µs Hold Time for Start Condition tHD, STA 0.6 µs Low Period of the SCL Clock t LOW 1.3 µs High Period of the SCL Clock t HIGH 0.6 µs Setup Time for a Repeated START Condition (Sr) tSU, STA 0.6 µs Data Hold Time tHD, DAT (Note 12) 0 150 ns Data Setup Time tSU, DAT 100 ns Rise Time of Both SDA and SCL Signals, Receiving tR (Note 13) 20 + 0.1CB 300 ns Fall Time of SDA Transmitting t F (Note 13) 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU, STO 0.6 µs Capacitive Load for Each Bus Line CB 400 pF Pulse Width of Spike Suppressed tSP 50 ns TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1B and 2) Serial Clock Frequency f SCLH (Note 14) 1.7 MHz Hold Time (Repeated) Start Condition tHD, STA 160 ns Low Period of the SCL Clock t LOW 320 ns High Period of the SCL Clock t HIGH 120 ns

MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (MAX1037/MAX1039), V REF = 4.096V (MAX1036/MAX1038). External clock, f SCL = 1.7MHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Setup Time for a Repeated START Condition (Sr) tSU, STA 160 ns Data Hold Time tHD, DAT (Note 12) 0 150 ns Data Setup Time tSU, DAT 10 ns Rise Time of SCL Signal (Current Source Enabled) tRCL (Note 13) 20 80 ns Rise Time of SCL Signal After Acknowledge Bit tRCL1 (Note 13) 20 160 ns Fall Time of SCL Signal t FCL (Note 13) 20 80 ns Rise Time of SDA Signal t RDA (Note 13) 20 160 ns Fall Time of SDA Signal t FDA (Note 13) 20 160 ns Setup Time for STOP Condition tSU, STO 160 ns Capacitive Load for Each Bus Line CB 400 pF Pulse Width of Spike Suppressed tSP 01 0 n s Note 1: The MAX1036/MAX1038 are tested at VDD = 5V and the MAX1037/MAX1039 are tested at VDD = 3V. All devices are config- ured for unipolar, single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 3: Offset nulled. Note 4: Ground ON channel; sine wave applied to all OFF channels. Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD. Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor. Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω. Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mVP-P. Note 10: Electrical characteristics are guaranteed from VDD(min) to VDD(max). For operation beyond this range, see the Typical Operating Characteristics. Note 11: Power-supply rejection ratio is measured as: , for the MAX1037/MAX1039 where N is the number of bits (8) and VREF = 2.048V. Power-supply rejection ratio is measured as: , for the MAX1036/MAX1038 where N is the number of bits (8) and VREF = 2.048V. Note 12: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of SCL’s falling edge (Figure 1). Note 13: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD. Minimum specification is tested at +25°C with CB = 400pF. Note 14: fSCLH must meet the minimum clock low time plus the rise/fall times. VV VV V VV FS FS N REF 55 45 2 55 45 () − ()[] × VV VV V VV FS FS N REF 33 27 2 33 27 () − ()[] ×

MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs Typical Operating Characteristics (VDD = 3.3V (MAX1037/MAX1039), VDD = 5V (MAX1036/MAX1038), fSCL = 1.7MHz, external clock (33% duty cycle), fSAMPLE = 188ksps, single ended, unipolar, TA = +25°C, unless otherwise noted.) 150 250 200 350 300 400 450 SUPPLY CURRENT vs. VOLTAGE MAX1036 toc01 VDD (V) IDD (µA) A) INTERNAL 4.096VREF B) INTERNAL 2.048VREF C) EXTERNAL 4.096VREF D) EXTERNAL 2.048VREF A C B D 150 250 200 350 300 400 450 -40 85 SUPPLY CURRENT vs. TEMPERATURE MAX1036 toc02 TEMPERATURE (°C) IDD (µA) 10-15 35 60 INTERNAL 4.096VREF INTERNAL 2.048VREF EXTERNAL 4.096VREF EXTERNAL 2.048VREF SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1036 toc03 VDD (V) IDD (µA) SDA = SCL = VDD -40 10 -15 35 60 85 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX1036 toc04 TEMPERATURE (°C) IDD (µA) SDA = SCL = VDD VDD = 5V VDD = 3.3V 100 200 150 300 250 350 02 0 3 010 40 50 60 AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (INTERNAL CLOCK) MAX1036 toc05 CONVERSION RATE (ksps) AVERAGE IDD (µA) A) INTERNAL REF ALWAYS ON B) INTERNAL REF AUTOSHUTDOWN C) EXTERNAL REF A C B INTERNAL CLOCK MODE fSCL = 1.7MHz 150 100 300 250 200 450 400 350 500 0 100 50 150 200 AVERAGE SUPPLY CURRENT VS. CONVERSION RATE (EXTERNAL CLOCK) MAX1036 toc06 CONVERSION RATE (ksps) AVERAGE IDD (µA) A C B A) INTERNAL REF ALWAYS ON B) INTERNAL REF AUTOSHUTDOWN C) EXTERNAL REF EXTERNAL CLOCK MODE fSCL = 1.7MHz 0.9900 0.9925 0.9950 0.9975 1.0000 1.0025 1.0050 1.0075 1.0100 NORMALIZED 4.096V REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX1036 toc7 VDD (V) VREF NORMALIZED 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 -40 -15 10 35 60 85 INTERNAL 4.096V REFERENCE VOLTAGE vs. TEMPERATURE MAX1036 toc08 TEMPERATURE (°C) VREF NORMALIZED 0.9900 0.9925 0.9950 0.9975 1.0000 1.0025 1.0050 1.0075 1.0100 INTERNAL 2.048V REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX1036 toc09 VDD (V) VREF NORMALIZED

MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 -40 -15 10 35 60 85 INTERNAL 2.048V REFERENCE VOLTAGE vs. TEMPERATURE MAX1036 toc10 TEMPERATURE (°C) VREF NORMALIZED -0.5 -0.2 -0.3 -0.4 -0.1 0.1 0.2 0.3 0.4 0.5 0 100 50 150 200 250 300 DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE MAX1036 toc11 DIGITAL OUTPUT CODE DNL (LSB) -0.5 -0.2 -0.3 -0.4 -0.1 0.1 0.2 0.3 0.4 0.5 0 100 50 150 200 250 300 INTEGRAL NONLINEARITY vs. DIGITAL CODE MAX1036 toc12 DIGITAL OUTPUT CODE INL (LSB) -120 -80 -100 -40 -60 -20 0 100k FFT PLOT MAX1036 toc13 FREQUENCY (Hz) AMPLITUDE (dBc) 40k20k 60k 80k fSAMPLE = 188ksps fIN = 25kHz 0.3 0.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OFFSET ERROR vs. SUPPLY VOLTAGE MAX1036 toc14 VDD (V) OFFSET ERROR (LSB) VREF = 2.048V 0.3 0.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40 10 -15 35 60 85 OFFSET ERROR vs. TEMPERATURE MAX1036 toc15 TEMPERATURE (°C) OFFSET ERROR (LSB) VDD = 3.3V VREF = 2.048V -0.1 -0.07 -0.08 -0.09 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 GAIN ERROR vs. SUPPLY VOLTAGE MAX1036 toc16 VDD (V) GAIN ERROR (LSB) VREF = 2.048V Typical Operating Characteristics (continued) (VDD = 3.3V (MAX1037/MAX1039), VDD = 5V (MAX1036/MAX1038), fSCL = 1.7MHz, external clock (33% duty cycle), fSAMPLE = 188ksps, single ended, unipolar, TA = +25°C, unless otherwise noted.)

MAX1036–MAX1039 Detailed Description The MAX1036 –MAX1039 ADCs use successive- approximation conversion techniques and input T/H cir- cuitry to capture and convert an analog signal to a serial 8-bit digital output. The MAX1036/MAX1037 are 4-channel ADCs, and the MAX1038/MAX1039 are 12- channel ADCs. These devices feature a high-speed 2- wire serial interface supporting data rates up to 1.7MHz. Figure 3 shows the simplified functional dia- gram for the MAX1038/MAX1039. Power Supply The MAX1036–MAX1039 operate from a single supply and consume 350µA at sampling rates up to 188ksps. The MAX1037/MAX1039 feature a 2.048V internal reference and the MAX1036/MAX1038 feature a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to V DD. Analog Input and Track/Hold The MAX1036–MAX1039 analog input architecture con- tains an analog input multiplexer (MUX), a T/H capaci- tor, T/H switches, a comparator, and a switched capacitor digital-to-analog converter (DAC) (Figure 4). In single-ended mode, the analog input multiplexer con- nects C T/H to the analog input selected by CS[3:0] (see the Configuration/Setup Bytes (Write Cycle) section). The charge on CT/H is referenced to GND when converted. In pseudo-differential mode, the analog input multiplexer connects C T/H to the ‘+’ analog input selected by CS[3:0]. The charge on CT/H is referenced to the ‘-’ ana- log input when converted. The MAX1036–MAX1039 input configuration is pseudo- differential in that only the signal at the ‘+’ analog input is sampled with the T/H circuitry. The ‘-’ analog input signal must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from ‘-’ analog input to GND. See the Single-Ended/Pseudo- Differential Input section. During the acquisition interval, the T/H switches are in the track position and C T/H charges to the analog input signal. At the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on C T/H as a sample of the input signal. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator input voltage to zero within the limits of 8-bit resolution. This action requires eight conversion clock cycles and is equiva- lent to transferring a charge of 18pF ✕ (VIN+ - V IN-) from CT/H to the binary weighted capacitive DAC form- ing a digital representation of the analog input signal. Sufficiently low source impedance is required to ensure an accurate sample. A source impedance below 1.5k Ω does not significantly degrade sampling accuracy. To minimize sampling errors with higher source imped- ances, connect a 100pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog input signal integrity. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the ninth falling clock edge 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs PIN MAX1036/ MAX1037 MAX1038/ MAX1039 NAME FUNCTION 1, 2, 3 8, 7, 6 AIN0 –AIN2 — 5, 4, 3, 2, 1 AIN3 –AIN7 — 16, 15, 14 AIN8 –AIN10 Analog Inputs 4 — AIN3/REF Analog Input 3/Reference Input or Output. Selected in the setup register. — 13 AIN11/REF Analog Input 11/Reference Input or Output. Selected in the setup register. 5 9 SCL Clock Input 6 10 SDA Data Input/Output 7 11 GND Ground 81 2 V DD Positive Supply. Bypass to GND with a 0.1µF capacitor. Pin Description

of interest, anti-alias filtering is recommended. than 50mV, the input current should be limited to 2mA. Figure 4. Equivalent Input Circuit

with respect to GND during a conversion. mode (see the Transfer Functions section). and generates SCL to permit that transfer. tion (S), a high-to-low transition on SDA with SCL high. 7 REG Register bit. 1 = Setup Byte, 0 = Configuration Byte (Table 2).

6 SEL2

5 SEL1

4 SEL0

3 CLK 1 = External clock, 0 = Internal clock. Defaulted to zero at power-up. 2 BIP/ UNI 1 = Bipolar, 0 = Unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section). 0 X Don ’t care, can be set to 1 or 0. Table 1. Setup Byte Format

sion with each additional result being stored in RAM. a read command to obtain new conversion results. clock mode if the SCL clock period exceeds 1ms. mode for conversion rates up to 188ksps. Figure 9. Write Cycle

reference and AIN_/REF configured as an analog input. The RAM contents are unknown after power-up. time prior to a STOP or repeated START condition. whether using external or internal reference. for the MAX1036 is 8µA and drops to 2µA at 1ksps. Typical Operating Characteristics section). ply current for external circuitry. 7 REG Register bit. 1 = Setup Byte (Table 1), 0 = Configuration Byte.

6 SCAN1

5 SCAN0

4 CS3

3 CS2

2 CS1

1 CS0

Ended/Pseudo-Differential Input section). Table 2. Configuration Byte Format

Table 3. Channel Selection in Single-Ended Mode (SGL / DIF = 1) Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero. Note 2: When SEL1 = 1, a single-ended read of AIN3/REF (MAX1036/MAX1037) or AIN11/REF (MAX1038/MAX1039) returns GND.

Table 4. Channel Selection in Pseudo-Differential Mode (SGL / DIF = 0) Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero. 1011 returns the negative difference between AIN10 and GND. AIN1–AIN0, AIN3–AIN2, AIN5–AIN4, AIN7–AIN6, AIN9–8, and AIN11–AIN10.

AIN_/REF as possible with a 0.1µF capacitor. polar operations, respectively. sitive analog and reference inputs. is measured using the endpoint method. 0 0 Scans up from AIN0 to the input selected by CS3 –CS0 (default setting). AIN0–AIN2, the scanning stops at AIN2 (MAX1036/MAX1037). scanning stops at AIN6 (MAX1038/MAX1039). Table 5. Scanning Configuration until a not acknowledge occurs. Table 6. Reference Voltage and AIN_/REF Format

In reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency ’s RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 ✕ log (SignalRMS / NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC ’s error consists of quanti- zation noise only. With an input range equal to the ADC’s full-scale range, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal ’s first five harmonics to the fun- damental itself. This is expressed as: where V1 is the fundamental amplitude, and V 2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal compo- nent) to the RMS value of the next-largest distortion component. Chip Information MAX1036/MAX1037 TRANSISTOR COUNT: 6283 MAX1038/MAX1039 TRANSISTOR COUNT: 7257 PROCESS: BiCMOS T H D VVVV V= × +++ 20 2 1log / MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs SDA SCLAIN3/REF VDD GNDAIN1 AIN2 AIN0 SOT23 TOP VIEW MAX1036 MAX1037 AIN7 AIN8 AIN9 AIN10 AIN11/REF VDD GND SDA SCL MAX1038 MAX1039 QSOP AIN6 AIN5 AIN2 AIN4 AIN3 AIN1 AIN0 Pin Configurations *OPTIONAL *RS *RS ANALOG INPUTS µC SDA SCL GND VDD SDA SCL AIN0 AIN1 AIN2 AIN3/REF RP RP MAX1036 MAX1037 MAX1038 MAX1039 Typical Operating Circuit

MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SOT23, 8L.EPS QSOP.EPS