MAX1035

MAX1034 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Software-Programmable Input Range for Each Channel ♦ Single-Ended Input Ranges 0 to +VREF/2, -VREF/2 to 0, 0 to +VREF, -VREF to 0, ±VREF/4, ±VREF/2, and ±VREF ♦ Differential Input Ranges ±VREF/2, ±VREF, and ±2 x VREF ♦ Eight Single-Ended or Four Differential Analog Inputs (MAX1034) ♦ Four Single-Ended or Two Differential Analog Inputs (MAX1035) ♦ ±6V Overvoltage Tolerant Inputs ♦ Internal or External Reference ♦ 115ksps Maximum Sample Rate ♦ Single +5V Power Supply ♦ 20-/24-Pin TSSOP Package MAX1034/MAX1035 8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs Pin Configurations

Ordering Information

19-3574; Rev 0; 5/05 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN- PACKAGE CHANNELS MAX1034EUG* -40°C to +85°C 24 TSSOP 8 MAX1035EUP -40°C to +85°C 20 TSSOP 4 SPI and QSPI are a trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Pin Configurations continued at end of data sheet. *Future product—c ontact factory for availability.

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CS, SCLK, DIN, DOUT, SSTRB to Continuous Power Dissipation (T A = +70°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Notes 1, 2) Resolution 14 Bits Integral Nonlinearity INL ±0.25 ±1 LSB Differential Nonlinearity DNL No missing codes ±1 LSB 0.5Transition Noise External or internal reference LSBRMS Unipolar 0 ±10Single-ended inputs Bipolar -1.0 ±10 Unipolar 0 ±20Offset Error Differential inputs (Note 3) Bipolar -2 ±20 mV Channel-to-Channel Gain Matching Unipolar or bipolar 0.025 %FSR Channel-to-Channel Offset Error Matching Unipolar or bipolar 1.0 mV Unipolar 10Offset Temperature Coefficient Bipolar 5 ppm/°C Unipolar ±0.5Gain Error Bipolar ±0.3 %FSR Unipolar 1.5Gain Temperature Coefficient Bipolar 1.0 ppm/°C Unipolar Endpoint Overlap Negative unipolar full scale to positive unipolar zero-scale 05 LSB

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC SPECIFICATIONS fIN(SINE-WAVE) = 5kHz, VIN = FSR - 0.05dB, fSAMPLE = 130ksps (Notes 1, 2) Differential inputs, FSR = 2 x VREF 84.5 Single-ended inputs, FSR = VREF 84 Single-ended inputs, FSR = VREF / 2 82.5Signal-to-Noise Plus Distortion SINAD Single-ended inputs, FSR = VREF / 4 79 80.5 dB Differential inputs, FSR = 2 x VREF 84.5 Single-ended inputs, FSR = VREF 84 Single-ended inputs, FSR = VREF / 2 82.5Signal-to-Noise Ratio SNR Single-ended inputs, FSR = VREF / 4 80.5 dB Total Harmonic Distortion (Up to the 5th Harmonic) THD -98 dB Spurious-Free Dynamic Range SFDR 92 99 dB Aperture Delay t AD Figure 21 15 ns Aperture Jitter t AJ Figure 21 100 ps Channel-to-Channel Isolation 105 dB CONVERSION RATE External clock mode, Figure 2 114 External acquisition mode, Figure 3 84Byte-Wide Throughput Rate fSAMPLE Internal clock mode, Figure 4 106 ksps ANALOG INPUTS (CH0–CH3 MAX1035, CH0–CH7 MAX1034, AGND1) Small-Signal Bandwidth All input ranges, V IN = 100mVP-P (Note 2) 2 MHz Full-Power Bandwidth All input ranges, V IN = 4VP-P (Note 2) 700 kHz R[2:1] = 001 -VREF/4 +V REF/4 R[2:1] = 100 -VREF/2 +V REF/2 R[2:1] = 101 -VREF 0 R[2:1] = 110 0 +VREF Input Voltage Range (Table 6) V CH_ R[2:1] = 111 -VREF +VREF V True-Differential Analog Common-Mode Voltage Range VCMDR DIF/SGL = 1 -4.75 +5.50 V Common-Mode Rejection Ratio CMRR DIF/SGL = 1, input voltage range = ±VREF/4 75 dB Input Current I CH_ -VREF < VCH_ < +VREF -1500 +650 µA Input Capacitance C CH_ 5p F Input Resistance R CH_ 6k Ω ELECTRICAL CHARACTERISTICS (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1) Reference Output Voltage V REF 4.056 4.096 4.136 V Reference Temperature Coefficient TCREF ±30 ppm/°C REF shorted to AGND1 10Reference Short-Circuit Current I REFSC REF shorted to AVDD -1 mA Reference Load Regulation I REF = 0 to 0.5mA 0.1 10 mV EXTERNAL REFERENCE (REFCAP = AVDD) Reference Input Voltage Range V REF 3.800 4.136 V REFCAP Buffer Disable Threshold VRCTH (Note 4) AVDD1 - 0.4 AVDD1 - 0.1 V VREF = +4.096V, external clock mode, external acquisition mode, internal clock mode, or partial power-down mode 90 200Reference Input Current I REF VREF = +4.096V, full power-down mode ±0.1 ±10 µA External clock mode, external acquisition mode, internal clock mode, or partial power-down mode 20 45Reference Input Resistance R REF Full power-down mode 40 kΩ DIGITAL INPUTS (DIN, SCLK, CS) Input High Voltage V IH 0.7 x DVDDO V Input Low Voltage V IL 0.3 x DVDDO V Input Hysteresis V HYST 0.2 V Input Leakage Current I IN VIN = 0 to DVDDO -10 +10 µA Input Capacitance C IN 10 pF DIGITAL OUTPUTS (DOUT, SSTRB) DVDDO = 4.75V, ISINK = 10mA 0.4Output Low Voltage V OL DVDDO = 2.7V, ISINK = 5mA 0.4 V Output High Voltage V OH ISOURCE = 0.5mA DVDDO - 0.4 V DOUT Tri-State Leakage Current IDDO CS = DVDDO -10 +10 µA POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO) Analog Supply Voltage AV DD1 4.75 5.25 V Digital Supply Voltage DV DD 4.75 5.25 V ELECTRICAL CHARACTERISTICS (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Preamplifier Supply Voltage AV DD2 4.75 5.25 V Digital I/O Supply Voltage DV DDO 2.70 5.25 V Internal reference 3 3.5 AVDD1 Supply Current I AVDD1 External clock mode, external acquisition mode, or internal clock mode External reference 2.5 3 mA DVDD Supply Current I DVDD External clock mode, external acquisition mode, or internal clock mode 0.9 2 mA AVDD2 Supply Current I AVDD2 External clock mode, external acquisition mode, or internal clock mode 17.5 25 mA DVDDO Supply Current IDVDDO External clock mode, external acquisition mode, or internal clock mode 0.2 1 mA Partial power-down mode 1.3 mATotal Supply Current Full power-down mode 1 µA Power-Supply Rejection Ratio PSRR All analog input ranges ±0.125 LSB TIMING CHARACTERISTICS (Figures 15 and 16) External clock mode 272 62 External acquisition mode 228 62SCLK Period t CP Internal clock mode 100 83 µs External clock mode 109 External acquisition mode 92SCLK High Pulse Width (Note 5) tCH Internal clock mode 40 ns External clock mode 109 External acquisition mode 92SCLK Low Pulse Width (Note 5) t CL Internal clock mode 40 ns DIN to SCLK Setup t DS 40 ns DIN to SCLK Hold t DH 0n s SCLK Fall to DOUT Valid t DO 40 ns CS Fall to DOUT Enable t DV 40 ns CS Rise to DOUT Disable t TR 40 ns CS Fall to SCLK Rise Setup t CSS 40 ns CS High Minimum Pulse Width t CSPW 40 ns SCLK Fall to CS Rise Hold t CSH 0n s SSTRB Rise to CS Fall Setup 40 ns DOUT Rise/Fall Time C L = 50pF 10 ns SSTRB Rise/Fall Time C L = 50pF 10 ns ELECTRICAL CHARACTERISTICS (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs Note 1: Parameter tested at AVDD1 = AVDD2 = DVDD = DVDDO = 5V. Note 2: See definitions in the Parameter Definitions section at the end of the data sheet. Note 3: Guaranteed by correlation with single-ended measurements. Note 4: To ensure external reference operation, VREFCAP must exceed (AVDD1 - 0.1V). To ensure internal reference operation, VREFCAP sition point between internal reference mode and external reference mode lies between the REFCAP buffer disable threshold minimum and maximum values (Figures 17 and 18). Note 5: The SCLK duty cycle can vary between 40% and 60%, as long as the tCL and tCH timing requirements are met. ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1034/35 toc01 AVDD1 (V) IAVDD1 (mA) 5.155.054.954.85 2.35 2.40 2.45 2.50 2.55 2.60 2.30 4.75 5.25 TA = +85°C TA = +25°C TA = -40°C EXTERNAL CLOCK MODE PREAMPLIFIER SUPPLY CURRENT vs. PREAMPLIFIER SUPPLY VOLTAGE MAX1034/35 toc02 AVDD2 (V) IAVDD2 (mA) 5.155.054.85 4.95 4.75 5.25 TA = +85°C TA = +25°C TA = -40°C EXTERNAL CLOCK MODE DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX1034/35 toc03 DVDD (V) IDVDD (mA) 5.155.054.954.85 0.70 0.75 0.80 0.85 0.90 0.65 4.75 5.25 TA = +85°C TA = +25°C TA = -40°C EXTERNAL CLOCK MODE Typical Operating Characteristics (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f CLK = 3.5MHz (50% duty cycle), external clock mode, V REF = 4.096V (external reference operation), REFCAP = AV DD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.) ELECTRICAL CHARACTERISTICS (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs DIGITAL I/O SUPPLY CURRENT vs. DIGITAL I/O SUPPLY VOLTAGE MAX1034/35 toc04 DVDDO (V) IDVDDO (mA) 5.155.054.85 4.95 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.10 4.75 5.25 TA = +85°C TA = +25°C TA = -40°C EXTERNAL CLOCK MODE ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1034/35 toc05 AVDD1 (V) IAVDD1 (mA) 5.155.054.954.85 0.47 0.49 0.51 0.53 0.55 0.45 4.75 5.25 TA = +85°C TA = +25°C TA = -40°C PARTIAL POWER-DOWN MODE PREAMPLIFIER SUPPLY CURRENT vs. PREAMPLIFIER SUPPLY VOLTAGE MAX1034/35 toc06 AVDD2 (V) IAVDD2 (mA) 5.155.054.954.85 0.12 0.14 0.16 0.18 0.20 0.10 4.75 5.25 TA = +85°C TA = +25°C TA = -40°C PARTIAL POWER-DOWN MODE DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX1034/35 toc07 DVDD (V) IDVDD (mA) 5.154.85 5.054.95 0.122 0.124 0.126 0.128 0.130 0.132 0.134 0.136 0.120 4.75 5.25 PARTIAL POWER-DOWN MODE TA = +85°C TA = +25°C TA = -40°C Typical Operating Characteristics (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f CLK = 3.5MHz (50% duty cycle), external clock mode, V REF = 4.096V (external reference operation), REFCAP = AV DD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs ANALOG SUPPLY CURRENT vs. CONVERSION RATE MAX1034/35 toc08 CONVERSION RATE (ksps) IAVDD1 (mA) 20015010050 0.5 1.0 1.5 2.0 2.5 3.0 EXTERNAL CLOCK MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE PREAMPLIFIER SUPPLY CURRENT vs. CONVERSION RATE MAX1034/35 toc09 IAVDD2 (mA) CONVERSION RATE (ksps) 200150100500 fCLK = 7.5MHz (NOTE 6) EXTERNAL CLOCK MODE FULL POWER-DOWN MODE, PARTIAL POWER-DOWN MODE DIGITAL SUPPLY CURRENT vs. CONVERSION RATE MAX1034/35 toc10 IDVDD (mA) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 CONVERSION RATE (ksps) 20015010050 fCLK = 7.5MHz (NOTE 6) FULL POWER-DOWN MODE EXTERNAL CLOCK MODE, PARTIAL POWER-DOWN MODE DIGITAL I/O SUPPLY CURRENT vs. CONVERSION RATE MAX1034/35 toc11 CONVERSION RATE (ksps) IDVDDO (mA) 20015010050 0.1 0.2 0.3 0.4 0.5 0.6 fCLK = 7.5MHz (NOTE 6) EXTERNAL CLOCK MODE FULL POWER-DOWN MODE, PARTIAL POWER-DOWN MODE Note 6: For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples. Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down or full power-down modes. Typical Operating Characteristics (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f CLK = 3.5MHz (50% duty cycle), external clock mode, V REF = 4.096V (external reference operation), REFCAP = AV DD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs EXTERNAL REFERENCE INPUT CURRENT vs. EXTERNAL REFERENCE INPUT VOLTAGE MAX1034/35 toc12 EXTERNAL REFERENCE VOLTAGE (V) EXTERNAL REFERENCE CURRENT (mA) 0.13 0.14 0.15 0.16 0.12 3.80 4.15 ALL MODES -0.10 -0.04 -0.06 -0.08 -0.02 0.02 0.04 0.06 0.08 0.10 -40 10 -15 35 60 85 GAIN DRIFT vs. TEMPERATURE MAX1034/35 toc13 TEMPERATURE (°C) GAIN DRIFT (%) +VREF/2 BIPOLAR ±VREF BIPOLAR RANGE ±VREF/4 BIPOLAR -1.0 -0.4 -0.6 -0.8 -0.2 0.2 0.4 0.6 0.8 1.0 -40 10 -15 35 60 85 OFFSET DRIFT vs. TEMPERATURE MAX1034/35 toc14 TEMPERATURE (°C) OFFSET ERROR (mV) +VREF/4 BIPOLAR RANGE ±VREF BIPOLAR CHANNEL-TO-CHANNEL ISOLATION vs. INPUT FREQUENCY MAX1034/35 toc15 FREQUENCY (kHz) ISOLATION (dB) 100010010 -100 -80 -60 -40 -20 -120 1 10,000 fSAMPLE = 115ksps ±VREF BIPOLAR RANGE CH0 TO CH2 COMMON-MODE REJECTION RATIO vs. FREQUENCY MAX1034/35 toc16 FREQUENCY (kHz) CMRR (dB) 100010010 -90 -80 -70 -60 -50 -40 -30 -20 -10 -100 1 10,000 fSAMPLE = 115ksps ±VREF BIPOLAR RANGE 1.0 0.5 -0.5 -1.0 0 81924096 12,288 16,383 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1034/35 toc17 DIGITAL OUTPUT CODE INL (LSB) fSAMPLE = 115ksps ±VREF BIPOLAR RANGE 1.0 0.5 -0.5 -1.0 0 81924096 12,288 16,383 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1034/35 toc18 DIGITAL OUTPUT CODE DNL (LSB) fSAMPLE = 115ksps ±VREF BIPOLAR RANGE -140 -100 -120 -60 -80 -20 -40 02 0 3 010 40 50 FFT AT 5kHz MAX1034/35 toc19 FREQUENCY (kHz) MAGNITUDE (dB) fSAMPLE = 115ksps fIN(SINE WAVE) = 5kHz ±VREF BIPOLAR RANGE Typical Operating Characteristics (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f CLK = 3.5MHz (50% duty cycle), external clock mode, V REF = 4.096V (external reference operation), REFCAP = AV DD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs SNR, SINAD, ENOB vs. ANALOG INPUT FREQUENCY MAX1034/35 toc20 FREQUENCY (kHz) SNR, SINAD (dB) 10010 100 1 1000 ENOB (BITS) fSAMPLE = 115ksps ±VREF BIPOLAR RANGE SNR SINAD ENOB Typical Operating Characteristics (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f CLK = 3.5MHz (50% duty cycle), external clock mode, V REF = 4.096V (external reference operation), REFCAP = AV DD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.) SNR, SINAD, ENOB vs. SAMPLE RATE MAX1034/35 toc21 SAMPLE RATE (ksps) SNR, SINAD (dB) 100101 100 0.1 1000 ENOB SNR, SINAD fIN(SINE WAVE) = 5kHz ±VREF BIPOLAR RANGE ENOB (BITS) -SFDR, THD vs. SAMPLE RATE MAX1034/35 toc22 SAMPLE RATE (ksps) -SFDR, THD (dB) 100101 -100 -80 -60 -40 -20 -120 0.1 1000 fIN(SINE WAVE) = 5kHz ±VREF BIPOLAR RANGE THD -SFDR -SFDR, THD vs. ANALOG INPUT FREQUENCY MAX1034/35 toc23 FREQUENCY (kHz) -SFDR, THD (dB) 10010 -100 -80 -60 -40 -20 -120 1 1000 fSAMPLE = 115ksps ±VREF BIPOLAR RANGE THD -SFDR ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE MAX1034/35 toc24 ANALOG INPUT VOLTAGE (V) ANALOG INPUT CURRENT (mA) 420-2-4 -0.5 -1.0 0.5 1.0 1.5 -1.5 -6 6 ALL MODES

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs SMALL-SIGNAL BANDWIDTH MAX1034/35 toc25 FREQUENCY (kHz) ATTENUATION (dB) 100010010 -25 -20 -15 -10 -30 1 10,000 REFERENCE VOLTAGE vs. TIME MAX1034/35 toc27 1V/div 4ms/div Typical Operating Characteristics (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f CLK = 3.5MHz (50% duty cycle), external clock mode, V REF = 4.096V (external reference operation), REFCAP = AV DD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.) FULL-POWER BANDWIDTH MAX1034/35 toc26 FREQUENCY (kHz) ATTENUATION (dB) 100010010 -50 -40 -30 -20 -10 -60 1 10,000 10,000 5000 20,000 15,000 35,000 30,000 25,000 40,000 81918190 8192 8193 8194 8195 NOISE HISTOGRAM (CODE EDGE) MAX1034/35 toc28 CODE NUMBER OF HITS 65,534 SAMPLES 10,000 30,000 20,000 60,000 50,000 40,000 70,000 81918190 8192 8193 8194 NOISE HISTOGRAM (CODE CENTER) MAX1034/35 toc29 CODE NUMBER OF HITS 65,534 SAMPLES

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs Pin Description PIN MAX1034 MAX1035 NAME FUNCTION

12 A V DD1

Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1 to AGND1 with a 0.1µF capacitor.

23 CH0 Analog Input Channel 0

34 CH1 Analog Input Channel 1

45 CH2 Analog Input Channel 2

56 CH3 Analog Input Channel 3

6— CH4 Analog Input Channel 4 7— CH5 Analog Input Channel 5 8— CH6 Analog Input Channel 6 9— CH7 Analog Input Channel 7 10 7 CS Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK. When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance. 11 8 DIN Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is high, transitions on DIN are ignored. 12 9 SSTRB Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that data is ready to be read from the device. When operating in external clock mode, SSTRB is always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires a dedicated I/O line. 13 10 SCLK Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT. When CS is high, transitions on SCLK are ignored. 14 11 DOUT Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK transition. When CS is high, DOUT is high impedance. 15 12 DGNDO D i gi tal I/O Gr ound . D GND , DGN D O, AGN D 3, AGND 2, and AGN D1 m ust be connected tog ether. 16 13 DGND Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. 17 14 DV DDO Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage. Bypass DVDDO to DGNDO with a 0.1µF capacitor. 18 15 DV DD Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage. Bypass DVDD to DGND with a 0.1µF capacitor. 19 16 REFCAP Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD. For internal reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1 (VREFCAP ≈ 4.096V). 20 17 REF Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an external reference voltage from 3.800V to 4.136V to REF. For internal reference operation, bypassing REF with a 1µF capacitor to AGND1 sets VREF = 4.096V ±1%.

MICROWIRE-compatible serial interface. AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD2 to AGND2 with a 0.1µF capacitor. 23 20 AGND2 Analog Ground 2. This ground carries approximately five times more current than AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. 24 1 AGND1 Anal og Gr ound 1. D GN D , D GN DO, AGN D 3, AGN D 2, and AGND 1 must b e connected together . Figure 1. Typical Application Circuit

DD1, AV DD2, DVDD, and DVDDO supplies. capacitor in parallel with the 0.1µF bypass capacitor. with programmable unipolar and bipolar signal ranges. with varying input voltage (Figure 5). Table 1. MAX1034/MAX1035 Power Supplies and Bypassing Table 2. Analog Input Configuration Byte 7 START Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte. Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).

3 DIF/SGL

Table 4. In differential mode, the input voltages are measured between two input channels, as shown in Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6. Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.

REF / 2, FSR = VREF, and FSR = 2 x VREF, respectively. voltage ranges that support the entire FSR. Table 3. Input Data Word Formats Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0) Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)

control the power modes of the MAX1034/MAX1035.

• External Clock Mode, Mode 0 (Figure 2)
• Highest maximum throughput (see the Electrical Characteristicstable)
• User controls the sample instant
• CS remains low during the conversion
• User supplies SCLK throughout the ADC con- version and reads data at DOUT
• External Acquisition Mode, Mode 1 (Figure 3)
• Lowest maximum throughput (see the Electrical Characteristics table)
• User controls the sample instant
• User supplies two bytes of SCLK, then drives CS high to relieve processor load while the ADC converts
• After SSTRB transitions high, the user supplies two bytes of SCLK and reads data at DOUT
• Internal Clock Mode, Mode 2 (Figure 4)
• High maximum throughput (see the Electrical Characteristics table)
• The internal clock controls the sampling instant 8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs

1 LSB = FSR x VREF

Figure 13. Ideal Unipolar Transfer Function, Single-Ended Figure 14. Ideal Unipolar Transfer Function, Single-Ended Figure 12. Ideal Bipolar Transfer Function, Single-Ended or

falling edge of the 16th clock cycle as shown in Figure 3. falling edge of the 11th internal clock signal (Figure 4). low on the rising SCLK edge of the subsequent start bit. conversions using external clock mode (mode 0).

• External-Clock-Mode Control Byte
• External-Acquisition-Mode Control Byte
• Internal-Clock-Mode Control Byte
• Reset Byte
• Full Power-Down-Mode Control Byte This prevents the MAX1034/MAX1035 from inadvertent- ly exiting partial power-down mode because of a CS glitch in a noisy digital environment. Full Power-Down Mode (Mode 7) When M[2:0] = 111, the device enters full power-down mode and the total supply current falls to 1µA (typ). In full power-down, all analog portions of the device are powered down. When using the internal reference, upon exiting full power-down mode, allow 10ms for the internal reference voltage to stabilize prior to initiating a conversion. To exit full power-down, change the mode by issuing one of the following mode-control bytes (see the Mode Control section):
• External-Clock-Mode Control Byte
• External-Acquisition-Mode Control Byte 8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs M2 M1 M0 MODE 00 0 External Clock (DEFAULT) 00 1 External Acquisition 01 0 Internal Clock 01 1 Reserved 10 0 Reset 10 1 Reserved 11 0 Partial Power-Down 11 1 Full Power-Down

Table 8. Mode-Control Bits M[2:0]

-FSR to 0V When a zero-scale analog input voltage is applied to the converter inputs, the digital output is all ones (0x3FFF). Ideally, the transition from 0x3FFF to 0x3FFE occurs at AGND1 - 0.5 LSB. Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. 0V to +FSR When a zero-scale analog input voltage is applied to the converter inputs, the digital output is all zeros (0x0000). Ideally, the transition from 0x0000 to 0x0001 occurs at AGND1 + 0.5 LSB. Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. Bipolar Offset Error When a zero-scale analog input voltage is applied to the converter inputs, the digital output is a one followed by all zeros (0x2000). Ideally, the transition from 0x1FFF to 0x2000 occurs at (2 N-1 - 0.5) LSB. Bipolar off- set error is the amount of deviation between the mea- sured midscale transition point and the ideal midscale transition point, with untested channels grounded. Gain Error When a positive full-scale voltage is applied to the con- verter inputs, the digital output is all ones (0x3FFF). The transition from 0x3FFE to 0x3FFF occurs at 1.5 LSB below full scale. Gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point with the offset error removed and all untested channels grounded. Unipolar Endpoint Overlap Unipolar endpoint overlap is the change in offset when switching between complementary input voltage ranges. For example, the difference between the volt- age that results in a 0x3FFF output in the -V REF/2 to 0V input voltage range and the voltage that results in a 0x0000 output in the 0 to +V REF/2 input voltage range is the unipolar endpoint overlap. The unipolar endpoint overlap is positive for the MAX1034/MAX1035, prevent- ing loss of signal or a dead zone when switching between adjacent analog input voltage ranges. Small-Signal Bandwidth A 100mV P-P sine wave is applied to the ADC, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Full-Power Bandwidth A 95% of full-scale sine wave is applied to the ADC, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Common-Mode Rejection Ratio (CMRR) CMRR is the ability of a device to reject a signal that is “common” to or applied to both input terminals. The common-mode signal can be either an AC or a DC sig- nal or a combination of the two. CMR is expressed in decibels. Common-mode rejection ratio is the ratio of the differential signal gain to the common-mode signal gain. CMRR applies only to differential operation. Power-Supply Rejection Ratio (PSRR) PSRR is the ratio of the output-voltage shift to the power-supply-voltage shift for a fixed input voltage. For the MAX1034/MAX1035, AV DD1 can vary from 4.75V to 5.25V. PSRR is expressed in decibels and is calculated using the following equation: For the MAX1034/MAX1035, PSRR is tested in bipolar operation with the analog inputs grounded. Aperture Jitter Aperture jitter, t AJ, is the statistical distribution of the variation in the sampling instant (Figure 21). Aperture Delay Aperture delay, tAD, is the time from the falling edge of SCLK to the sampling instant (Figure 21). Signal-to-Noise Ratio (SNR) SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral com- ponents to the Nyquist frequency excluding the funda- mental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS sig- nal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. SINAD dB Signal Noise RMS RMS () log=×  20 PSRR dB VV VV VVOUT OUT [] log . . (. ) (. ) 20 52 5 47 5 52 5 47 5 8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs

next-largest spectral component. Figure 21. Aperture Diagram

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs Chip Information TRANSISTOR COUNT: 28,210 PROCESS: BiCMOS Block Diagram MAX1034 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1 ANALOG INPUT MUX AND MULTIRANGE CIRCUITRY PGA AGND2 AVDD2 4.096V BANDGAP REFERENCE 5kΩ IN REF REFCAP REF CONTROL LOGIC AND REGISTERS FIFO CLOCK OUTSAR ADC SERIAL I/O AGND2 AVDD2 AGND3 AVDD1 DGND DVDD DGNDO SCLK DOUT SSTRB DIN CS DV DDO Pin Configurations (continued) AGND2 AV DD2 AGND3 REFCH1 CH0 AVDD1 AGND1 REFCAP DVDD DVDDO DGNDDIN CS CH3 CH2 DGNDO DOUTSCLK SSTRB MAX1035 TSSOP TOP VIEW

8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation go to www.maxim-ic.com/packages.) TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 1 G