MAX1028BEEP

MAX1026_11 MAXIM | Alldatasheet

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Technical content

Features

o Internal Temperature Sensor (±0.7°C Accuracy) o 16-Entry First-In/First-Out (FIFO) o Analog Multiplexer with True Differential Track/Hold 16-, 12-, 8-Channel Single Ended 8-, 6-, 4-Channel True Differential (Unipolar or Bipolar) o Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing Codes Over Temperature o Scan Mode, Internal Averaging, and Internal Clock o Low-Power Single +5V Operation 2.3mA at 300ksps o Internal 4.096V Reference or External Differential Reference o 10MHz 3-Wire SPI/QSPI/MICROWIRE-Compatible Interface o Space-Saving 28-Pin 5mm x 5mm TQFN Package MAX1026/MAX1028/MAX1030 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Pin Configurations 19-2853; Rev 4; 4/11 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. EVALUATION KIT AVAILABLE

Ordering Information

Ordering Information continued at end of data sheet. AutoShutdown is a trademark of Maxim Integrated Products, Inc. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. AIN0 EOC DOUT DIN CS SCLK VDD GND REF+ MAX1026 QSOP AIN1 AIN2 AIN5 AIN3 AIN4 REF-/AIN6 CNVST/AIN7 EOC DOUT DIN CSAIN3 AIN2 AIN1 AIN0 SCLK V DD GND REF+AIN7 AIN6 AIN5 AIN4 CNVST/AIN11 REF-/AIN10AIN9 AIN8 MAX1028 QSOP +TOP VIEW PART TEMP RANGE PIN-PACKAGE MAX1026BCEE+T 0°C to +70°C 16 QSOP MAX1026BEEE+T -40°C to +85°C 16 QSOP MAX1028BCEP+T 0°C to +70°C 20 QSOP MAX1028BEEP+T -40°C to +85°C 20 QSOP Pin Configurations continued at end of data sheet. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = +5V ±5%, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), V REF = 4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AIN0–AIN13, REF-/AIN_, CNVST/AIN_, Continuous Power Dissipation (T A = +70°C) 28-Pin TQFN 5mm x 5mm Operating Temperature Ranges PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution RES 10 Bits Integral Nonlinearity INL ±1.0 LSB Differential Nonlinearity DNL No missing codes over temperature ±1.0 LSB Offset Error ±0.5 ±2.0 LSB Gain Error (Note 2) ±0.5 ±2.0 LSB Offset Error Temperature Coefficient ±2 ppm/°C FSR Gain Temperature Coefficient ±0.8 ppm/°C Channel-to-Channel Offset Matching ±0.1 LSB DYNAMIC SPECIFICATIONS (30kHz sine wave input, 4.096VP-P, 300ksps, fSCLK = 4.8MHz) Signal-to-Noise Plus Distortion SINAD 61 dB Total Harmonic Distortion THD Up to the 5th harmonic -88 dBc Spurious-Free Dynamic Range SFDR 89 dBc Intermodulation Distortion IMD f IN1 = 29.9kHz, fIN2 = 30.2kHz 76 dBc Full-Power Bandwidth -3dB point 1 MHz Full-Linear Bandwidth S/(N + D) > 68dB 100 kHz

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±5%, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), V REF = 4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE External reference 0.8Power-Up Time t PU Internal reference (Note 3) 65 μs Acquisition Time t ACQ 0.6 μs Internally clocked 3.5Conversion Time t CONV Externally clocked (Note 4) 2.7 μs Externally clocked conversion 0.1 4.8External Clock Frequency f SCLK Data I/O 10 MHz Aperture Delay 30 ns Aperture Jitter <50 ps ANALOG INPUT Unipolar 0 V REFInput Voltage Range Bipolar (Note 5) - V RE F /2 V RE F /2 V Input Leakage Current V IN = VDD ±0.01 ±1 μA Input Capacitance During acquisition time (Note 6) 24 pF INTERNAL TEMPERATURE SENSOR Grade B, TA = +25°C ±0.7Measurement Error (Note 7) Grade B, TA = TMIN to TMAX ±1.2 ±3.0 °C Tem p er atur e M easur em ent N oi se 0.1 °C RMS Temperature Resolution 1/8 °C Power-Supply Rejection 0.3 °C/V INTERNAL REFERENCE REF Output Voltage 4.024 4.096 4.168 V REF Temperature Coefficient TC REF Grade B ±20 p p m /° C Output Resistance 6.5 k _ REF Output Noise 200 μV RMS REF Power-Supply Rejection PSRR -70 dB EXTERNAL REFERENCE INPUT REF- Input Voltage Range V REF- 0 500 mV REF+ Input Voltage Range V REF+ 1.0 V DD + 50mV V VREF+ = 4.096V, fSAMPLE = 300ksps 40 100REF+ Input Current I REF+ VREF+ = 4.096V, fSAMPLE = 0 ±0.1 ±5 μA

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Note 1: Tested at VDD = +5V, unipolar input mode. Note 2: Offset nulled. Note 3: Time for reference to power up and settle to within 1 LSB. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 5: The operational input voltage range for each individual input of a differentially configured pair is from GND to VDD. The oper- ational input voltage difference is from -VREF / 2 to +VREF / 2. Note 6: See Figure 3 (Input Equivalent Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating Characteristics section. Note 7: Fast automated test, excludes self-heating effects. Note 8: When CNVST is configured as a digital input, do not apply a voltage beween VIL and VIH. Note 9: Supply current is specified depending on whether an internal or external reference is used for voltage conversions. Temperature measurements always use the internal reference. ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±5%, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), V REF = 4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, CNVST)(Note 8) Input Voltage Low V IL 0.8 V Input Voltage High V IH 2.0 V Input Hysteresis V HYST 200 mV Input Leakage Current I IN VIN = 0V or VDD ±0.01 ±1.0 μA Input Capacitance C IN 15 pF DIGITAL OUTPUTS (DOUT, EOC) ISINK = 2mA 0.4Output Voltage Low V OL ISINK = 4mA 0.8 V Output Voltage High V OH ISOURCE = 1.5mA V DD - 0.5 V Three-State Leakage Current I L CS = VDD ±0.05 ±1 μA Three-State Output Capacitance C OUT CS = VDD 15 pF POWER REQUIREMENTS Supply Voltage V DD 4.75 5.25 V During temp sense 2800 3200 fSAMPLE = 300ksps 2300 2550 fSAMPLE = 0, REF on 1050 1350 Internal reference Shutdown 0.2 5 During temp sense 1800 2300 fSAMPLE = 300ksps 1600 1700 Supply Current (Note 9) I DD External reference Shutdown 0.2 5 μA Power-Supply Rejection PSR V DD = 4.75V to 5.25V; full-scale input ±0.2 ±1.4 mV

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Note 10: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal reference needs to be powered up, the total time is additive. The internal reference is always used for temperature mea surements. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Externally clocked conversion 208SCLK Clock Period t CP Data I/O 100 ns SCLK Duty Cycle t CH 40 60 % SCLK Fall to DOUT Transition t DOT CLOAD = 30pF 40 ns CS Rise to DOUT Disable t DOD CLOAD = 30pF 40 ns CS Fall to DOUT Enable t DOE CLOAD = 30pF 40 ns DIN to SCLK Rise Setup t DS 40 ns SCLK Rise to DIN Hold t DH 0n s C S Fal l to S C LK Ri se S etup Ti m et CSS0 40 ns CS Fall to SCLK Rise Hold Time t CSH0 0n s CS Rise to SCLK Rise Hold Time t CSH 0n s CS Rise to SCLK Rise Setup Time t CSS1 0n s tCSW CKSEL = 00, CKSEL = 01 (temp sense) 40 nsCNVST Pulse Width CKSEL = 01 (voltage conversion) 1.4 μs t T S Temp sense 55 Voltage conversion 7CS or CNVST Rise to EOC Low (Note 10) t R P Reference power-up 65 μs TIMING CHARACTERISTICS (Figure 1) -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0 256 512 768 1024 INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX1026/28/30 toc01 OUTPUT CODE INTEGRAL NONLINEARITY (LSB) -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0 256 512 768 1024 DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX1026/28/30 toc02 OUTPUT CODE DIFFERENTIAL NONLINEARITY (LSB) SINAD vs. FREQUENCY MAX1026/28/30 toc03 FREQUENCY (kHz) SINAD AMPLITUDE (dB) 100101 100 0.1 1000 Typical Operating Characteristics (VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.)

4.0494 4.0496 4.0495 4.0498 4.0497 4.0499 4.0500 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX1026/28/30 toc10 SUPPLY VOLTAGE (V) INTERNAL REFERENCE VOLTAGE (V) MAX1026/MAX1028/MAX1030 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference SFDR vs. FREQUENCY MAX1026/28/30 toc04 FREQUENCY (kHz) SFDR AMPLITUDE (dB) 100101 100 120 0.1 1000 SUPPLY CURRENT vs. SAMPLING RATE MAX1026/28/30 toc05 SAMPLING RATE (ksps) SUPPLY CURRENT (μA) 10010 400 600 800 1000 1200 200 1 1000 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1026/28/30 toc06 SUPPLY VOLTAGE (V) SUPPLY CURRENT (μA) 5.155.054.954.85 1050 1100 1150 1200 1000 4.75 5.25 0.2 0.1 0.4 0.3 0.5 0.6 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1026/28/30 toc07 SUPPLY VOLTAGE (V) SHUTDOWN SUPPLY CURRENT (μA) SUPPLY CURRENT vs. TEMPERATURE MAX1026/28/30 toc08 TEMPERATURE (°C) SUPPLY CURRENT (μA) 603510-15 1050 1100 1150 1200 1250 1300 1000 -40 85 fS = 300ksps 0.2 0.1 0.4 0.3 0.5 0.6 -40 10 -15 35 60 85 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX1026/28/30 toc09 TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT (μA) Typical Operating Characteristics (continued) (VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.)

4.051 4.050 4.049 4.048 4.047 -40 10 -15 35 60 85 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1026/28/30 toc11 TEMPERATURE (°C) INTERNAL REFERENCE VOLTAGE (V) 0.2 0.1 0.4 0.3 0.5 0.6 OFFSET ERROR vs. SUPPLY VOLTAGE MAX1026/28/30 toc12 SUPPLY VOLTAGE (V) OFFSET ERROR (LSB) 0.2 0.1 0.4 0.3 0.5 0.6 -40 10 -15 35 60 85 OFFSET ERROR vs. TEMPERATURE MAX1026/28/30 toc13 TEMPERATURE (°C) OFFSET ERROR (LSB) -1.0 -0.5 0.5 GAIN ERROR vs. SUPPLY VOLTAGE MAX1026/28/30 toc14 SUPPLY VOLTAGE (V) GAIN ERROR (LSB) -1.0 -0.5 0.5 GAIN ERROR vs. TEMPERATURE MAX1026/28/30 toc15 TEMPERATURE (°C) GAIN ERROR (LSB) -40 -15 35 85 6010 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Typical Operating Characteristics (continued) (VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) -1.00 -0.50 0.50 0.25 -0.25 -0.75 1.00 0.75 TEMPERATURE SENSOR ERROR vs. TEMPERATURE MAX1026/28/30 toc16 TEMPERATURE (°C) TEMPERATURE SENSOR ERROR (°C) -40 -15 35 85 6010 GRADE B 04 26 8 1 0 SAMPLING ERROR vs. SOURCE IMPEDANCE MAX1026/28/30 toc17 SOURCE IMPEDANCE (kΩ) SAMPLING ERROR (LSB)

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Pin Description PIN MAX1030 TQFN MAX1030 QSOP MAX1028 MAX1026 NAME FUNCTION 1, 17, 19, 25 — — — N.C. No Connection. Not internally connected. 2–12, 26, 27, 28 1–14 — — AIN0–13 Analog Inputs — — 1–10 — AIN0–9 Analog Inputs — — — 1–6 AIN0–5 Analog Inputs 13 15 — — REF-/AIN14 Negative Input for External Differential Reference/Analog Input 14. See Table 3 for details on programming the setup register. — — 11 — REF-/AIN10 Negative Input for External Differential Reference/Analog Input 10. See Table 3 for details on programming the setup register. — — — 7 REF-/AIN6 Negative Input for External Differential Reference/Analog Input 6. See Table 3 for details on programming the setup register. 14 16 — — CNVST/ AIN15 Active-Low Conversion Start Input/Analog Input 15. See Table 3 for details on programming the setup register. — — 12 — CNVST/ AIN11 Active-Low Conversion Start Input/Analog Input 11. See Table 3 for details on programming the setup register. ——— 8 CNVST/ AIN7 Active-Low Conversion Start Input/Analog Input 7. See Table 3 for details on programming the setup register. 15 17 13 9 REF+ Positive Reference Input. Bypass to GND with a 0.1µF capacitor. 16 18 14 10 GND Ground 18 19 15 11 V DD Power Input. Bypass to GND with a 0.1µF capacitor. 20 20 16 12 SCLK Serial Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%.) See Table 3 for details on programming the clock mode. 21 21 17 13 CS Active-Low Chip-Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance. 22 22 18 14 DIN Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 23 23 19 15 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is connected to V DD. 24 24 20 16 EOC End of Conversion Output. Data is valid after EOC pulls low. — — — — EP Exposed Pad (TQFN Only). Connect EP to GND.

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Converter Operation The MAX1026/MAX1028/MAX1030 ADCs use a fully dif- ferential, successive-approximation register (SAR) con- version technique and an on-chip T/H block to convert temperature and voltage signals into a 10-bit digital result. Both single-ended and differential configurations are supported, with a unipolar signal range for single- ended mode and bipolar or unipolar ranges for differ- ential mode. Input Bandwidth The ADC’s input-tracking circuitry has a 1MHz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias prefiltering of the input signals is necessary to avoid high-frequen- cy signals aliasing into the frequency band of interest. Analog Input Protection Internal ESD protection diodes clamp all pins to V DD and GND, allowing the inputs to swing from (GND - 0.3V) to (V DD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed V DD by more than 50mV or be lower than GND by 50mV. If an off-channel analog input voltage exceeds the supplies, limit the input current to 2mA. 3-Wire Serial Interface The MAX1026/MAX1028/MAX1030 feature a serial interface compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, ensure the CPU serial interface runs in master mode so it generates the serial clock signal. Select the SCLK frequency of 10MHz or less, and set clock polarity (CPOL) and phase (CPHA) in the μP control registers to the same value. The MAX1026/ MAX1028/MAX1030 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. Bipolar true-dif- ferential results and temperature sensor results are available in two’s complement format, while all others are in binary. Serial communication always begins with an 8-bit input data byte (MSB first) loaded from DIN. Send a second byte, immediately following the setup byte, to write to the unipolar mode or bipolar mode registers (see Tables 1, 3, 4, and 5). A high-to-low transition on CS ini- tiates the data input operation. The input data byte and the subsequent data bytes are clocked from DIN into the serial interface on the rising edge of SCLK. Tables 1–7 detail the register descriptions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively, control the clock modes in the setup register (see Table 3). Choose between four different clock modes for various ways to start a conversion and determine whether the acquisi- tions are internally or externally timed. Select clock mode 00 to configure CNVST/AIN_ to act as a conver- sion start and use it to request the programmed inter- nally timed conversions without tying up the serial bus. In clock mode 01, use CNVST to request conversions one channel at a time, controlling the sampling speed without tying up the serial bus. Request and start inter- nally timed conversions through the serial interface by writing to the conversion register in the default clock mode, 10. Use clock mode 11 with SCLK up to 4.8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps. Clock mode 11 disables scanning and averaging. See Figures 4–7 for timing specifica- tions and how to begin a conversion. These devices feature an active-low, end-of-conversion output. EOC goes low when the ADC completes the last-requested operation and is waiting for the next input data byte (for clock modes 00 and 10). For clock mode 01, EOC goes low after the ADC completes each requested operation. EOC goes high when CS or CNVST goes low. EOC is always high in clock mode 11. Single-Ended/Differential Input The MAX1026/MAX1028/MAX1030 use a fully differen- tial ADC for all conversions. The analog inputs can be configured for either differential or single-ended con- versions by writing to the setup register (see Table 3). Single-ended conversions are internally referenced to GND (see Figure 3). In differential mode, the T/H samples the difference between two analog inputs, eliminating common-mode DC offsets and noise. IN+ and IN- are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15. AIN0–AIN7 are available on the MAX1026, MAX1028, and MAX1030. AIN8–AIN11 are only available on the MAX1028 and MAX1030. AIN12–AIN15 are only available on the MAX1030. See Tables 2–5 for more details on configuring the inputs. For the inputs that can be configured as CNVST or an analog input, only one can be used at a time. For the inputs that can be configured as REF- or an analog input, the REF- configuration excludes the analog input.

appropriate bit of the bipolar or unipolar register. mode causes the digital output code to be zero. the transfer function graphs, Figures 8 and 9). external track-and-hold timing, use clock mode 01. explanation of the clock mode conversions. surement, without tying up the serial bus. converting the digital code to a temperature. on timing specifications and starting a conversion. Figure 3. Equivalent Input Circuit

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Applications Information Register Descriptions The MAX1026/MAX1028/MAX1030 communicate between the internal registers and the external circuitry through the SPI/QSPI-compatible serial interface. Table 1 details the registers and the bit names. Tables 2–7 show the various functions within the conversion regis- ter, setup register, averaging register, reset register, unipolar register, and bipolar register. Conversion Time Calculations The conversion time for each scan is based on a num- ber of different factors: conversion time per sample, samples per result, results per scan, if a temperature measurement is requested, and if the external refer- ence is in use. Use the following formula to calculate the total conver- sion time for an internally timed conversion in clock modes 00 and 10 (see the section as applicable): total conversion time = tcnv x navg x nresult + tTS + tRP where: tcnv = tacq(max) + tconv(max) navg = samples per result (amount of averaging) nresult = number of FIFO results requested; determined by number of channels being scanned or by NSCAN1, NSCAN0 t TS = time required for temperature measurement; set to zero if temp measurement is not requested tRP = internal reference wake-up; set to zero if the inter- nal reference is already powered up or if the external reference is being used In clock mode 01, the total conversion time depends on how long CNVST is held low or high, including any time required to turn on the internal reference. Conversion time in externally clocked mode (CKSEL1, CKSEL0 = 11) depends on the SCLK period and how long CS is held high between each set of eight SCLK cycles. Conversion Register Select active analog input channels, scan modes, and a single temperature measurement per scan by writing to the conversion register. Table 2 details channel selection, the four scan modes, and how to request a temperature measurement. Request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01. A conversion is not performed if it is requested on a channel that has been configured as CNVST or REF-. Do not request conversions on channels 8–15 on the MAX1026 and channels 12–15 on the MAX1028. Set CHSEL3:CHSEL0 to the lower channel’s binary value. If the last two channels are configured as a differential pair and one of them has been reconfigured as CNVST or REF-, the pair is ignored. Select scan mode 00 or 01 to return one result per sin- gle-ended channel and one result per differential pair within the requested range, plus one temperature result if selected. Select scan mode 10 to scan a single input channel numerous times, depending on NSCAN1 and NSCAN0 in the averaging register (Table 6). Select scan mode 11 to return only one result from a single channel. REGISTER NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Conversion 1 CHSEL3 CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 TEMP Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0 Averaging 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 NSCAN0 Reset 0 0 0 1 RESET XXX Unipolar mode (setup) UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9* UCH10/11* UCH12/13 UCH14/15 Bipolar mode (setup) BCH0/1 BCH1/2 BCH4/5 BCH6/7 BCH8/9* BCH10/11* BCH12/13 BCH14/15 Table 1. Input Data Byte (MSB First) *Unipolar/bipolar channels 8–15 are only valid on the MAX1028 and MAX1030. **Unipolar/bipolar channels 12–15 are only valid on the MAX1030.

and REFSEL0) control internal or external reference use. the analog input channels for differential operation. unipolar and bipolar mode registers. output format in bipolar mode is two's complement. requested for single-channel scans. multiple times. Clock mode 11 disables averaging. the FIFO or to reset all registers to their default states. to the default power-up state. — 7 (MSB) Set to 1 to select conversion register. CHSEL3 6 Analog input channel select. CHSEL2 5 Analog input channel select. CHSEL1 4 Analog input channel select. CHSEL0 3 Analog input channel select. of a scan contains temperature information. Table 2. Conversion Register* 0 0 Scans channels 0 through N.

01 Scans channels N through the highest

r eg i ster sets the num b er of r esul ts. 1 1 No scan. Converts channel N once only.

Table 3. Setup Register* — 7 (MSB) Set to zero to select setup register. — 6 Set to 1 to select setup register. CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference mode configuration. REFSEL0 2 Reference mode configuration. DIFFSEL1 1 Unipolar/bipolar mode register configuration for differential mode. DIFFSEL0 0 (LSB) Unipolar/bipolar mode register configuration for differential mode. 0 0 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged. 0 1 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged. 1 0 One byte of data follows the setup byte and is written to the unipolar mode register. 1 1 One byte of data follows the setup byte and is written to the bipolar mode register.

ter, which powers up in clock mode 10 (CKSEL1 = 1). code minus an offset to adjust from Kelvin to Celsius. to ensure a resolution of 1/8 of a degree. complement for bipolar mode. UCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for unipolar differential conversion. UCH2/3 6 Set to 1 to configure AIN2 and AIN3 for unipolar differential conversion. UCH4/5 5 Set to 1 to configure AIN4 and AIN5 for unipolar differential conversion. UCH6/7 4 Set to 1 to configure AIN6 and AIN7 for unipolar differential conversion. UCH8/9 3 Set to 1 to configure AIN8 and AIN9 for unipolar differential conversion (MAX1028/MAX1030 only). UCH10/11 2 Set to 1 to configure AIN10 and AIN11 for unipolar differential conversion (MAX1028/MAX1030 only). UCH12/13 1 Set to 1 to configure AIN12 and AIN13 for unipolar differential conversion (MAX1030 only). UCH14/15 0 (LSB) Set to 1 to configure AIN14 and AIN15 for unipolar differential conversion (MAX1030 only). Table 4. Unipolar Mode Register (Addressed Through Setup Register) BCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for bipolar differential conversion. BCH2/3 6 Set to 1 to configure AIN2 and AIN3 for bipolar differential conversion. BCH4/5 5 Set to 1 to configure AIN4 and AIN5 for bipolar differential conversion. BCH6/7 4 Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion. BCH8/9 3 Set to 1 to configure AIN8 and AIN9 for bipolar differential conversion (MAX1028/MAX1030 only). BCH10/11 2 Set to 1 to configure AIN10 and AIN11 for bipolar differential conversion (MAX1028/MAX1030 only). BCH12/13 1 Set to 1 to configure AIN12 and AIN13 for bipolar differential conversion (MAX1030 only). BCH14/15 0 (LSB) Set to 1 to configure AIN14 and AIN15 for bipolar differential conversion (MAX1030 only). Table 5. Bipolar Mode Register (Addressed Through Setup Register)

— 7 (MSB) Set to zero to select averaging register. — 6 Set to zero to select averaging register. — 5 Set to 1 to select averaging register. AVGON 4 Set to 1 to turn averaging on. Set to zero to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans. NAVG0 2 Configures the number of conversions for single-channel scans. Table 6. Averaging Register* 0 x x Performs 1 conversion for each requested result. 1 0 0 Performs 4 conversions and returns the average for each requested result. 1 0 1 Performs 8 conversions and returns the average for each requested result. 1 1 0 Performs 16 conversions and returns the average for each requested result. 1 1 1 Performs 32 conversions and returns the average for each requested result. 0 0 Scans channel N and returns 4 results. 0 1 Scans channel N and returns 8 results. 1 0 Scans channel N and returns 12 results. 1 1 Scans channel N and returns 16 results. — 7 (MSB) Set to zero to select reset register. — 6 Set to zero to select reset register. — 5 Set to zero to select reset register. — 4 Set to 1 to select reset register. RESET 3 Set to zero to reset all registers. Set to 1 to clear the FIFO only. x 0 (LSB) Reserved. Don’t care. Table 7. Reset Register

out later. See Figure 4 for clock mode 00 timing. pulling CS low to communicate with the serial interface. cedes all other FIFO results. otherwise, the FIFO can become corrupted. timed. In this case, hold CNVST low for at least 40ns. to be performed before a result is written to the FIFO. once EOC has been pulled low. SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION. X = DON'T CARE. Figure 4. Clock Mode 00

no missing codes and a monotonic transfer function. the time between the samples. tal, the first five harmonics, and the DC offset.

1 LSB = VREF

Figure 9. Bipolar Transfer Function, Full Scale (±FS) = ±VREF / 2 Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF

Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: where V1 is the fundamental amplitude, and V2–V5 are the amplitudes of the first five harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distor- tion component. Chip Information PROCESS: BiCMOS THD 20 x log V V V V / V 2 1= +++ () MAX1026/MAX1028/MAX1030 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE MAX1030BCEG+T 0°C to +70°C 24 QSOP MAX1030BEEG+T -40°C to +85°C 24 QSOP MAX1030BCTI+T 0°C to +70°C 28 TQFN-EP* MAX1030BETI+T -40°C to +85°C 28 TQFN-EP* Pin Configurations (continued) EOC DOUT DIN CSAIN3 AIN2 AIN1 AIN0 SCLK VDD GND REF+AIN7 AIN6 AIN5 AIN4 CNVST/AIN15 REF-/AIN14 AIN13 AIN12AIN11 AIN10 AIN9 AIN8 QSOP MAX1030 AIN3 AIN5 AIN6 AIN7 AIN8 N.C. SCLK VDD N.C. CS GND REF+ N.C. 4567 2021 19 17 16 15 AIN0 AIN1 AIN13 AIN12 AIN11 AIN10 MAX1030AIN4 N.C. 28 8AIN2 AIN9 EOC 23 13 REF-/AIN14DOUT 22 14 CNVST/AIN15DIN TQFN TOP VIEW *EP = Exposed paddle (connect to GND).

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

16 QSOP E16+1 21-0055 90-0167

20 QSOP E20+1 21-0055 90-0168

24 QSOP E24+1 21-0055 90-0172

28 TQFN-EP T2855+6 21-0140 90-0026

10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

3 11/09 Removed the Grade A devices from the Ordering Information table and Electrical Characteristics table. 1, 3, 21 4 4/11 Revised Ordering Information, Electrical Characteristics, Timing Characteristics, Typical Operating Characteristics, Pin Description, Package Information. 1–5, 7, 8, 21