MAX1021

MAX1020 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ 10-Bit, 300ksps ADC Analog Multiplexer with True-Differential Track/Hold (T/H)

16 Single-Ended Channels or 8 Differential

Channels (Unipolar or Bipolar)

12 Single-Ended Channels or 6 Differential

Channels (Unipolar or Bipolar)

8 Single-Ended Channels or 4 Differential

Channels (Unipolar or Bipolar) Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB DNL ♦ 10-Bit, Octal, 2µs Settling DAC Ultra-Low Glitch Energy (4nV•s) Power-Up Options from Zero Scale or Full Scale Excellent Accuracy: ±1 LSB INL ♦ Internal Reference or External Single-Ended/ Differential Reference Internal Reference Voltage 2.5V or 4.096V ♦ Internal ±1°C Accurate Temperature Sensor ♦ On-Chip FIFO Capable of Storing 16 ADC Conversion Results and One Temperature Result ♦ On-Chip Channel-Scan Mode and Internal Data-Averaging Features ♦ Analog Single-Supply Operation +2.7V to +3.6V or +4.75V to +5.25V ♦ 25MHz, SPI/QSPI/MICROWIRE Serial Interface ♦ AutoShutdown Between Conversions ♦ Low-Power ADC 2.5mA at 300ksps 22µA at 1ksps 0.2µA at Shutdown ♦ Low-Power DAC: 1.5µA ♦ Evaluation Kit Available (Order MAX1258EVKIT) MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Ordering Information/Selector Guide 19-3280; Rev 2; 8/04 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. EVALUATION KIT AVAILABLE Pin Configurations appear at end of data sheet. PART TEMP RANGE PIN-PACKAGE REF VOLTAGE (V) ANALOG SUPPLY VOLTAGE (V) RESOLUTION BITS* ADC CHANNELS DAC CHANNELS GPIOs MAX1020BETX -40 °C to +85°C 36 Thin QFN-EP 4.096 4.75 to 5.25 10 8 8 4 MAX1021BETX* -40 °C to +85°C 36 Thin QFN-EP** 2.5 2.7 to 3.6 10 8 8 4 MAX1022BETX* -40 °C to +85°C 36 Thin QFN-EP** 4.096 4.75 to 5.25 10 12 8 0 MAX1023BETX* -40 °C to +85°C 36 Thin QFN-EP 2.5 2.7 to 3.6 10 12 8 0 MAX1057BETM -40 °C to +85°C 48 Thin QFN-EP 2.5 2.7 to 3.6 10 16 8 12 MAX1058BETM -40 °C to +85°C 48 Thin QFN-EP** 4.096 4.75 to 5.25 10 16 8 12 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. AutoShutdown is a trademark of Maxim Integrated Products, Inc. *Future product—contact factory for availability. EP = Exposed pad. *Number of resolution bits refers to both DAC and ADC.

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DV DD + 0.3V) Analog Inputs, Analog Outputs and REF_ Maximum Current into Any Pin (except AGND, DGND, AVDD, Continuous Power Dissipation (TA = +70°C) 36-Pin Thin QFN (6mm x 6mm) 48-Pin Thin QFN (7mm x 7mm) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC DC ACCURACY (Note 1) Resolution 10 Bits Integral Nonlinearity INL ±0.5 ±1.0 LSB Differential Nonlinearity DNL ±0.5 ±1.0 LSB Offset Error ±0.25 ±2.0 LSB Gain Error (Note 2) ±0.025 ±2.0 LSB Gain Temperature Coefficient ±1.4 ppm/°C Channel-to-Channel Offset ±0.1 LSB DYNAMIC SPECIFICATIONS (10kHz sine wave input, VIN = 2.5VP-P (MAX1021/MAX1023/MAX1057), VIN = 4.096VP-P (MAX1020/MAX1022/MAX1058), 300ksps, fSCLK = 4.8MHz) Signal-to-Noise Plus Distortion SINAD 61 dB Total Harmonic Distortion (Up to the Fifth Harmonic) THD -70 dBc Spurious-Free Dynamic Range SFDR 66 dBc Intermodulation Distortion IMD f in1 = 9.9kHz, fin2 = 10.2kHz 72 dBc Full-Linear Bandwidth SINAD > 70dB 100 kHz Full-Power Bandwidth -3dB point 1 MHz CONVERSION RATE (Note 3) External reference 0.8 µs Power-Up Time t PU Internal reference (Note 4) 218 C onver si on C l ock C ycl es Note: If the package power dissipation is not exceeded, one output at a time may be shorted to AV DD, DVDD, AGND, or DGND indefinitely

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Acquisition Time t ACQ (Note 5) 0.6 µs Internally clocked 3.5Conversion Time t CONV Externally clocked 2.7 µs Internal Clock Frequency Internally clocked conversion 4.3 MHz External Clock Frequency f CLK Externally clocked conversion (Note 5) 0.1 4.8 MHz Duty Cycle 40 60 % Aperture Delay 30 ns Aperture Jitter <50 ps ANALOG INPUTS Unipolar 0 V REFInput Voltage Range (Note 6) Bipolar -V REF / 2 V REF / 2 V Input Leakage Current ±0.01 ±1 µA Input Capacitance 24 pF INTERNAL TEMPERATURE SENSOR TA = +25°C ±0.7Measurement Error (Notes 5, 7) TA = TMIN to TMAX ±1.0 ±3.0 °C Temperature Resolution 1/8 °C/LSB INTERNAL REFERENCE MAX1021/MAX1023/MAX1057 2.482 2.50 2.518REF1 Output Voltage (Note 8) MAX1020/MAX1022/MAX1058 4.066 4.096 4.126 V REF1 Voltage Temperature Coefficient TCREF ±30 ppm/°C REF1 Output Impedance 6.5 k Ω VREF = 2.5V 0.39REF1 Short-Circuit Current VREF = 4.096V 0.63 mA EXTERNAL REFERENCE REF1 Input Voltage Range V REF1 REF mode 11 (Note 4) 1 AVDD + 0.05 V REF mode 01 1 AVDD + 0.05REF2 Input Voltage Range (Note 4) V REF2 REF mode 11 0 1 V

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VREF = 2.5V (MAX1021/MAX1023/MAX1057), fSAMPLE = 300ksps 25 80 VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSAMPLE = 300ksps 40 80 REF1 Input Current (Note 9) I REF1 Acquisition between conversions ±0.01 ±1 µA VREF = 2.5V (MAX1021/MAX1023/MAX1057), fSAMPLE = 300ksps 25 80 VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSAMPLE = 300ksps 40 80 REF2 Input Current I REF2 Acquisition between conversions ±0.01 ±1 µA DAC DC ACCURACY (Note 10) Resolution 10 Bits Integral Nonlinearity INL ±0.5 ±1 LSB Differential Nonlinearity DNL Guaranteed monotonic ±0.5 LSB Offset Error V OS (Note 8) ±3 ±10 mV Offset-Error Drift ±10 ppm of FS/°C Gain Error GE (Note 8) ±1.25 ±10 LSB Gain Temperature Coefficient ±8 ppm of FS/°C DAC OUTPUT No load 0.02 AVDD - 0.02 Output-Voltage Range 10kΩ load to either rail 0.1 AVDD - 0.1 V DC Output Impedance 0.5 Ω Capacitive Load (Note 11) 1 nF AVDD = 2.7V, VREF = 2.5V (MAX1021/MAX1023/MAX1057), gain error < 1% 2000 Resistive Load to AGND R L AVDD = 4.75V, VREF = 4.096V (MAX1020/MAX1022/MAX1058), gain error < 2% 500 Ω

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS From power-down mode, AVDD = 5V 25Wake-Up Time (Note 12) From power-down mode, AVDD = 2.7V 21 µs 1kΩ Output Termination Programmed in power-down mode 1 k Ω 100kΩ Output Termination At wake-up or programmed in power-down mode 100 k Ω DYNAMIC PERFORMANCE (Notes 5, 13) Output-Voltage Slew Rate SR Positive and negative 3 V/µs Output-Voltage Settling Time t S To 1 LSB, 400 - C00 hex (Note 7) 2 5 µs Digital Feedthrough Code 0, all digital inputs from 0 to DV DD 0.5 nV •s Major Code Transition Glitch Impulse Between codes 2047 and 2048 4 nV •s From VREF 660Output Noise (0.1Hz to 50MHz) Using internal reference 720 µVP-P From VREF 260Output Noise (0.1Hz to 500kHz) Using internal reference 320 µVP-P DAC-to-DAC Transition Crosstalk 0.5 nV •s INTERNAL REFERENCE MAX1021/MAX1023/MAX1057 2.482 2.50 2.518REF1 Output Voltage (Note 8) MAX1020/MAX1022/MAX1058 4.066 4.096 4.126 V REF1 Temperature Coefficient TC REF ±30 ppm/°C VREF = 2.5V 0.39REF1 Short-Circuit Current VREF = 4.096V 0.63 mA EXTERNAL-REFERENCE INPUT REF1 Input Voltage Range V REF1 REF modes 01, 10, and 11 (Note 4) 0.7 AV DD V REF1 Input Impedance R REF1 70 100 130 k Ω DIGITAL INTERFACE DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC) Input-Voltage High V IH DVDD = 2.7V to 5.25V 2.4 V V Input Leakage Current I L ±0.01 ±10 µA Input Capacitance C IN 15 pF DIGITAL OUTPUT (DOUT) (Note 14) Output-Voltage Low V OL ISINK = 2mA 0.4 V

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output-Voltage High V OH ISOURCE = 2mA DVDD - 0.5 V Tri-State Leakage Current ±10 µA Tri-State Output Capacitance C OUT 15 pF DIGITAL OUTPUT (EOC) (Note 14) Output-Voltage Low V OL ISINK = 2mA 0.4 V Output-Voltage High V OH ISOURCE = 2mA DVDD - 0.5 V Tri-State Leakage Current ±10 µA Tri-State Output Capacitance C OUT 15 pF DIGITAL OUTPUTS (GPIO_) (Note 14) ISINK = 2mA 0.4GPIOB_, GPIOC_ Output- Voltage Low ISINK = 4mA 0.8 V GPIOB_, GPIOC_ Output- Voltage High ISOURCE = 2mA DVDD - 0.5 V GPIOA_ Output-Voltage Low I SINK = 15mA 0.8 V GPIOA_ Output-Voltage High I SOURCE = 15mA DVDD - 0.8 V Tri-State Leakage Current ±10 µA Tri-State Output Capacitance C OUT 15 pF POWER REQUIREMENTS (Note 15) Digital Positive-Supply Voltage DV DD 2.70 AV DD V Idle, all blocks shut down 0.2 4 µA Digital Positive-Supply Current DI DD Only ADC on, external reference 1 mA MAX1021/MAX1023/MAX1057 2.7 3.6Analog Positive-Supply Voltage AV DD MAX1020/MAX1022/MAX1058 4.75 5.25 V Idle, all blocks shut down 0.2 1 µA fSAMPLE = 300ksps 2.8 4.2Only ADC on, external reference fSAMPLE = 100ksps 2.6Analog Positive Supply Current A IDD All DACs on, no load, internal reference 1.5 4.0 mA AVDD = 2.7V MAX1021/MAX1023/MAX1057 -77 REF1 Positive-Supply Rejection PSRR AVDD = 4.75V MAX1020/MAX1022/MAX1058 -80 dB MAX1021/MAX1023/MAX1057 AVDD = 2.7V to 3.6V ±0.1 ±0.5 DAC Positive-Supply Rejection PSRD Output code = FFFhex M AX 1020/M AX 1022/M AX 1058 AV D D = 4.75V to 5.25V ±0.1 ±0.5 mV

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAX1021/MAX1023/ MAX1057 AVDD = 2.7V to 3.6V ±0.06 ±0.5 ADC Positive-Supply Rejection PSRA Full- scale input M AX 1020/M AX 1022/ M AX 1058 AV D D = 4.75V to 5.25V ±0.06 ±0.5 mV TIMING CHARACTERISTICS (Figures 6–13) SCLK Clock Period t CP 40 ns SCLK Pulse-Width High t CH 40/60 duty cycle 16 ns SCLK Pulse-Width Low t CL 60/40 duty cycle 16 ns GPIO Output Rise/Fall After CS Rise tGOD CLOAD = 20pF 100 ns GPIO Input Setup Before CS Fall t GSU 0n s LDAC Pulse Width t LDACPWL 20 ns CLOAD = 20pF, SLOW = 0 1.8 12.0SCLK Fall to DOUT Transition (Note 16) tDOT CLOAD = 20pF, SLOW = 1 10 40 ns CLOAD = 20pF, SLOW = 0 1.8 12.0SCLK Rise to DOUT Transition (Notes 16, 17) tDOT CLOAD = 20pF, SLOW = 1 10 40 ns CS Fall to SCLK Fall Setup Time t CSS 10 ns S C LK Fal l to CS Ri se S etup Ti m et CSH 0n s DIN to SCLK Fall Setup Time t DS 10 ns DIN to SCLK Fall Hold Time t DH 0n s CS Pulse-Width High t CSPWH 50 ns CS Rise to DOUT Disable t DOD CLOAD = 20pF 25 ns CS Fall to DOUT Enable t DOE CLOAD = 20pF 1.5 25.0 ns EOC Fall to CS Fall t RDS 30 ns CKSEL = 01 (temp sense) or CKSEL = 10 (temp sense), internal reference on 55 CKSEL = 01 (temp sense) or CKSEL = 10 (temp sense), internal reference initially off 120 CKSEL = 01 (voltage conversion) 8 CKSEL = 10 (voltage conversion), internal reference on 8 CS or CNVST Rise to EOC Fall t DOV CKSEL = 10 (voltage conversion), internal reference initially off 80 µs CKSEL = 00, CKSEL = 01 (temp sense) 40 nsCNVST Pulse Width t CSW CKSEL = 01 (voltage conversion) 1.4 µs

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.) Note 1: Tested at DVDD = AVDD = +3.6V (MAX1021/MAX1023/MAX1057), DVDD = AVDD = +5.25V (MAX1020/MAX1022/MAX1058). Note 2: Offset nulled. Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the clock period. Note 4: See Table 5 for reference-mode details. Note 5: Not production tested. Guaranteed by design. Note 6: See the ADC/DAC References section. Note 7: Fast automated test, excludes self-heating effects. Note 8: Specified over the -40°C to +85°C temperature range. Note 9: REFSEL[1:0] = 00 or when DACs are not powered up. Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981. Note 11: The DAC buffers are guaranteed by design to be stable with a 500pF load. Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode. Note 13: All DAC dynamic specifications are valid for a load of 1nF and 10kΩ. Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time. Note 15: All digital inputs at either DVDD or DGND. DVDD should not exceed AVDD. Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit. Note 17: Clock mode 11 only. SHUTDOWN CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1020 toc01 SUPPLY VOLTAGE (V) SHUTDOWN CURRENT (µA) 5.155.054.954.85 0.05 0.10 0.15 0.20 0.25 0.30 4.75 5.25 MAX1020/MAX1022/MAX1058 SHUTDOWN CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1020 toc02 SUPPLY VOLTAGE (V) SHUTDOWN CURRENT (µA) 3.33.0 0.12 0.14 0.16 0.18 0.20 0.10 2.7 3.6 MAX1021/MAX1023/MAX1057 SHUTDOWN CURRENT vs. TEMPERATURE MAX1020 toc03 TEMPERATURE (°C) SHUTDOWN CURRENT (µA) 603510-15 0.1 0.2 0.3 0.4 0.5 0.6 -40 85 Typical Operating Characteristics (AVDD = DV DD = 3V (MAX1021/MAX1023/MAX1057), external V REF = 2.5V (MAX1021/MAX1023/MAX1057), AV DD = DV DD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), f SAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports INTERNAL OSCILLATOR FREQUENCY vs. ANALOG SUPPLY VOLTAGE MAX1020 toc04 SUPPLY VOLTAGE (V) INTERNAL OSCILLATOR FREQUENCY (MHz) 5.155.054.954.85 4.1 4.2 4.3 4.4 4.5 4.0 4.75 5.25 MAX1020/MAX1022/MAX1058 INTERNAL OSCILLATOR FREQUENCY vs. ANALOG SUPPLY VOLTAGE MAX1020 toc05 SUPPLY VOLTAGE (V) INTERNAL OSCILLATOR FREQUENCY (MHz) 3.33.0 4.65 4.70 4.75 4.80 4.85 4.90 4.60 2.7 3.6 MAX1021/MAX1023/MAX1057 INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE MAX1020 toc06 TEMPERATURE (°C) INTERNAL OSCILLATOR FREQUENCY (MHz) 603510-15 4.0 4.2 4.4 4.6 4.8 5.0 3.8 -40 85 MAX1021/MAX1023/MAX1057 MAX1020/MAX1022/MAX1058 ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc07 OUTPUT CODE INTEGRAL NONLINEARITY (LSB) 768512256 -0.2 -0.1 0.1 0.2 0.3 -0.3 0 1024 MAX1020/MAX1022/MAX1058 ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc08 OUTPUT CODE INTEGRAL NONLINEARITY (LSB) 768512256 -0.2 -0.1 0.1 0.2 0.3 -0.3 0 1024 MAX1021/MAX1023/MAX1057 ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc09 OUTPUT CODE DIFFERENTIAL NONLINEARITY (LSB) 768512256 -0.2 -0.1 0.1 0.2 0.3 -0.3 0 1024 MAX1020/MAX1022/MAX1058 ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc10 OUTPUT CODE DIFFERENTIAL NONLINEARITY (LSB) 768512256 -0.2 -0.1 0.1 0.2 0.3 -0.3 0 1024 MAX1021/MAX1023/MAX1057 ADC OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE MAX1020 toc11 SUPPLY VOLTAGE (V) OFFSET ERROR (LSB) 5.155.054.954.85 -0.7 -0.6 -0.5 -0.4 -0.8 4.75 5.25 MAX1020/MAX1022/MAX1058 ADC OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE MAX1020 toc12 SUPPLY VOLTAGE (V) OFFSET ERROR (LSB) 3.33.0 -1.5 -1.0 -0.5 -2.0 2.7 3.6 MAX1021/MAX1023/MAX1057 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ADC OFFSET ERROR vs. TEMPERATURE MAX1020 toc13 TEMPERATURE (°C) OFFSET ERROR (LSB) 603510-15 -1.5 -1.0 -0.5 -2.0 -40 85 MAX1021/MAX1023/MAX1057 MAX1020/MAX1022/MAX1058 ADC GAIN ERROR vs. ANALOG SUPPLY VOLTAGE MAX1020 toc14 SUPPLY VOLTAGE (V) GAIN ERROR (LSB) 5.155.054.954.85 -0.050 -0.025 0.025 0.050 -0.075 4.75 5.25 MAX1020/MAX1022/MAX1058 ADC GAIN ERROR vs. ANALOG SUPPLY VOLTAGE MAX1020 toc15 SUPPLY VOLTAGE (V) GAIN ERROR (LSB) 3.33.0 0.25 0.30 0.35 0.40 0.45 0.50 0.20 2.7 3.6 MAX1021/MAX1023/MAX1057 ADC GAIN ERROR vs. TEMPERATURE MAX1020 toc16 TEMPERATURE (°C) GAIN ERROR (LSB) 603510-15 -0.25 0.25 0.50 0.75 1.00 -0.50 -40 85 MAX1021/MAX1023/MAX1057 MAX1020/MAX1022/MAX1058 ADC EXTERNAL REFERENCE INPUT CURRENT vs. SAMPLING RATE MAX1020 toc17 SAMPLING RATE (ksps) ADC EXTERNAL REFERENCE INPUT CURRENT (µA) 25020015010050 0 300 MAX1020/MAX1022/MAX1058 MAX1021/MAX1023/MAX1057 ANALOG SUPPLY CURRENT vs. SAMPLING RATE MAX1020 toc18 SAMPLING RATE (ksps) ANALOG SUPPLY CURRENT (mA) 25020015010050 0.5 1.0 1.5 2.0 2.5 3.0 0 300 MAX1020/MAX1022/MAX1058 MAX1021/MAX1023/MAX1057 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1020 toc19 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 5.155.054.954.85 2.4 2.5 2.6 2.7 2.8 2.2 2.3 4.75 5.25 MAX1020/MAX1022/MAX1058 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAx1020 toc20 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 3.33.0 2.1 2.2 2.3 2.4 2.5 2.6 1.9 2.0 2.7 3.6 MAX1021/MAX1023/MAX1057 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1020 toc21 TEMPERATURE (°C) ANALOG SUPPLY CURRENT (mA) 603510-15 2.4 2.5 2.6 2.7 2.3 -40 85 MAX1020/MAX1022/MAX1058 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1020 toc22 TEMPERATURE (°C) ANALOG SUPPLY CURRENT (mA) 603510-15 2.13 2.12 2.11 2.14 2.15 2.16 2.10 -40 85 MAX1021/MAX1023/MAX1057 DAC INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc23 OUTPUT CODE INTEGRAL NONLINEARITY (LSB) 768512256 -0.2 -0.1 0.1 0.2 0.3 -0.3 0 1024 MAX1020/MAX1022/MAX1058 DAC INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc24 OUTPUT CODE INTEGRAL NONLINEARITY (LSB) 768512256 -0.2 -0.1 0.1 0.2 0.3 -0.3 0 1024 MAX1021/MAX1023/MAX1057 DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc25 OUTPUT CODE DIFFERENTIAL NONLINEARITY (LSB) 1035103210291026 -0.05 0.05 0.10 -0.10 1023 1038 MAX1020/MAX1022/MAX1058 DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX1020 toc26 OUTPUT CODE DIFFERENTIAL NONLINEARITY (LSB) 1035103210291026 -0.05 0.05 0.10 -0.10 1023 1038 MAX1021/MAX1023/MAX1057 DAC FULL-SCALE ERROR vs. ANALOG SUPPLY VOLTAGE MAX1020 toc27 SUPPLY VOLTAGE (V) DAC FULL-SCALE ERROR (LSB) 5.155.054.954.85 0.01 0.02 0.03 0.04 4.75 5.25 MAX1020/MAX1022/MAX1058 DAC FULL-SCALE ERROR vs. ANALOG SUPPLY VOLTAGE MAx1020 toc28 SUPPLY VOLTAGE (V) DAC FULL-SCALE ERROR (LSB) 3.33.0 -0.65 -0.60 -0.55 -0.50 -0.70 2.7 3.6 MAX1021/MAX1023/MAX1057 DAC FULL-SCALE ERROR vs. TEMPERATURE MAX1020 toc29 TEMPERATURE (°C) DAC FULL-SCALE ERROR (LSB) 603510-15 0.5 1.0 1.5 2.0 -1.0 -0.5 -40 85 INTERNAL REFERENCE EXTERNAL REFERENCE = 4.096V MAX1020/MAX1022/MAX1058 DAC FULL-SCALE ERROR vs. TEMPERATURE MAX1020 toc30 TEMPERATURE (°C) DAC FULL-SCALE ERROR (LSB) 603510-15 -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 -2.00 -1.75 -40 85 INTERNAL REFERENCE EXTERNAL REFERENCE = 2.500V MAX1021/MAX1023/MAX1057 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC FULL-SCALE ERROR vs. REFERENCE VOLTAGE MAX1020 toc31 REFERENCE VOLTAGE (V) DAC FULL-SCALE ERROR (LSB) 431 2 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 -1.00 MAX1020/MAX1022/MAX1058 DAC FULL-SCALE ERROR vs. REFERENCE VOLTAGE MAX1020 toc32 REFERENCE VOLTAGE (V) DAC FULL-SCALE ERROR (LSB) -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 3.0 MAX1021/MAX1023/MAX1057 DAC FULL-SCALE ERROR vs. LOAD CURRENT MAX1020 toc33 LOAD CURRENT (mA) DAC FULL-SCALE ERROR (LSB) 252015105 03 0 MAX1020/MAX1022/MAX1058 DAC FULL-SCALE ERROR vs. LOAD CURRENT MAX1020 toc34 LOAD CURRENT (mA) DAC FULL-SCALE ERROR (LSB) 0 3.0 MAX1021/MAX1023/MAX1057 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1020 toc35 TEMPERATURE (°C) INTERNAL REFERENCE VOLTAGE (V) 603510-15 4.09 4.10 4.11 4.12 4.08 -40 85 MAX1020/MAX1022/MAX1058 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1020 toc36 TEMPERATURE (°C) INTERNAL REFERENCE VOLTAGE (V) 603510-15 2.49 2.50 2.51 2.52 2.48 -40 85 MAX1021/MAX1023/MAX1057 ADC REFERENCE SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1020 toc37 SUPPLY VOLTAGE (V) ADC REFERENCE SUPPLY CURRENT (µA) 5.155.054.954.85 42.2 42.4 42.6 42.8 43.0 42.0 4.75 5.25 MAX1020/MAX1022/MAX1058 ADC REFERENCE SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1020 toc38 SUPPLY VOLTAGE (V) ADC REFERENCE SUPPLY CURRENT (µA) 3.33.0 25.5 25.6 25.7 25.8 25.4 2.7 3.6 MAX1021/MAX1023/MAX1057 ADC REFERENCE SUPPLY CURRENT vs. TEMPERATURE MAX1020 toc39 TEMPERATURE (°C) ADC REFERENCE SUPPLY CURRENT (µA) 603510-15 -40 85 MAX1020/MAX1022/MAX1058 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ADC REFERENCE SUPPLY CURRENT vs. TEMPERATURE MAX1020 toc40 TEMPERATURE (°C) ADC REFERENCE SUPPLY CURRENT (µA) 6035-15 10 25.25 25.50 25.75 26.00 26.25 26.50 26.75 27.00 25.00 -40 85 MAX1021/MAX1023/MAX1057 ADC FFT PLOT MAX1020 toc41 ANALOG INPUT FREQUENCY (kHz) AMPLITUDE (dB) 15010050 -140 -120 -100 -80 -60 -40 -20 -160 0 200 fSAMPLE = 32.768kHz fANALOG_)N = 10.080kHz fCLK = 5.24288MHz SINAD = 61.21dBc SNR = 61.21dBc THD = 73.32dBc SFDR = 81.25dBc ADC IMD PLOT MAX1020 toc42 ANALOG INPUT FREQUENCY (kHz) AMPLITUDE (dB) 15010050 -140 -120 -100 -80 -60 -40 -20 -160 0 200 fCLK = 5.24288MHz fIN1 = 9.0kHz fIN2 = 11.0kHz AIN = -6dBFS IMD = 78.0dBc ADC CROSSTALK PLOT MAX1020 toc43 ANALOG INPUT FREQUENCY (kHz) AMPLITUDE (dB) 15010050 -140 -120 -100 -80 -60 -40 -20 -160 0 200 fCLK = 5.24288MHz fIN1 = 10.080kHz fIN2 = 8.0801kHz SNR = 61.11dBc THD = 73.32dBc ENOB = 9.86 BITS SFDR = 86.34dBc DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT MAX1020 toc44 OUTPUT CURRENT (mA) DAC OUTPUT VOLTAGE (V) 60300 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.00 -30 90 DAC OUTPUT = MIDSCALE MAX1020/MAX1022/MAX1058 SINKING SOURCING DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT MAX1020 toc45 OUTPUT CURRENT (mA) DAC OUTPUT VOLTAGE (V) 20100-20 -10 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.21 -30 30 DAC OUTPUT = MIDSCALE MAX1021/MAX1023/MAX1057 SINKING SOURCING GPIO OUTPUT VOLTAGE vs. SOURCE CURRENT MAX1020 toc46 SOURCE CURRENT (mA) GPIO OUTPUT VOLTAGE (V) 80604020 0 100 MAX1020/MAX1022/MAX1058 GPIOA0–A3 OUTPUTS GPIOB0–B3, C0–C3 OUTPUTS GPIO OUTPUT VOLTAGE vs. SOURCE CURRENT MAX1020 toc47 SOURCE CURRENT (mA) GPIO OUTPUT VOLTAGE (V) 80604020 0.5 1.0 1.5 2.0 2.5 3.0 0 100 MAX1021/MAX1023/MAX1057 GPIOA0–A3 OUTPUTS GPIOB0–B3, C0–C3 OUTPUTS GPIO OUTPUT VOLTAGE vs. SINK CURRENT MAX1020 toc48 SINK CURRENT (mA) GPIO OUTPUT VOLTAGE (mV) 80604020 300 600 900 1200 1500 0 100 MAX1020/MAX1022/MAX1058 GPIOA0–A3 OUTPUTS GPIOB0–B3, C0–C3 OUTPUTS Typical Operating Characteristics (continued) (AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports GPIO OUTPUT VOLTAGE vs. SINK CURRENT MAX1020 toc49 SINK CURRENT (mA) GPIO OUTPUT VOLTAGE (mV) 40 50302010 300 600 900 1200 1500 06 0 MAX1021/MAX1023/MAX1057 GPIOA0–A3 OUTPUTS GPIOB0–B3, C0–C3 OUTPUTS TEMPERATURE SENSOR ERROR vs. TEMPERATURE MAX1020 toc50 TEMPERATURE (°C) TEMPERATURE SENSOR ERROR (°C) 6035-15 10 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 -1.00 -40 85 DAC-TO-DAC CROSSTALK RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc51 100µs VOUTA 1V/div VOUTB 10mV/div AC-COUPLED MAX1021/MAX1023/MAX1057 DAC-TO-DAC CROSSTALK RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc52 100µs VOUTA 2V/div VOUTB 10mV/div AC-COUPLED MAX1020/MAX1022/MAX1058 DYNAMIC RESPONSE RISE TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc53 1µs VOUT 1V/div CS 1V/div MAX1021/MAX1023/MAX1057 DYNAMIC RESPONSE RISE TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc54 1µs VOUT 2V/div CS 2V/div MAX1020/MAX1022/MAX1058 DYNAMIC RESPONSE FALL TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc55 1µs VOUT 1V/div CS 1V/div MAX1021/MAX1023/MAX1057 DYNAMIC RESPONSE FALL TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc56 1µs VOUT 2V/div CS 2V/div MAX1020/MAX1022/MAX1058 MAJOR CARRY TRANSITION RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc57 1µs VOUT 10mV/div AC-COUPLED CS 1V/div MAX1021/MAX1023/MAX1057 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAJOR CARRY TRANSITION RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc58 1µs VOUT 20mV/div AC-COUPLED CS 2V/div MAX1020/MAX1022/MAX1058 DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW) MAX1020 toc59 200ns VOUT 100mV/div AC-COUPLED SCLK 1V/div MAX1021/MAX1023/MAX1057 DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW) MAX1020 toc60 200ns VOUT 100mV/div AC-COUPLED SCLK 2V/div MAX1020/MAX1022/MAX1058 NEGATIVE FULL-SCALE SETTLING TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc61 1µs VOUT 1V/div MAX1021/MAX1023/MAX1057 VLDAC 1V/div NEGATIVE FULL-SCALE SETTLING TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc62 2µs VOUT_ 2V/div MAX1020/MAX1022/MAX1058 VLDAC 2V/div POSITIVE FULL-SCALE SETTLING TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc63 1µs VOUT_ 1V/div MAX1021/MAX1023/MAX1057 VLDAC 1V/div POSITIVE FULL-SCALE SETTLING TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc64 1µs VOUT_ 2V/div MAX1020/MAX1022/MAX1058 VLDAC 2V/div ADC REFERENCE FEEDTHROUGH RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc65 200µs VDAC-OUT 10mV/div AC-COUPLED MAX1021/MAX1023/MAX1057 VREF2 1V/div ADC REFERENCE SWITCHING ADC REFERENCE FEEDTHROUGH RLOAD = 10kΩ, CLOAD = 100pF MAX1020 toc66 200µs VDAC-OUT 2mV/div AC-COUPLEDMAX1020/MAX1022/MAX1058 VREF2 2V/div ADC REFERENCE SWITCHING Typical Operating Characteristics (continued) (AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE = 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Pin Description MAX1020/ MAX1021 MAX1022/ MAX1023 MAX1057/ MAX1058 NAME FUNCTION 1, 2 — — GP IOA0, G P IOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA. 334 EOC Active-Low End-of-Conversion Output. Data is valid after the falling edge of EOC.

447 D V DD

Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF capacitor. 55 8 DGND Digital Ground. Connect DGND to AGND. 66 9 DOUT Serial-Data Output. Data is clocked out on the falling edge of the SCLK clock in modes 00, 01, and 10. Data is clocked out on the rising edge of the SCLK clock in mode 11. It is high impedance when CS is high. 77 10 SCLK Serial-Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%.) See Table 5 for details on programming the clock mode. 88 1 1 DIN Serial-Data Input. DIN data is latched into the serial interface on the falling edge of SCLK. 9–12, 16–19 9–12, 16–19 12–15, 22–25 OUT0–OUT7 DAC Outputs 13 13 18 AV DD Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF capacitor. 14 14 19 AGND Analog Ground 15, 23, 32, 2, 15, 24, 32 32 — N.C. No Connection. Not internally connected. 20 20 26 LDAC Active-Low Load DAC. LDAC is an asynchronous active-low input that updates the DAC outputs. Drive LDAC low to make the DAC registers transparent. 21 21 27 CS Active-Low Chip-Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance. 22 22 28 RES_SEL Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to wake up the DAC outputs with a 100kΩ resistor to VREF. Set RES_SEL high to power up the DAC input register to FFFh. Set RES_SEL low to power up the DAC input register to 000h. 24, 25 — — GP IOC 0, G P IOC 1 G ener al - P ur p ose I/O C 0, C 1. G P IO C 0, C 1 can si nk 4m A and sour ce 2m A.

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Pin Description (continued) MAX1020/ MAX1021 MAX1022/ MAX1023 MAX1057/ MAX1058 NAME FUNCTION 26 26 35 REF1 Reference 1 Input. Reference voltage; leave unconnected to use the internal reference (2.5V for the MAX1021/MAX1023/MAX1057 or 4.096V for the MAX1020/MAX1022/MAX1058). REF1 is the positive reference in ADC external differential reference mode. Bypass REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the ADC/DAC References section. 27–31, 34 —— AIN0–AIN5 Analog Inputs 35 — — REF2/AIN6 Reference 2 Input/Analog-Input Channel 6. See Table 5 for details on programming the setup register. REF2 is the negative reference in the ADC external differential reference. 36 — — CNVST/AIN7 Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details on programming the setup register. —1— CNVST/AIN11 Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for details on programming the setup register. 23, 25, 27–31, 33, 34, 35 — AIN0–AIN9 Analog Inputs —3 6— REF2/AIN10 Reference 2 Input/Analog-Input Channel 10. See Table 5 for details on programming the setup register. REF2 is the negative reference in the ADC external differential reference. —— 1 CNVST/AIN15 Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for details on programming the setup register. —— 2, 3, 5, 6 GPIOA0–GPIOA3 Gener al - P ur p ose I/O A0–A3. GP IOA0–GP IOA3 can si nk and sour ce 15m A. —— 16, 17, 20, 21 GPIOB0–GPIOB3 General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and source 2mA. —— 29–32 GP IOC 0–GP IOC 3 General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and source 2mA. —— 33, 34, 36–47 AIN0–AIN13 Analog Inputs —— 48 REF2/AIN14 Reference 2 Input/Analog-Input Channel 14. See Table 5 for details on programming the setup register. REF2 is the negative reference in the ADC external differential reference. ——— E P Exposed Paddle. Must be externally connected to AGND. Do not use as a ground connect.

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Detailed Description The MAX1020–MAX1023/MAX1057/MAX1058 integrate a multichannel, 10-bit ADC and an octal, 10-bit DAC in a single IC. These devices also include a temperature sensor and configurable GPIOs with a 25MHz SPI- /QSPI-/MICROWIRE-compatible serial interface. The ADC is available in 8/12/16 input-channel versions. The octal DAC outputs settle within 2.0µs, and the ADC has a 300ksps conversion rate. All devices include an internal reference (2.5V or 4.096V) providing a well-regulated, low-noise reference for both the ADC and DAC. Programmable reference modes for the ADC and DAC allow the use of an inter- nal reference, an external reference, or a combination of both. Features such as an internal ±1°C accurate temperature sensor, FIFO, scan modes, programmable internal or external clock modes, data averaging, and AutoShutdown allow users to minimize both power con- sumption and processor requirements. The low glitch energy (4nV

• s) and low digital feedthrough (0.5nV •s) of the integrated octal DACs make these devices ideal for digital control of fast-response closed-loop systems. The devices are guaranteed to operate with a supply voltage from +2.7V to +3.6V (MAX1021/MAX1023/ MAX1057) and from +4.5V to +5.5V (MAX1020/ MAX1022/MAX1058), they consume 25mA at 300ksps throughput, only 22µA at 1ksps throughput, and under 0.2µA in the shutdown mode. The MAX1057/MAX1058 feature 12 GPIOs, while the MAX1020/MAX1021 offer 4 GPIOs that can be configured as inputs or outputs. Figure 1 shows the MAX1057/MAX1058 functional dia- gram. The MAX1020/MAX1021 only include the GPIO A0, A1, GPIO C0, C1 block. The MAX1022/MAX1023 exclude the GPIOs. The output-conditioning circuitry takes the internal parallel data bus and converts it to a serial data format at DOUT, with the appropriate wake- up timing. The arithmetic logic unit (ALU) performs the averaging function. SPI-Compatible Serial Interface The MAX1020–MAX1023/MAX1057/MAX1058 feature a serial interface that is compatible with SPI and MICROWIRE devices. For SPI, ensure the SPI bus mas- ter (typically a microcontroller (µC)) runs in master mode so that it generates the serial clock signal. Select the SCLK frequency of 25MHz or less, and set the clock polarity (CPOL) and phase (CPHA) in the µC con- trol registers to the same value. The MAX1020– MAX1023/MAX1057/MAX1058 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch any input data at DIN on the falling edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK in clock modes 00, 01, and 10. Output data at DOUT is updated on the rising edge of SCLK in clock mode 11. See Figures 6–11. Bipolar true-differential results and tem- perature-sensor results are available in two’s comple- ment format, while all other results are in binary. A high-to-low transition on CS initiates the data-input operation. Serial communications to the ADC always begin with an 8-bit command byte (MSB first) loaded from DIN. The command byte and the subsequent data bytes are clocked from DIN into the serial interface on the falling edge of SCLK. The serial-interface and fast- interface circuitry is common to the ADC, DAC, and GPIO sections. The content of the command byte determines whether the SPI port should expect 8, 16, or 24 bits and whether the data is intended for the ADC, DAC, or GPIOs (if applicable). See Table 1. Driving CS high resets the serial interface. The conversion register controls ADC channel selec- tion, ADC scan mode, and temperature-measurement requests. See Table 4 for information on writing to the conversion register. The setup register controls the clock mode, reference, and unipolar/bipolar ADC con- figuration. Use a second byte, following the first, to write to the unipolar-mode or bipolar-mode registers. See Table 5 for details of the setup register and see Tables 6, 7, and 8 for setting the unipolar- and bipolar- mode registers. Hold CS low between the command byte and the second and third byte. The ADC averag- ing register is specific to the ADC. See Table 9 to address that register. Table 11 shows the details of the reset register. Begin a write to the DAC by writing 0001XXXX as a command byte. The last 4 bits of this command byte are don’t-care bits. Write another 2 bytes (holding CS low) to the DAC interface register following the com- mand byte to select the appropriate DAC and the data to be written to it. See the DAC Serial Interface section and Tables 10, 20, and 21. Write to the GPIOs (if applicable) by issuing a com- mand byte to the appropriate register. Writing to the MAX1020/MAX1021 GPIOs requires 1 additional byte

Figure 1. MAX1057/MAX1058 Functional Diagram

Table 1. Command Byte (MSB First) *Only applicable on the MAX1020/MAX1021/MAX1057/MAX1058. GPIOs on devices without GPIOs are ignored. accept both single-ended and differential input signals. using a selectable bipolar or unipolar transfer function. See the ADC Transfer Functions section for more data.

1. Use clock mode 11 with SCLK up to 4.8MHz for

low. EOC is always high in clock mode 11. channel and the negative input is referred to AGND. AIN14/AIN15. AIN0–AIN7 are available on all devices. AIN0–AIN11 are available on the MAX1022/MAX1023.

AIN0–AIN15 are available on the MAX1057/MAX1058. MAX1057/MAX1058 always operate in unipolar mode. mode. For external T/H timing, use clock mode 01. the required acquisition time lengthens. ates an RC filter that limits the analog input bandwidth. cy signals aliasing into the frequency band of interest. without being serviced by the serial bus. FIFO is empty, DOUT is zero. Figure 2. Equivalent Input Circuit

• s). The 10-bit DAC code is unipolar binary with 1 LSB = VREF / 4096. DAC Digital Interface Figure 1 shows the functional diagram of the MAX1057/ MAX1058. The shift register converts a serial 16-bit word to parallel data for each input register operating with a clock rate up to 25MHz. The SPI-compatible digi- tal interface to the shift register consists of CS, SCLK, DIN, and DOUT. Serial data at DIN is loaded on the falling edge of SCLK. Pull CS low to begin a write sequence. Begin a write to the DAC by writing 0001XXXX as a command byte. The last 4 bits of the DAC select register are don’t-care bits. See Table 10. Write another 2 bytes to the DAC interface register fol- lowing the command byte to select the appropriate DAC and the data to be written to it. See Tables 20 and 21. The eight double-buffered DACs include an input and a DAC register. The input registers are directly connect- ed to the shift register and hold the result of the most recent write operation. The eight 10-bit DAC registers hold the current output code for the respective DAC. Data can be transferred from the input registers to the DAC registers by pulling LDAC low or by writing the appropriate DAC command sequence at DIN. See

Table 20. The outputs of the DACs are buffered through See Table 2 for various analog outputs from the DAC. AGND and the output buffers are powered down. Table 2. DAC Output Code Table

section. See Figures 11 and 12 for GPIO timing. can sink 4mA and source 2mA. See Table 3. three internally timed conversion modes. Table 5. Pulse SCLK at speeds from 0.1MHz to 4.8MHz. Write to SCLK with a 40% to 60% duty cycle. The SCLK frequency controls the conversion timing. Conversions in Clock Mode 11 section. 10 to program the DAC for external reference, REF1. ADC external differential mode. REF2/AIN_ functions as the device’s negative reference. register to one to take a temperature measurement. adjust from Kelvin to Celsius. the old measurement is overwritten by the new result. Table 3. GPIO Maximum Sink/Source Current

circuitry through the SPI-compatible serial interface. command register, respectively. pins are treated as a single differential channel. NSCAN0 in the ADC averaging register ( Table 9). channels for differential operation. Table 4. Conversion Register* —7 (MSB) S et to one to sel ect conver si on r eg i ster . CHSEL3 6 Analog-input channel select. CHSEL2 5 Analog-input channel select. CHSEL1 4 Analog-input channel select. CHSEL0 3 Analog-input channel select. 00 Scans channels 0 through N.

01 Scans channels N through the highest

11 N o scan. C onver ts channel N once onl y.

Table 5. Setup Register* —7 (MSB) Set to zero to select setup register. —6 Set to one to select setup register. CKSEL1 5 Clock mode and CNVST configuration; resets to one at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference-mode configuration. REFSEL0 2 Reference-mode configuration. DIFFSEL1 1 Unipolar-/bipolar-mode register configuration for differential mode. DIFFSEL0 0 (LSB) Unipolar-/bipolar-mode register configuration for differential mode. d el ay of 218 i nter nal - conver si on cl ock cycl es.

00 Internal (DAC

internal reference to settle after wake-up. AIN Internal reference not used. internal reference to settle after wake-up. internal reference to settle after wake-up. AIN Internal reference not used. internal reference to settle after wake-up.

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 5c. Clock Mode 11 REFSEL1 REFSEL0 VOLTAGE REFERENCE OVERRIDE CONDITIONS AUTOSHUTDOWN REF2 CONFIGURATION AIN Inter nal r efer ence tur ns off after scan i s com p l ete. If i nter nal r efer ence i s tur ned off, ther e i s a p r og r am m ed d el ay of 218 exter nal conver si on cl ock cycl es. and ADC) Temperature Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed d el ay of 244 exter nal conver si on cl ock cycl es for the i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s at D OU T after 188 fur ther exter nal cl ock cycl es. AIN14/AIN10/AIN6 AIN Internal reference not used. External single- ended (REF1 for DAC and REF2 for ADC) Tem p er atur e Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed d el ay of 244 exter nal conver si on cl ock cycl es for the i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s at D OU T after 188 fur ther exter nal cl ock cycl es. REF2 AIN Default reference mode. Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 external conversion clock cycles. Internal (ADC) and external REF1 (DAC) Temperature Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed d el ay of 244 exter nal conver si on cl ock cycl es for the i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s at D OU T after 188 fur ther exter nal cl ock cycl es. AIN14/AIN10/AIN6 AIN Internal reference not used. External differential (ADC), external REF1 (DAC) Temperature Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed d el ay of 244 exter nal conver si on cl ock cycl es for the i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s at D OU T after 188 fur ther exter nal cl ock cycl es. REF2 Table 5d. Differential Select Modes DIFFSEL1 DIFFSEL0 FUNCTION 00 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged. 01 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged. 10 1 byte of data follows the command setup byte and is written to the unipolar-mode register. 11 1 byte of data follows the command setup byte and is written to the bipolar-mode register. 1)The FBGON bit is set to one in the reset register. 2)At least one DAC output is powered up and REFSEL[1:0] (in the setup register) = 00. 3)At least one DAC is powered down through the 100kΩ to VREF and REFSEL[1:0] = 00. If any of the above conditions exist, the ADC reference is always on, but there is a 188 clock-cycle delay before temperature-sensor measurements begin, if requested.

Table 6. Unipolar-Mode Register (Addressed Through the Setup Register) UCH0/1 7 (MSB) Configure AIN0 and AIN1 for unipolar differential conversion. UCH2/3 6 Configure AIN2 and AIN3 for unipolar differential conversion. UCH4/5 5 Configure AIN4 and AIN5 for unipolar differential conversion. UCH6/7 4 Configure AIN6 and AIN7 for unipolar differential conversion. UCH8/9 3 Configure AIN8 and AIN9 for unipolar differential conversion. UCH10/11 2 Configure AIN10 and AIN11 for unipolar differential conversion. UCH12/13 1 Configure AIN12 and AIN13 for unipolar differential conversion. UCH14/15 0 (LSB) Configure AIN14 and AIN15 for unipolar differential conversion. Table 7. Bipolar-Mode Register (Addressed Through the Setup Register) unipolar single-ended conversion. unipolar single-ended conversion. unipolar single-ended conversion.

CS low and run 16 SCLK cycles before pulling CS high. gram the unipolar- and bipolar-mode registers. tial, or unipolar differential, see Table 8. complement (see the ADC Transfer Functions section). number of results requested for single-channel scans. Table 8. Unipolar/Bipolar Channel Function

00 Unipolar single-ended

01 Bipolar differential

10 Unipolar differential

11 Unipolar differential

Table 9. ADC Averaging Register* —7 (MSB) Set to zero to select ADC averaging register. —6 Set to zero to select ADC averaging register. —5 Set to one to select ADC averaging register. AVGON 4 Set to one to turn averaging on. Set to zero to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans. NAVG0 2 Configures the number of conversions for single-channel scans. 0X X Performs one conversion for each requested result. 10 0 Performs four conversions and returns the average for each requested result. 10 1 Performs eight conversions and returns the average for each requested result. 11 0 Performs 16 conversions and returns the average for each requested result. 11 1 Performs 32 conversions and returns the average for each requested result. 00 Scans channel N and returns four results. 01 Scans channel N and returns eight results. 10 Scans channel N and returns 12 results. 11 Scans channel N and returns 16 results.

being the average of four conversions of channel N. and the DAC Serial Interface section. Table 10. DAC Select Register —7 (MSB) Set to zero to select DAC select register. —6 Set to zero to select DAC select register. —5 Set to zero to select DAC select register. —4 Set to one to select DAC select register. Table 11. Reset Register —7 (MSB) Set to zero to select ADC reset register. —6 Set to zero to select ADC reset register. —5 Set to zero to select ADC reset register. —4 Set to zero to select ADC reset register. —3 Set to one to select ADC reset register. SLOW 1 Set to one to turn on slow mode. Table 12. GPIO Command Register —7 (MSB) Set to zero to select GPIO register. —6 Set to zero to select GPIO register. —5 Set to zero to select GPIO register. —4 Set to zero to select GPIO register. —3 Set to zero to select GPIO register. —2 Set to zero to select GPIO register. GPIOSEL1 1 GPIO configuration bit. GPIOSEL2 0 (LSB) GPIO write bit.

10 GPIO write; written data is entered

Table 13. MAX1020/MAX1021 GPIO Configuration Table 14. MAX1057/MAX1058 GPIO Configuration Table 15. MAX1020/MAX1021 GPIO Write Table 16. MAX1057/MAX1058 GPIO Write GPIO configuration register in the MAX1057/MAX1058. GPIO, as shown in Tables 13–19. into the GPIO write register in the MAX1057/MAX1058. after the last CS rising edge.

DOUT in the MAX1057/MAX1058. See Tables 18 and 19.

1. Write the next 16 bits to the DAC interface register,

through 7 and forces them to a high-impedance state. DAC outputs 0 through 3 remain in their previous state. Table 18. MAX1020/MAX1021 GPIO Read Table 19. MAX1057/MAX1058 GPIO Read Table 17. GPIO-Mode Control

01 Tri-state Input

Table 20. DAC Serial-Interface Configuration 000 0X XX XX XX XXX XX NOP No operation. leave output buffers in their present state. leave output buffers in their present state. equivalent to software LDAC.

temperature-transfer functions. occur halfway between successive-integer LSB values. or bipolar) takes precedence. Table 21. DAC Power-Up and Power-Down Commands affect the DAC’s present state. DAC output is disconnected and high impedance. A zero does not affect the DAC’s present state.

long as the 4 leading bits (normally zeros) are ignored. programming the clock mode in the setup register. channels, store the results in the FIFO, and shut down. results are available in 12-bit format.

213 F S

1 LSB = VREF / 1024

Figure 3. Unipolar Transfer Function—Full Scale (FS) = V REF Figure 5. Temperature Transfer Function Figure 4. Bipolar Transfer Function—Full Scale (±FS) = ±VREF / 2

Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition ( CNVST is not required). ing the command byte written to the conversion register. pled noise may result in degraded ADC SNR.

1. See Figure 9 for clock mode 11 timing.

DOUT during the last 2 bytes of the 192 cycles. Temperature results are available in 12-bit format. time required to turn on the internal reference. Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Unipolar ADC Offset Error For an ideal converter, the first transition occurs at 0.5 LSB, above zero. Offset error is the amount of deviation between the measured first transition point and the ideal first transition point. Bipolar ADC Offset Error While in bipolar mode, the ADC’s ideal midscale transi- tion occurs at AGND -0.5 LSB. Bipolar offset error is the measured deviation from this ideal value. ADC Gain Error Gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed and with a full-scale analog input voltage applied to the ADC, resulting in all ones at DOUT. DAC Offset Error DAC offset error is determined by loading a code of all zeros into the DAC and measuring the analog output voltage. DAC Gain Error DAC gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed, when loading a code of all ones into the DAC. Aperture Jitter Aperture jitter (t AJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (t AD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital sam- ples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog- to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist fre- quency excluding the fundamental, the first five har- monics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD(dB) = 20 x log (Signal RMS / NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quanti- zation noise only. With an input range equal to the full- scale range of the ADC, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: where V 1 is the fundamental amplitude, and V 2 through V6 are the amplitudes of the first five harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal compo- nent) to the RMS value of the next largest distortion component. ADC Channel-to-Channel Crosstalk Bias the ON channel to midscale. Apply a full-scale sine wave test tone to all OFF channels. Perform an FFT on the ON channel. ADC channel-to-channel crosstalk is expressed in dB as the amplitude of the FFT spur at the frequency associated with the OFF channel test tone. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation prod- ucts are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ± f1). The individual input tone levels are at -7dB FS. Small-Signal Bandwidth A small -20dB FS analog input signal is applied to an ADC so the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conver- sion result has decreased by -3dB. Note that the T/H performance is usually the limiting factor for the small- signal input bandwidth. THD x VVVVV V= ++++() 20 22 32 42 52 62 1log /

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Full-Power Bandwidth A large -0.5dB FS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as full- power input bandwidth frequency. DAC Digital Feedthrough DAC digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital con- trol lines are toggled. ADC Power-Supply Rejection ADC power-supply rejection (PSR) is defined as the shift in offset error when the power-supply is moved from the minimum operating voltage to the maximum operating voltage. DAC Power-Supply Rejection DAC PSR is the amount of change in the converter’s value at full-scale as the power-supply voltage changes from its nominal value. PSR assumes the converter’s linearity is unaffected by changes in the power-supply voltage. Chip Information TRANSISTOR COUNT: 58,141 PROCESS: BiCMOS

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports AIN0 REF1 GPIOC0 N.C. LDAC OUT7 RES_SEL CS GPIOC1EOC DVDD DGND SCLK DIN OUT0 GPIOA0 1 AGND N.C. OUT4 OUT6 AVDD OUT3 OUT2 OUT1 REF2/AIN6 AIN5 N.C. N.C. AIN4 AIN3 AIN2 AIN1 CNVST/AIN7 THIN QFN MAX1020 MAX1021 TOP VIEW DOUT OUT5 GPIOA1 Pin Configurations AIN2 REF1 N.C. AIN0 LDAC OUT7 RES_SEL CS AIN1EOC DVDD DGND SCLK DIN OUT0 CNVST/AIN11 1 AGND N.C. OUT4 OUT6 AVDD OUT3 OUT2 OUT1 AIN9 AIN8 AIN7 N.C. AIN6 AIN5 AIN4 AIN3 REF2/AIN10 THIN QFN MAX1022 MAX1023DOUT OUT5 N.C. 2GPIOA0 3GPIOA1 5GPIOA2 6GPIOA3 7DVDD 8DGND 9DOUT 10SCLK 11DIN 12OUT0 CNVST/AIN15 EOC REF1 AIN1 GPIOC3 GPIOC2 GPIOC1 GPIOC0 RES_SEL CS OUT7 AIN2 AIN0 14OUT2 15OUT3 17GPIOB1 18AVDD 19AGND 20GPIOB2 21GPIOB3 22OUT4 23OUT5 24OUT6 OUT1 GPIOB0 AIN13 AIN12 AIN10 AIN9 AIN8 AIN7 AIN6 AIN5 AIN4 AIN3 REF2/AIN14 AIN11 LDAC THIN QFN MAX1057 MAX1058

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation, go to www.maxim-ic.com/packages.) 32, 44, 48L QFN.EPS PROPRIETARY INFORMATION APPROVAL TITLE: DOCUMENT CONTROL NO. 21-0144 PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm D REV. e L e L A1 AA2 E/2 E D/2 D DETAIL A D2/2 b L k E2/2 E2(NE-1) X e (ND-1) X e e CLCL CL CL k DALLAS SEMICONDUCTOR DETAIL B e L

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation, go to www.maxim-ic.com/packages.) PROPRIETARY INFORMATION DOCUMENT CONTROL NO.APPROVAL TITLE: REV. 21-0144 DALLAS SEMICONDUCTOR PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm D

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS e e LL A1 A2 A E/2 E D/2 D E2/2 E2(NE-1) X e (ND-1) X e e D2/2 b k k L CLCL CL CL E 1 221-0141 PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm L e

MAX1020–MAX1023/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 47 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation, go to www.maxim-ic.com/packages.) 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 3. N IS THE TOTAL NUMBER OF TERMINALS. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. NOTES: 10. WARPAGE SHALL NOT EXCEED 0.10 mm. E 2 221-0141 PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm