MAX1007

MAX1007 MAXIM | Alldatasheet

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The MAX1007 is a multifunctional integrated circuit designed for high-performance mobile radios. It includes one 8-bit analog-to-digital converter (ADC), and two 7-bit and two 6-bit digital-to-analog converters (DACs) for functions including radio-frequency (RF) power sensing and antenna-diversity selection. The ADC provides for power sense, receive-signal strength intensity (RSSI) measurements and system supervision. In the power-sense mode, the ADC con- verts the power-sensing circuitry signal (representing either the transmitted (Tx) or received (Rx) RF power) into a digital code, ensuring optimum Tx power setting and Rx signal analysis. An additional direct input to the ADC provides for system-supervision measurements, such as power-supply voltages, battery voltage, and temperature. Four DAC blocks typically control DC levels in radios. As part of the Maxim PWT1900 chip set, the two 7-bit DACs control the gain settings and the two 6-bit DACs control the varactor diodes to tune a TCXO and bias a GaAs amplifier. Each DAC register and output can be updated independently, providing maximum flexibility. For antenna diversity, a magnitude-comparison circuit captures and compares two peak signals. A latched logic-comparator output reveals which signal has the largest magnitude. The MAX1007 also includes an on- board voltage reference for the ADC and DACs. The MAX1007 offers a high level of signal integrity with minimal power dissipation. Single-supply operation ranges from +2.85V to +3.6V. To further save power, there are two shutdown modes: standby and total shutdown. Standby is a partial shutdown that keeps the bandgap reference and the 2.4V reference generator active. Total shutdown disables all circuit blocks except the serial interface, reducing supply current to less than 1µA. The MAX1007 is available in a 24-pin SSOP and is specified for commercial and extended temperature ranges. PWT1900 Wireless Communications: Cellular Radios PMR/SMR PCS Radios WLL ' Multi-Input 8-Bit ADC ' Two 7-Bit DACs with Buffered Outputs ' Two 6-Bit DACs: Buffered/Unbuffered ' Power-Sense Conditioning Circuitry ' RSSI Measurement ' Antenna-Diversity Circuitry ' Internal Reference ' Serial-Logic Interface ' +2.85V to +3.6V Single-Supply Operation ' Two Shutdown Modes MAX1007 Mobile-Radio Analog Controller 19-1180; Rev 0; 6/98 PART MAX1007CAG MAX1007EAG -40°C to +85°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE

24 SSOP

Ordering Information

Pin Configuration appears at end of data sheet. CS SCLK DIN

7 DOUTSDAC

PREAMBLE-SWITCHED DIVERSITY POWER SENSE CIRCUITRY PSDWDW DUAL T/H VREF XDAC GDAC KDAC REF PSOUT BANT ADC CTRL PKWDW D FLIP-FLOP MAX1007 Functional Diagram For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.

Mobile-Radio Analog Controller ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Continuous Power Dissipation (TA = +70° C) Operating Temperature Ranges AVDD, DVDD RxEN = 1, TxEN = 1; AVDD = DVDD = 3V RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state B on Figure 1 RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW = ADCCTRL = DGND RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state B on Figure 1. PSDWDW and PSD- CNTRL as per state D on Figure 2 RxEN = 0, TxEN = 1; AVDD = DVDD = 3V; PKWDW = ADCCTRL = DGND RxEN = 0, TxEN = 1; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state B on Figure 1 RxEN = 1, TxEN = 0; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state C on Figure 1 RxEN = 0, TxEN = 1; AVDD = DVDD = 3V; PKWDW and ADCCTRL as per state C on Figure 1 CONDITIONS mA1.24 3.5Standby: XDAC, GDAC, Ref, RefBuf Active mA4.07 10.5 Receive Mode 4: KDAC, XDAC, ADC, RSSI Buffer, Ref, RefBuf, PSD Circuit Active mA11.2 31 Receive Mode 3: KDAC, XDAC, ADC, Peak Detector RSSI Buffer, Ref, RefBuf Active V2.85 3.0 3.6Supply Voltages mA2.95 Receive Mode 2: KDAC, XDAC, Peak Detector, RSSI Buffer, Ref, RefBuf Active mA1.24 3.5 Receive Mode 1: KDAC, XDAC, Ref, RefBuf Active mA1.8 5.0Transmit Mode 1: All DACs, Ref, RefBuf Active mA4.7 Transmit Mode 2: All DACs, PGA, REF, Peak Detector, PSBIAS, ISOURCE, RefBuf Active mA12.2 32 Transmit Mode 3: All DACs, PGA, REF, Peak Detector, PSBIAS, ISOURCE, RefBuf, ADC Active UNITSMIN TYP MAXPARAMETER RxEN = 0, TxEN = 0; AVDD = DVDD = 3V; ADCCTRL = PSDCTRL = PKWDW = PSDWDW = DGND; SCLK not active, either high or low µA1 10Total Shutdown POWER-SUPPLY REQUIREMENTS SUPPLY CURRENTS [I(AVDD) + I(DVDD)] (Note 1)

Mobile-Radio Analog Controller ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) (Note 2) 2 < code ≤ FS 2 < code ≤ FS 2 < code ≤ FS CL = 30pF, RL = 40kΩ , settling to 5% of final value RL = 40kΩ 2 < code ≤ FS (Note 2) 2 < code ≤ FS (Note 2) CL = 30pF, RL = 40kΩ No resistive load 2 < code ≤ FS CONDITIONS %FSR±10Gain Error LSB±1Offset Error LSB±1Integral Nonlinearity LSB±1Differential Nonlinearity Bits7Resolution µs4Full-Scale Step Response Time V2.1 2.42 2.75Full-Scale Output Swing V/µs0.1Output Slew Rate %FSR±10Gain Error LSB±1Offset Error LSB±1Integral Nonlinearity LSB±1Differential Nonlinearity Bits6Resolution LSB±1Differential Nonlinearity Bits6Resolution kΩ30Output Resistance LSB±1/2Integral Nonlinearity LSB±1Offset Error %FSR±10Gain Error V2.1 2.42 2.75Full-Scale Output Swing UNITSMIN TYP MAXPARAMETER CL = 30pF, RL = 40kΩ , settling to 2% of final value RL = 40kΩ CL = 30pF, RL = 40kΩ µs4Full-Scale Step Response Time V2.1 2.42 2.75Full-Scale Output Swing V/µs0.1Output Slew Rate CL = 30pF, RL = 40kΩ , settling to within 2% of final value µs4Power-Up Time from Standby With respect to VREF VREF = 1.028V (typ) VREF = 1.028V (typ) LSB±5Gain Error LSB±2Offset Error µs5.2Conversion Time LSB±1Integral Nonlinearity LSB±1Differential Nonlinearity V0 VREFInput Signal Range Bits8Resolution µs1.74ADC Power-Up Time from Standby V1.028Reference Voltage XDAC GDAC SDAC, KDAC ADC

Mobile-Radio Analog Controller ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) VIL VIH SYMBOL V0.3VDDInput Voltage Low V0.7VDDInput Voltage High V2.42Internal DAC Reference µA200PS Bias Sink Current V1.87PS Bias Voltage Output V0.96 1.028 1.1Output Voltage mV100 300Minimum Peak Level Detected µs10 20Lowpass-Filter Time Constant Ω200Pull-Down Input Resistance µA50 100 180Current Source -0.44 VVREFMaximum Peak Level Detected mV150Offset Voltage V/V -0.53 Power-Sense Amp Gain (PGA) UNITSMIN TYP MAXPARAMETER CIN RIN IIN pF10Inpt Capacitance kΩ20Input Resistance µA±1Input Current ns100CS High to DOUT Disable ns200 434SCLK Pulse Width Low ns200 434SCLK Pulse Width High ns150SCLK High to DOUT Valid ns100CS Low to DOUT Valid ns20CS Low to SCLK High ns0DIN to SCLK Hold ns100DIN Valid to SCLK Setup t9 ns500 ADC Data Output Delay After End of ADC Conversion (Figure 4b) VOL VOH V0.4Output Voltage Low VVDD - 0.4Output Voltage High CL = 20pF, RL = 100kΩ RS in series with CL, CL = 1nF, 200Ω ≤ RS ≤ 1kΩ RPS, FPS1, FPS2 pulled to AGND when not selected Figure 3b RS in series with CL, CL = 1nF, 200Ω ≤ RS ≤ 1kΩ Reflected transmit, classes 2, 3, 4 Reflected transmit, class 1 RPS, FPS1, FPS2 to ADC input Forward transmit CONDITIONS CL = 20pF, RL = 100kΩ Digital inputs PSDCTRL, PSDWDW Excluding PSDCTRL, PSDWDW CL = 20pF Digital Outputs (DOUT, BANT, SDG) TIMING SPECIFICATIONS (Figure 4) Digital Inputs (CS, SCLK, DIN, PKWDW, ADCCTRL, PSDWDW, PSDCTRL) SERIAL-LOGIC INTERFACE REFERENCE TRANSMIT POWER SENSE RSSI CIRCUIT

-0.5 -0.2 -0.3 -0.4 -0.1 0.1 0.2 0.3 0.4 0.5 0 10050 150 200 250 300 DIFFERENTIAL NONLINEARITY MAX1007-01 CODES DNL (LSBs) 1.25 1.35 1.30 1.45 1.40 1.50 1.55 -40 25 85 SUPPLY CURRENT vs. TEMPERATURE (Tx MODE) MAX1007-02 TEMPERATURE (°C) SUPPLY CURRENT (mA) VDD = 3.6V VDD = 2.85V 1.80 2.00 1.90 2.20 2.10 2.30 2.40 25-40 85 SUPPLY CURRENT vs. TEMPERATURE (Rx MODE) MAX1007-03 TEMPERATURE (°C) SUPPLY CURRENT (mA) VDD = 3.6V VDD = 2.85V 1.019 1.022 1.021 1.020 1.023 1.024 1.025 -5-40 25 55 85 REFERENCE VOLTAGE vs. TEMPERATURE MAX1007-04 TEMPERATURE (°C) REFERENCE VOLTAGE (V) VDD = 3.6V VDD = 2.85V 1.76 1.82 1.80 1.78 1.84 1.86 -5-40 25 55 85 PS BIAS VOLTAGE vs. TEMPERATURE MAX1007-05 TEMPERATURE (°C) PS BIAS VOLTAGE (V) VDD = 3.6V VDD = 2.85V MAX1007 Mobile-Radio Analog Controller ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +2.85V to +3.6V, fSCLK = 1.152MHz, TA = TMIN to TMAX, unless otherwise noted.) (TA = +25° C, unless otherwise noted.) Note 1:All digital inputs at DVDD or DGND. Note 2:All DACs use an internal reference voltage of 2.42V. PARAMETER MIN TYP MAX UNITS PSDWDW Low to BANT Valid ADCCTRL Low to RF input 200 ns 100 ns SCLK Duty Cycle 50 % SYMBOL t10 t11 CONDITIONS RF input on RSSI, RPS, FPS1, FPS2, or PSBIAS, (Figure 4c) CL = 20pF (Figure 4c)

Mobile-Radio Analog Controller Pin Description NAME FUNCTION 1 RPS Used to measure reverse-transmit power level. Only active in transmit mode when PKWDW = 1, SDAC[F/R] = Reverse. When not selected, this pin is internally pulled to AGND through a 200Ω switch.

2 FPS2

Used to measure forward power-sense class 2/3/4. Only active in transmit mode when GDAC[Power Class] = Class 2/3/4, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally pulled to AGND through a 200Ω switch. PIN

3 FPS1

Used to measure forward power-sense level 1. Only active in transmit mode when GDAC[Power Class] = Class 1, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally pulled to AGND through a 200Ω switch. 4 SDAC Buffered output of 7-bit DAC. Controls gain stage in up/down converter. 8 REF 1.028V Reference Voltage Output

7 AGND Analog Ground

6 XDAC Unbuffered output of 6-bit DAC. Used to control VCXO frequency.

5 AVDD Analog Supply Voltage

13 PSDCTRL Preamble-Switched Diversity Measurement-Control Signal (Figure 2). This pin has a 20kΩ pull-down resistor to digital ground.

12 BANT

Best-Antenna Digital Output. Result of preamble-switched diversity measurement (Figure 2). “0” indicates more power was sensed from period A with respect to period B. “1” means vice versa. Period A is sensed in the first 12 clock periods following the PSDWDW rising edge. 11 SDG Software-Programmable Logic Output. Can be used to shut down external bias generator. 10 GDAC Buffered output of 6-bit DAC. Controls negative gate bias voltage of external power amplifier. 9 KDAC Buffered output of 7-bit DAC. Controls gain stage in external modulator block. 14 PSDWDW Preamble-Switched Diversity Measurement Window (Figure 2). This pin has a 20kΩ pull-down resistor to digital ground.

15 ADCCTRL RSSI/Power-Sense Measurement-Control Input (Figure 1)

19 SCLK Serial-Clock Input. Clock can be stopped and resumed at any time (40% to 60% duty cycle).

18 DGND Digital Ground

17 DOUT Serial-Data Output. Enabled when CS is low.

16 PKWDW RSSI/Power-Sense Measurement-Window Digital Input (Figure 1)

24 RSSI

Received-Signal Strength Indicator Analog Input for power-sense and antenna diversity measurements. Signal goes into peak-detector circuit and is sampled at the end of the measurement window by the 8-bit ADC. Only active in receive mode when PKWDW = 1. Peak-detector circuit can be bypassed by using CH1 as the ADC input. 23 PSBIAS Power-Sense Measurement Buffered-Bias Output Voltage. Active only during power sensing. 22 CS Chip Select Input. Enables serial interface when low.

21 DIN Serial-Data Input

20 DVDD Digital Supply Voltage

current source are both generated by the MAX1007.

10 CLOCKS

8 CLOCKS

6 CLOCKS

Figure 1. RSSI/Power-Sense Control Signals

8 CLOCKS4 4 9 CLOCKS

Figure 2. Antenna-Diversity Control Signals

The RSSI input provides a filtered input and a direct input to the ADC. The filtered signal path consists of a unity-gain buffer, an RC lowpass filter, and a peak detector to condition the signal for the ADC. The low - pass filter’s time constant is 10µs (min). The mux at the ADC’s input selects CH0 (filtered input) or CH1 (direct RSSI input). Control Timing The power-sense circuit is activated by the externally generated PKWDW signal (Figure 1) when the MAX1007 is either in transmit or receive mode. When the PKWDW signal goes high, the entire power-sense circuit turns on. However, since the PGA is active only in the transmit mode, it remains shut down during RSSI power measurements to conserve power. Antenna Diversity The antenna or preamble-switched diversity (PSD) cir - cuit compares the signal amplitude presented at RSSI during two different time periods and latches the result at BANT (Best Antenna). The circuit consists of a dual track/hold (T/H) stage, a comparator, and an output latch (D flip-flop). The comparison begins with the signal from the first antenna applied to the RSSI pin (Figure 2). PSDWDW goes high, and the PSD circuit is turned on. A power- on-reset signal initializes the D flip-flop so that it always starts with BANT low. After 4 clocks to reset the peak detector, PSDCTRL goes high to start the measure - ment. The T/H stage acquires the signal for 8 clocks while PSDCTRL is high, then holds the peak value while the second antenna is switched externally to the RSSI pin and the T/H is zeroed. PSDCTRL goes low for another 4 clocks, then goes high to enable the peak detector again. The peak detector is active for another 8 clocks while the output is compared with the peak value for the first antenna. When PSDWDW goes low at the end of the comparison phase, the comparator’s out- put is clocked into the D flip-flop. The D flip-flop’s out - put, BANT, is low if the first antenna signal is greater than the second, and high if the second signal is greater than the first. PSDCTRL goes low one clock period after PSDWDW goes low to power down the PSD circuitry. Analog-to-Digital Converter The ADC is an 8-bit, half-flash ADC with a T/H and two inputs (CH0, CH1). When selected, the acquisition time is 1.74µs. The ADC input range is equal to the 1.028V internal reference. Reference The bandgap voltage reference supports several blocks of the MAX1007. The nominal 1.21V output is scaled and buffered for the power-sense bias, the PGA, the ADC, and the DACs. The PSBIAS output volt - age is 1.87V nominal. The ADC reference is 1.028V. It is buffered to isolate switching noise and to allow exter - nal capacitor bypassing (0.014µF to 0.05µF) for AC sta- bility. A buffered gain supplies all DACs with a nominal 2.42V reference voltage. Digital-to-Analog Converters All four DAC outputs are reset to zero at power-up. Preset DACs to output voltages other than zero in total shutdown mode and update DACs by settling the LD bit in the command byte. XDAC XDAC is a 6-bit voltage-output DAC intended to drive varactor diodes to tune a voltage-controlled crystal oscillator. The input is double-buffered for independent updates. The inverted R-2R ladder output is unbuffered since the load is strictly capacitive. The maximum out - put voltage is 2.42V nominal, and the maximum output resistance is 30k Ω . The output is reset to zero at power-up and is active instantly. When XDAC is dis - abled, the DAC output is actively pulled to AGND. GDAC GDAC is a 6-bit voltage-output DAC intended to control an external negative bias generator, such as the MAX840, for a GaAs amplifier. The digital input is double- buffered. The inverted R-2R ladder output is buffered and can drive a 5kΩ load. The maximum output voltage is 2.42V nominal. The DAC output is reset to zero at power-up and is active in standby. A programmable logic output ( SDG) is provided to shut down the exter - nal bias generator. SDAC and KDAC SDAC and KDAC are 7-bit voltage-output DACs intend - ed to tune power levels of an up/downconverter or a modulator. The digital inputs are double-buffered. The inverted R-2R ladder outputs are buffered and can drive 5kΩ loads. The maximum output voltage is 2.42V nominal. The SDAC and KDAC DAC outputs are reset to zero at power-up. Serial-Interface and Control Logic The serial interface is a 4-wire implementation with CS, SCLK, and DIN inputs and a DOUT output. The hard - ware consists of a 7-bit command register, an 8-bit data input register, an 8-bit data output register, a counter, and control logic. Communication is framed in 16-bit words (8 command bits followed by 8 data bits) MAX1007 Mobile-Radio Analog Controller

Mobile-Radio Analog Controller Chip Information TRANSISTOR COUNT: 6744 RSSI PSBIAS CS DINSDAC FPS1 FPS2 RPS TOP VIEW DVDD SCLK DGND DOUTREF AGND XDAC AVDD PKWDW ADCCTRL PSDWDW PSDCTRLBANT SDG GDAC KDAC SSOP MAX1007 Pin Configuration Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. SSOP.EPS