MAX1005 MAXIM | Alldatasheet
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For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. The MAX1005 is a combined digitizer and reconstruc- tion integrated circuit designed to work in systems that demodulate and modulate communications signals. It integrates IF undersampling and signal synthesis func- tions into a single, low-power circuit. Its analog-to- digital converter (ADC) is used to directly sample or undersample a downconverted RF signal, while its digital-to-analog converter (DAC) recreates the IF sub- carrier and transmission data. The MAX1005’s ADC is ideal for undersampling applications, due to the analog input amplifier’s wide (15MHz) bandwidth. The DAC has very low glitch energy, which minimizes the trans- mission of unwanted spurious signals. An on-chip reference provides for low-noise ADC and DAC conver- sions. The MAX1005 provides a high level of signal integrity from a low power budget. It operates from a single power supply, or from separate analog and digital sup- plies with independent voltages ranging from +2.7V to +5.5V. The MAX1005 can operate with an unregulated analog supply of 5.5V and a regulated digital supply down to 2.7V. This flexible power-supply operation saves additional power in complex digital systems. The MAX1005 has three operating modes: transmit (DAC active), receive (ADC active), and shutdown (ADC and DAC inactive). In shutdown mode, the total supply current drops below 1µA. The device requires only 2.4µs to wake up from shutdown mode. The MAX1005 is ideal for hand-held, as well as base-station applications. It is available in a tiny 16-pin QSOP pack- age specified for operation over both the commercial and extended temperature ranges. PWT1900 PHS/P Wireless Loops PCS/N ' Differential-Input, 5-Bit ADC ' Differential-Output, 7-Bit DAC ' 15Msps Min Conversion Rate ' 25MHz -1dB Full-Power Bandwidth ' 44dB SFDR for ADC 39dB at 10.7MHz SFDR (Imaged) for DAC ' Internal Voltage Reference ' Parallel Logic Interface ' Single-Supply Operation (+2.7V to +5.5V) ' 0.1µA Low-Power Shutdown Mode MAX1005 IF Undersampler VCCD CLK TOP VIEW MAX1005 QSOP DGND RXEN TXEN AIO+ AIO- AGND VCCA 19-1291; Rev 0; 9/97 PART MAX1005CEE MAX1005EEE -40°C to +85°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE
16 QSOP
Functional Diagram appears at end of data sheet.
ELECTRICAL CHARACTERISTICS
(VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ¥ , TA = TMIN to TMAX, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Digital I/O Pins (D0–D6, CLK, RXEN, TXEN) (whichever is smaller) Analog I/O Pins (AIO+, AIO-) Power Dissipation (TA = +70° C) Operating Temperature Ranges (Notes 9, 10) AIO+ = AIO- (Note 4) (Notes 6, 7) (Note 3) (Note 5) CONDITIONS -42 dB-42 -24THDTotal Harmonic Distortion mV368 400 432VINFull-Scale Input Range LSB±2Offset Error LSB±0.2DNLDifferential Nonlinearity LSB±0.2INLIntegral Nonlinearity Bits5NResolution dB67PSRPower-Supply Rejection CLK period0.5DAC Latency dBc-50Clock Feedthrough µs0.7 2.4tWAKEWakeup Time Exiting Shutdown LSB±0.2 ±1INLIntegral Nonlinearity Bits7NResolution -28 dBcTHD+NTotal Harmonic Distortion plus Noise 39 dBc28 39SFDRSpurious-Free Dynamic Range LSB±0.2 ±1DNLDifferential Nonlinearity LSB±1Offset Error mVp-p736 800 864VOUTTransmit Full-Scale Output Voltage UNITSMIN TYP MAXSYMBOLPARAMETER VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V VCCA = VCCD = 3.0V VCC_ (A or D or both) = 3.0V ±100mVp-p at 100kHz VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V (Note 9) (Note 9) 4.9 Bits4.5 4.9ENOBEffective Number of Bits 44 dB24 44SFDRSpurious-Free Dynamic Range VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V TRANSMIT DAC DC ACCURACY (Note 1) TRANSMIT DAC DYNAMIC PERFORMANCE (TA = +25° C) (Note 2) TRANSMIT ADC DC ACCURACY (Note 8) RECEIVE ADC DYNAMIC PERFORMANCE (TA = +25° C) (Note 8)
ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ¥ , TA = TMIN to TMAX, unless otherwise noted.) VCCD = 2.7V to 5.5V VCCD = 2.7V to 5.5V D0–D4, VCCD = 2.7V to 5.5V, ISINK = 50µA D0–D4, VCCD = 2.7V to 5.5V, ISOURCE = 200µA VCCA = VCCD = 3.0V, CL ≤ 12.5pF, RXEN = TXEN VCCA = VCCD = 3.0V, C L ≤ 12.5pF AIO+ or AIO- to GND Differential between AIO+ and AIO- VCCA = VCCD = 3.0V, C L ≤ 12.5pF CONDITIONS -0.1 0.5 V0.3VCCDVILInput Low Voltage VCCD - VCCD + 0.5 0.1 V 0.7VCCD VIHInput High Voltage V0 0.5VOLOutput Low Voltage VVCCD - 1.0 VCCDVOHOutput High Voltage µA<0.1 5ICCA + ICDShutdown Supply Current 3.0 5.6 mA 4.0 6.4 ICCDDigital Supply Current 2.5 3.8 mA 9.0 14.8 ICCAAnalog Supply Current µs0.6 2.4tWAKE Wakeup Time Exiting Shutdown Mode Msps15 MHz15 25Input Full-Power Bandwidth (-1dB) Conversion Rate V2.7 5.5VCCA, VCCDSupply Voltage pF4CINInput Capacitance (Note 6) LSB<0.1PSRPower-Supply Rejection kΩ1.56 2.00 2.44RINInput Resistance ppm/° C-2000TCRIN Input Resistance Temperature Coefficient UNITSMIN TYP MAXSYMBOLPARAMETER RXEN, TXEN D0–D6, CLK RXEN, TXEN D0–D6, CLK VIN = 90% of full scale RXEN = 0, TXEN = 1, ADC off, DAC on RXEN = 1, TXEN = 0, ADC on, DAC off VCC_ (A or D or both) = 3.0V ±100mVp-p at 100kHz TA = +25° C, differential between AIO+ and AIO- RXEN = 0, TXEN = 1, ADC off, DAC on RXEN = 1, TXEN = 0, ADC on, DAC off DIGITAL INPUTS/OUTPUTS (D0–D6, RXEN, TXEN, CLK) (Note 12) POWER REQUIREMENTS ANALOG INPUT/OUTPUT (AIO+, AIO-) (Note 11)
ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ¥ , TA = TMIN to TMAX, unless otherwise noted.) RXEN, TXEN; VCCD = 2.7V to 3.6V D0–D6, CLK; VCCD = 2.7V to 5.5V CL ≤ 12.5pF TA = +25° C (Note 6) TA = +25° C (Note 6) RXEN, TXEN; VCCD = 3.6V to 5.5V D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6) CONDITIONS µA -1 7 IINInput Current ns13 20tDOADC CLK to Output Data Valid %45 55CLK Duty Cycle ns5 0.3tHOLDDAC Data Hold Time ns5 0.6tDSDAC Data Setup Time pF8CINInput Capacitance UNITSMIN TYP MAXSYMBOLPARAMETER TXEN = 0 and RXEN = 1, or TXEN = 1 and RXEN = 0 TXEN = RXEN TXEN = RXEN TXEN = 0 and RXEN = 1, or TXEN = 1 and RXEN = 0 Note 1: TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End- Point Linearity method. Note 2: fIN = 4.3MHz digital sine wave applied to DAC data inputs; fCLK = 15MHz. The reference frequency (fREF) is defined to be 10.7MHz (fCLK - fIN). All frequency components present in the DAC output waveform except for fREF and fIN are consid- ered spurious. Note 3: For DAC SFDR measurements, the amplitude of fREF (10.7MHz) is compared to the amplitudes of all frequency compo- nents of the output waveform except for fIN (4.3MHz). Note 4: For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of all harmonic and noise components of the output waveform (except for fIN and fREF) to the RMS amplitude of the fREF com- ponent. Note 5: Clock feedthrough is defined as the difference in amplitude between the fREF component and the fCLK component when measured differentially from AIO+ to AIO-. Note 6: Guaranteed by design. Not production tested. Note 7: The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to propagate through to the DAC switches. Note 8: RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ- entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method. Note 9: fIN = 10.7MHz, fCLK = 15MHz. Amplitude is 1dB below full-scale. The reference frequency (fREF) is defined to be 4.3MHz (fCLK - fIN). All components except for fREF and fIN are considered spurious. Note 10:Receive ADC THD measurements include the first five harmonics. Note 11:CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are required, then bypass these pins only to VCCA. Note 12:All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are measured to VOH(AC) for rising output signals and to VOL(AC) for falling output signals. The values for VOH(AC) and VOL(AC) as a function of the VCCD supply are shown in the following table: VCCD (V) VOH(AC) (V) VOL(AC) (V) 2.7 to 3.3 VCCD - 1.1 0.5 3.3 to 5.5 2/3 x VCCD 0.5 TIMING CHARACTERISTICS (Data Outputs: RL = 1MΩ , CL = 15pF, TA = TMIN to TMAX, unless otherwise noted.) (Note 12)
-0.50 -0.30 -0.40 -0.10 -0.20 0.10 0.00 0.20 0.40 0.30 0.50 -15 -9 -6 -3-12 0 3 6 129 15 RECEIVE ADC INTEGRAL NONLINEARITY MAX1005-01 CODE INL (LSB) -0.50 -0.30 -0.40 -0.10 -0.20 0.10 0.00 0.20 0.40 0.30 0.50 -15 -9 -6 -3-12 0 3 6 129 15 RECEIVE ADC DIFFERENTIAL NONLINEARITY MAX1005-02 CODE DNL (LSB) -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0.2 0.4 0.3 0.5 -64 -32 -16-48 0 16 32 48 64 TRANSMIT DAC INTEGRAL NONLINEARITY MAX1005-03 CODE INL (LSB) -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0.2 0.4 0.3 0.5 -64 -32 -16-48 0 16 32 48 64 TRANSMIT DAC DIFFERENTIAL NONLINEARITY MAX1005-04 CODE DNL (LSB) -70 -40 -50 -60 -30 -20 -10 MAX1005-05 FREQUENCY (MHz) AMPLITUDE (dB) fIN = 10.7MHz fCLK = 15MHz
256 POINTS
ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) VIN = 90% OF FULL SCALE (VCCA = VCCD = 3.0V, TA = +25° C, unless otherwise noted.)
ically ±400mV. The DAC code table is shown in Table 1. Table 1. Transmit DAC Code Table suited for undersampling applications. not be externally held high, to prevent excessive input leakage currents. receive ADC. If RXEN = 0 and TXEN = 1, then AIO- is the negative transmit DAC output pin. receive ADC. If RXEN = 0 and TXEN = 1, then AIO+ is the positive transmit DAC output pin.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Power-Supply Bypassing and Grounding The MAX1005 has separate analog (VCCA) and digital (VCCD) power-supply connections, as well as separate analog and digital ground connections to minimize cou - pling of noisy digital signals into the circuit’s analog por - tion. The device will operate with both of these power supplies connected to any voltage between +2.7V and +5.5V. This feature allows the digital circuitry to operate from a regulated logic power supply; this reduces power consumption and maintains compatibility with external logic, while allowing the analog circuitry to operate from an unregulated supply. The analog ground (AGND) and digital ground (DGND) should be tied together close to the device. At no time should the voltage between AGND and DGND exceed ±0.3V. The entire board needs good DC bypassing for both analog and digital supplies. Place the power-supply bypass capacitors close to where the power is routed onto board. 10µF electrolytic capacitors with low equiva - lent-series-resistance (ESR) ratings are recommended. For best effective bits performance, minimize capacitive loading at the digital outputs. Keep the digital output traces as short as possible. Bypass each of the VCC_ supply pins to its respective GND with high-quality ceramic capacitors located as close to the package as possible. TRANSISTOR COUNT: 2377 SUBSTRATE CONNECTED TO AGND 5-BIT FLASH ADC VCCA DAC BANDGAP REFERENCE ADC BANDGAP REFERENCE DIGITAL INTERFACE TXEN RXEN ADC CLOCK DRIVER 1k 1k AIO+ AIO- 7-BIT DAC MAX1005 VCCA AGND VCCD DGND CLK DAC CLOCK DRIVER D6–D07 QSOP.EPS