MAX100

MAX100 MAXIM | Alldatasheet

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The MAX100 ECL-compatible, 250Msps, 8-bit analog-to- digital converter (ADC) allows accurate digitizing of ana- log signals from DC to 125MHz (Nyquist frequency). Designed with Maxim’s proprietary advanced bipolar processes, the MAX100 contains a high-performance track/hold (T/H) amplifier and a quantizer in a single ceramic strip-line package. The innovative design of the internal T/H assures an exceptionally wide input bandwidth of 1.2GHz and aper- ture delay uncertainty of less than 2ps, resulting in a high 6.8 effective bits performance. Special comparator output design and decoding circuitry reduce out-of-sequence code errors. The probability of erroneous codes occurring due to metastable states is reduced to less than 1 error per 10 15 clock cycles. Unlike other ADCs, which can have errors that result in false full-scale or zero-scale out- puts, the MAX100 keeps the magnitude to less than 1LSB. The analog input is designed for either differential or single- ended use with a ±270mV range. Sense pins for the refer- ence input allow full-scale calibration of the input range or facilitate ratiometric use. Midpoint tap for the reference string is available for applications that need to modify the output coding for a user-defined bilinear response. Use of separate high-current and low-current ground pins pro- vides better noise immunity and highest device accuracy. Dual output data paths provide several data output modes for easy interfacing. These modes can be configured as either one or two identical latched ECL outputs. An 8:16 demultiplexer mode that reduces the output data rates to one-half the clock rate is also available. For applications that require faster data rates, refer to Maxim’s MAX101, which allows conversion rates up to 500Msps. ' 250Msps Conversion Rate ' 6.8 Effective Bits at 125MHz ' Less than ±1/2LSB INL ' 50Ω Differential or Single-Ended Inputs ' ±270mV Input Signal Range ' Reference Sense Inputs ' Ratiometric Reference Inputs ' Configurable Dual-Output Data Paths ' Latched, ECL-Compatible Outputs ' Low Error Rate, Less than 10-15Metastable States ' Selectable On-Chip 8:16 Demultiplexer ' 84-Pin Ceramic Flat Pack High-Speed Digital Instrumentation High-Speed Signal Processing Medical Systems Radar/Sonar High-Energy Physics Communications MAX100 DCLK DCLK A=BDIVMOD BData (B0–B7) AData (A0–A7) AIN+ AIN- CLK CLK VART VARTS VARBVARBSVACT VACTS L A T C H E S B U F F E R L A T C H E S MODE CONTROL TRACK/ HOLD FLASH CONVERTER 8 8 Call toll free 1-800-998-8800 for free literature. PART MAX100CFR* 0°C to +70°C TEMP. RANGE PIN-PACKAGE

84 Ceramic Flat Pack (with heatsink)

19-0282; Rev 0; 7/94 EVALUATION KIT AVAILABLE *Contact factory for 84-Pin Ceramic Flat Pack without heatsink. 250Msps, 8-Bit ADC with Track/Hold

250Msps, 8-Bit ADC with Track/Hold ELECTRICAL CHARACTERISTICS (continued) (VEE = -5.2V, V CC = +5V, R L = 50 Ω to -2V, VA RT = 1.02V, VA RB = -1.02V, T MIN to T MAX = 0°C to +70°C, T A = +25°C, unless otherwise noted.) (Note 3) VART to VARB -5 20 -1.95 -1.60 CONDITIONS VCC = 5.0V AData, BData, DCLK, DCLK mA710ICCPositive Supply Current V-1.95 -1.50VOLDigital Output Low Voltage 464 670 Ω116 175RREFReference String Resistance Ω /°C0.02Reference String Resistance Temperature Coefficient UNITSMIN TYP MAXSYMBOLPARAMETER DIV, MOD, A=B, CLK, CLK, TA = TMIN to TMAX V-1.5VIL Digital Input Low Voltage (Note 8) DIV, MOD, A=B, CLK, CLK, TA = TMIN to TMAX V-1.07VIH Digital Input High Voltage (Note 8) DIV, MOD, A=B = -1.8V, TA = TMIN to TMAX µA 08 0 IIL CLK, CLK, VIL = -1.8V (no termination), TA = TMIN to TMAX Digital Input Low Current -5 20DIV, MOD, A=B = -0.8V, TA = TMIN to TMAX µA 08 0 IIH CLK, CLK, VIH = -0.8V (no termination), TA = TMIN to TMAX Digital Input High Current TA = +25°C TA = TMIN to TMAX TA = TMIN to TMAX AData, BData, DCLK, DCLK V-1.10 -0.70VOHDigital Output High Voltage TA = +25°C TA = TMIN to TMAX VEE = -5.2V TA = +25°C mA-780IEENegative Supply Current TA = TMIN to TMAX -750 -560 VINCM = ±0.5V TA = TMIN to TMAX dBCMRRCommon-Mode Rejection Ratio 35 dB40VCC(nom) = ±0.25VPower-Supply Rejection Ratio PSRR TA = TMIN to TMAX REFERENCE INPUT LOGIC INPUTS LOGIC OUTPUTS (Note 9) POWER REQUIREMENTS VEE(nom) = ±0.25V 40

vs. OUTPUT CODE 0.75 0.50 0.25 -0.25 0 64 128 192 256 -0.50 -0.75 INL (LSBs) OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.75 0.50 0.25 -0.25 DNL (LSBs) 64 128 192 256 -0.50 -0.75 (TA = +25°C, unless otherwise noted.) MAX100 250Msps, 8-Bit ADC with Track/Hold TIMING CHARACTERISTICS (VEE = -5.2V, VCC = +5V, RL = 50Ω to -2V, VART = 1.02V, VARB = -1.02V, TA = +25°C, unless otherwise noted.) DIV = 0, Figure 1 DIV = 1, Figure 2 CLK, CLK, Figures 1 and 2 0.8 2.4 CLK, CLK, Figures 1 and 2 ns1.9 5.7tPD1 CLK to DCLK Propagation Delay CONDITIONS See Figures 3 and 4 and Table 1 (delay depends on output mode) 20% to 80% Clock Cycles 8 1/2 8 1/2 tNPD 7 1/2 7 1/2 Pipeline Delay (Latency) 7 1/2 7 1/2 ps700tR 500Rise Time ns1.9tPWH ns1.9 5.0tPWLClock Pulse Width Low Clock Pulse Width High UNITSMIN TYP MAXSYMBOLPARAMETER DIV = 0, Figure 1 DIV = 1, Figure 2 DCLK to A/BData Propagation Delay DCLK DATA DCLK DATA20% to 80% ps550tF 600Fall Time Divide-by-1 mode Divide-by- 2 mode BData AData Note 3:All devices are 100% production tested at +25°C and are guaranteed by design for T A = TMIN to TMAX as specified. Note 4:Deviation from best-fit straight line. See Integral Nonlinearity section. Note 5:See the Signal-to-Noise Ratio and Effective Bits section in the Definitions of Specifications. Note 6:SNR calculated from effective bits performance using the following equation: SNR (dB) = 1.76 + (6.02) (effective bits). Note 7:Clock pulse width minimum requirements tPWL and tPWH must be observed to achieve stated performance. Note 9:Outputs terminated through 50Ω to -2.0V.

250Msps, 8-Bit ADC with Track/Hold fCLK = 250MHz, fAIN = 120.4462MHz SER = -42.3dB, NOISE FLOOR = -65.4dB FREQUENCY (MHz) FFT PLOT (fAIN = 120.4462MHz) -10 -20 -30 -40 SIGNAL AMPLITUDE (dB) -50 -60 -70 -80 -90 -100 fCLK = 250MHz, fAIN = 10.4462MHz SER = -45.87dB, NOISE FLOOR = -68.5dB FFT PLOT (fAIN = 10.4462MHz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 12.5 25 37.5 50 62.5 SIGNAL AMPLITUDE (dB) FREQUENCY (MHz) 05 0 EFFECTIVE BITS vs. ANALOG INPUT FREQUENCY MAX100-10 fAIN (MHz) EFFECTIVE BITS 100 150 200 250 300 fCLK = 250MHz, VIN = 95% FS 05 0 100 150 200 250 MAX100-12 fAIN (MHz) EFFECTIVE BITS EFFECTIVE BITS vs. ANALOG INPUT FREQUENCY TCASE = +80°C, fCLK = 250MHz, VIN = 95% FS 30050 100 150 200 250 EFFECTIVE BITS vs. CLOCK FREQUENCY MAX100-11 fCLK (MHz) EFFECTIVE BITS fAIN = 10.4MHz, VIN = 95% FS 05 0 100 150 200 250 MAX100-13 fAIN (MHz) EFFECTIVE BITS TCASE = -15°C, fCLK = 250MHz VIN = 95% FS EFFECTIVE BITS vs. ANALOG INPUT FREQUENCY (TA = +25°C, unless otherwise noted.)

250Msps, 8-Bit ADC with Track/Hold (TA = +25°C, unless otherwise noted.) A = CLK, 200mV/div B = DCLK, 200mV/div A B CLOCK RELATIONSHIP (DIVIDE-BY-1 MODE) TIMEBASE = 1ns/div, fCLK = 250MHz A = CLK, 500mV/div B = DCLK, 500mV/div C = AData, 500mV/div A B C CLOCK/DATA (DIVIDE-BY-1 MODE) TIMEBASE = 2ns/div, fCLK = 250MHz A = CLK, 500mV/div B = DCLK, 500mV/div C = AData, 500mV/div CLOCK/DATA (DIVIDE-BY-2 MODE) A B C TIMEBASE = 2ns/div, fCLK = 250MHz TIMEBASE = 1ns/div, tf = 596ps DATA OUTPUT (NEGATIVE EDGE) 100mV/div AData OUTPUT A = DCLK, 200mV/div B = AData, 200mV/div CLOCK/DATA DETAIL (DIVIDE-BY-5 MODE) TIMEBASE = 5ns/div, fCLK = 250MHz A B TIMEBASE = 1ns/div, tr = 580ps DIGITAL CLOCK (POSITIVE EDGE) DCLK 100mV/div

250Msps, 8-Bit ADC with Track/Hold 12 MOD Modulus. MOD and DIV select the output modes. See Table 1. 5, 6, 9, 10, 31, 33, 35, 48, 58, 59, 63, 81, 83 N.C. No Connect—there is no internal connection to these pins. 8, 21, 43, 56 VCC Positive power supply, +5V ±5% nominal 13 DCLK Complementary Differential Clock Outputs. Used to synchronize following circuitry: AData and BData outputs are valid t PD2 after the rising edge of DCLK. See Figures 1–4. 16 A=B Sets AData equal to BData when asserted (A=B = 1). See Table 1. 11 DIV Divide Enable Input. DIV and MOD select the output modes. See Table 1. 3, 61 CLK Complementary Differential Clock Inputs. Can be driven from standard 10K ECL with the following considerations: Internally, pins 2 & 62 and 3 & 61 are the ends of a 50Ω transmission line. Either end can be driven, with the other end terminated with 50Ω to -2V. See Typical Operating Circuit. 4, 7, 15, 49, 57, 60, 64, 67, 70, 71, 74, 77, 78, 79, 82, 84 GND Power-Supply Ground. Connect GND and DGND pins (Note 10). 2, 62 CLK NAME FUNCTION 1 PAD Internal connection, leave open. PIN 17, 20, 23, 26, 36, 39, 42, 45 A7–A0 19, 22, 25, 28, 38, 41, 44, 47 B7–B0 AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData outputs conform to standard 10K ECL logic swings and drive 50Ω transmission lines. Terminate with 50Ω to -2V. See Figures 1–4. 18, 24, 27, 30, 34, 37, 40, 46 DGND Power-Supply Ground. Connect all ground (GND, DGND) pins together, as described in Note 10. 29 SUB Circuit Substrate Contact. This pin must be connected to VEE. 32, 69, 80 VEE Negative Power Supply, -5.2V ±5% nominal

50 VART Positive Reference Voltage Input (Note 11)

51 VARTS Positive Reference Voltage Sense (Note 11)

14 DCLK

±270mV. Drive AIN+ and AIN- differentially for best high-frequency performance.

54 VARBS Negative Reference Voltage Sense (Note 11)

55 VARB Negative Reference Voltage Input (Note 11)

65 TP3 Internal node. Do not connect. 66 TP2 Internal node. Do not connect. 68 TP1 Internal connection. This pin must be connected to GND.

52 VACTS Reference Bias Resistor Center-Tap Sense (Note 12)

53 VACT Reference Bias Resistor Center Tap (Note 12)

ground plane (separated by at least 1/4 inch) and at only one location on the board (see Typical Operating Circuit). noise-free operation of the reference supplies contributes directly to high ADC accuracy. bypassed carefully (refer to Note 11). Figure 1. Output Timing: Divide-by-1 Mode (DIV = 0)

and supplies also degrades effective bits performance. lowing equation to yield the ADC’s effective bits. the Nyquist rate (1/2 the input clock rate). in aperture delay (Figure 5). missing codes and a monotonic transfer function. Figure 5. T/H Aperture Timing

described above when, for example, clock is low. latch and hold its state until the clock goes low again. log data at high conversion rates. stores the analog input voltage for the ADC to convert. edge is applied, the T/H enters hold mode (Figure 5). ranged or all zeros (zero scale) when under ranged. Table 1. Input Voltage Range offset voltage in one of the input terminals AIN + or AIN-.

250Msps, 8-Bit ADC with Track/Hold Table 2. Output Mode Control

0 X 0

0 X 1

DESCRIPTION

8:16 demultiplexer mode. AData and BData ports are active. BData carries older sample and AData carries most recent sam- ple (Figure 4). 1251 0 1 AData and BData ports are active, both carry identi- cal sampled data. Alternate samples are taken but dis- carded. 501 1 0 AData port updates data on 5th input CLK. BData port inac- tive. Other 4 sam- pled data points are discarded. 501 1 1 AData and BData ports are both active with identi- cal data. Data is updated on out- put ports every 5th input clock (CLK). The other 4 samples are discarded. R R R R PARASITIC RESISTANCE TO COMPARATORS POSITIVE REFERENCE CENTER TAP NEGATIVE REFERENCE R/2 R/2 VACTS VACT VARBS VARB VART VARTS PARASITIC RESISTANCE Figure 6. Reference Ladder String *Input clocks (CLK, –C—L—K–) = 250MHz for all above combinations. will have the same duty cycle as CLK.

250Msps, 8-Bit ADC with Track/Hold Reference The ADC’s reference resistor is a Kelvin-sensed, center- tapped resistor string that sets the ADC’s LSB size and dynamic operating range. Normally, the top and bottom of this string are driven with an op amp, and the center tap is left open. However, driving the center tap is an effective way to modify the output coding to provide a user-defined bilinear response. The buffer amplifier used to drive the top and bottom inputs will need to supply approximately 18mA due to the resistor string impedance of 116Ω mini- mum. A reference voltage of ±1.02V is normally applied to inputs VA RT and VARB. This reference voltage can be adjusted up to ±1.4V to accommodate extended input requirements (accuracy specifications are guaranteed with ±1.02V references). The reference input VA RTS, VARBS, and VACTS allow Kelvin sensing of the applied voltages to increase precision. An RC network at the ADC’s reference terminals is needed for best performance. This network consists of a 33Ω resistor connected in series with the op amp out- put that drives the reference. A 0.47µF capacitor must be connected near the resistor at the op amp’s output (see Typical Operating Circuit ). This resistor and capacitor combination should be located within 0.5 inches of the MAX100 package. Any noise on these pins will directly affect the code uncertainty and degrade the ADC’s effective-bits performance. CLK and DCLK All input and output clock signals are differential. The input clocks, CLK and CLK , are the primary timing sig- nals for the MAX100. CLK and CLK are fed to the inter- nal circuitry from pins 2 & 3 or pins 62 & 61 through an internal 50 Ω transmission line. One pair of CLK/CLK inputs should be driven and the other pair terminated by 50Ω to -2V. Either pair can be used as the driven inputs (input lines are balanced) for easy circuit con- nection. A minimum pulse width (t PWL) is required for CLK and CLK (Figures 1–4). For best performance and consistent results, use a low phase-jitter clock source for CLK and CLK . Phase jitter larger than 2ps from the input clock source reduces the converter’s effective-bits performance and causes inconsistent results. DCLK and DCLK are output clock signals derived from the input clocks and are used for external timing of the AData and BData outputs. The MAX100 is character- ized to work with maximum input clock frequencies of 250MHz (Table 1). See Typical Operating Circuit. Output Mode Control DIV, MOD, and A=B are input pins that determine the operating mode of the two output data paths. Six options are available (Table 1). A typical operating con- figuration (8:16 demultiplexer mode) is set by 1 on DIV, 0 on MOD, and 0 on A=B. This will give the most recent sample at AData with the older data on BData. Both outputs are synchronous and are at half the input clock rate. To terminate the control inputs, use a resis- tor to -2V or the equivalent circuit resistor combination from DGND to -5.2V up to 1k Ω . When using a diode pull-up to tie an input high, bias the diode “on” with a pull-down resistor to avoid input voltage excursions close to ground. The control inputs are compatible with standard ECL 10K logic levels over temperature. Layout, Grounding, and Power Supplies The MAX100 is designed with separate analog and dig- ital ground connections to isolate high-current digital noise spikes. The high-current digital ground, DGND, is connected to the collectors of the output emitter fol- lower transistors. The low-current ground connection is GND, which is a combination of the analog ground and the ground of the low-current digital decode section. The DGND and GND connections should be at the same DC level, and should be connected at only one location on the board. This will provide better noise immunity and highest device accuracy. A ground plane is recommended. A +5V ±5% supply as well as a -5.2V ±5% supply is needed for proper operation. Bypass the VEE and VCC supply pins to GND with high-quality 0.1µF and 0.001µF ceramic capacitors located as close to the package as possible. An evaluation kit with a suggest- ed layout is available.

250Msps, 8-Bit ADC with Track/Hold MAX100 1/2 MAX412 1/2 MAX412 D Q Q D Q Q D Q Q D Q Q DCLK DCLK A=B DIV MOD 50Ω 50Ω 50Ω -2V -2V -2V -2V CLOCK BData AData +5V 0.1µF 0.001µF 20Ω 50 8, 21, 43, 56 72. 73 75, 76 AIN+ AIN- CLK DGND GND SUB VEE 29 32, 69, 80* -2V -2V CLK *PINS 68, 4, 7, 15, 49, 57, 60, 64 37, 40, 46 -5.2V 0.1µF 0.001µF 10µF 0.47µF VART VCC VARTS VARB VARBS 120Ω 50Ω 1.02V 0.01µF 0.01µF 2.5V MX580LH 2+VS VOUT GND 51Ω 20k CMPSH-30.22µF CMPSH-30.22µF 51Ω 20Ω 33Ω 20k 50k 70k 10k VACT VACTS MC100E151 MC100E151 WATKINS-JOHNSON SMRA 89-1 MC100E116 150Ω 50Ω

250Msps, 8-Bit ADC with Track/Hold GND CLK CLK N.C.63 TOP VIEW MAX100 VCC GND N.C. N.C. VARBS VARB VART VARTS VACTS VACT DGND N.C. GND VCC GND CLK CLK PAD 1 VCC GND N.C. N.C. N.C. N.C. DCLK DCLK MOD DIV DGND A = B GND VCC N.C. GND N.C. GND GND GND GND VEE AIN- AIN- GND AIN+ AIN+ GND GND TP1 VEE GND TP3 TP2

64 GND

N.C. DGND N.C. DGND N.C. VEE DGND DGND Ceramic Flat Pack

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX100 250Msps, 8-Bit ADC with Track/Hold 0 100 200 300 400 500 MAX100-insertB VELOCITY (ft /min) θJA (°C/W) PIN FIN HEATSINK FORCED CONVECTION PARAMETERS

45 Degrees*

*DIRECTION OF AIRFLOW ACROSS HEATSINK

0 Degrees*

0.060±.005(7x) 0.075±.020(6x) EQUAL SPACES D c PIN #1 e SE2 E b A2 A1 A 0.060±.005 5–6°

84 LEAD CERAMIC FLAT

A b C D e E S DIM MIN MAX MIN MAX 17.272 1.041 3.048 0.406 0.228 29.184 44.196 25.298 28.448 29.184 44.196 25.298 28.194 1.930 18.288 1.270 3.302 0.508 0.279 29.794 44.704 25.502 28.829 29.794 44.704 25.502 28.702 2.184 0.680 0.041 0.120 0.016 0.009 1.149 1.740 0.996 1.120 1.149 1.740 0.996 1.110 0.076 0.720 0.050 0.130 0.020 0.011 1.173 1.760 1.004 1.135 1.173 1.760 1.004 1.130 0.086 1.270 BSC 0.050 BSC