MAT04

MAT04_15 AD | Alldatasheet

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REV.D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a MAT04 Matched Monolithic Quad Transistor PIN CONNECTIONS 14-Lead Cerdip (Y Suffix) 14-Lead Plastic DIP (P Suffix) 14-Lead SO (S Suffix)

FEATURES

Low Offset Voltage: 200 /H9262V max High Current Gain: 400 min Excellent Current Gain Match: 2% max Low Noise Voltage at 100 Hz, 1 mA: 2.5 nV/ √Hz max Excellent Log Conformance: rBE = 0.6 /H9024 max Matching Guaranteed for All Transistors Available in Die Form PRODUCT DESCRIPTION The MAT04 is a quad monolithic NPN transistor that offers ex- cellent parametric matching for precision amplifier and nonlin- ear circuit applications. Performance characteristics of the MAT04 include high gain (400 minimum) over a wide range of collector current, low noise (2.5 nV/ √Hz maximum at 100 Hz, I C = 1 mA) and excellent logarithmic conformance. The MAT04 also features a low offset voltage of 200 µV and tight current gain matching, to within 2%. Each transistor of the MAT04 is individually tested to data sheet specifications. For matching parameters (offset voltage, input offset current, and gain match), each of the dual transistor combinations are verified to meet stated limits. Device performance is guaranteed at 25°C and over the industrial and military temperature ranges. The long-term stability of matching parameters is guaranteed by the protection diodes across the base-emitter junction of each transistor. These diodes prevent degradation of beta and match- ing characteristics due to reverse bias base-emitter current. The superior logarithmic conformance and accurate matching characteristics of the MAT04 makes it an excellent choice for use in log and antilog circuits. The MAT04 is an ideal choice in applications where low noise and high gain are required. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

ELECTRICAL CHARACTERISTICS (@ TA = 25/H11543C unless otherwise noted. Each transistor is individually tested. For matching parameters (VOS, IOS, ∆hFE) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted.) MAT04E MAT04F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Current Gain h FE 10 µA ≤ IC ≤ 1 mA

0 V ≤ VCB ≤ 30 V1 400 800 300 600

Current Gain Match ∆hFE IC = 100 µA 0 V ≤ VCB ≤ 30 V2 0.5 2 1 4 % Offset Voltage V OS 10 µA ≤ IC ≤ 1 mA

0 V ≤ VCB ≤ 30 V3 50 200 100 400 µV

Offset Voltage Change vs. ∆VOS/∆IC 10 µA ≤ IC ≤ 1 mA Collector Current V CB = 0 V3 52 5 1 0 5 0 µV Offset Voltage Change vs. V CB ∆VOS/∆VCB 10 µA ≤ IC ≤ 1 mA

0 V ≤ VCB ≤ 30 V3 50 100 100 200 µV

Bulk Emitter Resistance r BE 10 µA ≤ IC ≤ 1 mA VCB = 0 V4 0.4 0.6 0.4 0.6 Ω Input Bias Current I B IC = 100 µA

0 V ≤ VCB ≤ 30 V 125 250 165 330 nA

Input Offset Current I OS IC = 100 µA; VCB = 0 V 0.6 5 2 13 nA Breakdown Voltage BV CEO IC = 10 µA4 0 4 0 V Collector Saturation Voltage V CE(SAT) IB = 100 µA; IC = 1 mA 0.03 0.06 0.03 0.06 V Collector-Base Leakage Current I CBO VCB = 40 V 5 5 pA Noise Voltage Density e n VCB = 0 V; fO = 10 Hz 2 3 2 4 nV/ √Hz IC = 1 mA; fO = 100 Hz 1.8 2.5 1.8 3 nV/ √Hz fO = 1 kHz5 1.8 2.5 1.8 3 nV/ √Hz Gain Bandwidth Product f T IC = 1 mA; VCE = 10 V 300 300 MHz Output Capacitance C OBO VCB = 15 V; IE = 0 f = 1 MHz 10 10 pF Input Capacitance C EBO VBE = 0 V; IC = 0 f = 1 MHz 40 40 pF NOTES 1Current gain measured at I C = 10 µA, 100 µA and 1 mA. 2Current gain match is defined as: ∆ ∆h Ih I FE BF E MIN C = 100( )( ) 3Measured at I C = 10 µA and guaranteed by design over the specified range of I C. 4Guaranteed by design. 5Sample tested. Specifications subject to change without notice. –2– REV. D MAT04–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS(at –25 /H11543C ≤ TA /H11550 85/H11543C for MAT04E, –40 /H11543C ≤ TA /H11550 85/H11543C for MAT04F, unless otherwise noted. Each transistor is individually tested. For matching parameters (V OS, IOS) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted.) MAT04E MAT04F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Current Gain h FE 10 µA ≤ IC ≤ 1 mA

0 V ≤ VCB ≤ 30 V1 225 625 200 500

Offset Voltage V OS 10 µA ≤ IC ≤ 1 mA

0 V ≤ VCB ≤ 30 V2 60 260 120 520 µV

Average Offset TCV OS IC = 100 µA Voltage Drift V CB = 0 V3 0.2 1 0.4 2 µV/°C Input Bias Current I B IC = 100 µA

0 V ≤ VCB ≤ 30 V 160 445 200 500 nA

Input Offset Current I OS IC = 100 µA VCB = 0 V 4 20 8 40 nA Average Offset TCI OS IC = 100 µA Current Drift V CB = 0 V 50 100 pA/ °C Breakdown Voltage BV CEO IC = 10 µA4 0 4 0 V Collector-Base I CBO VCB = 40 V Leakage Current 0.5 0.5 nA Collector-Emitter I CES VCE = 40 V Leakage Current 5 5 nA Collector-Substrate I CS VCS = 40 V Leakage Current 0.7 0.7 nA MAT04 –3–REV. D

REV. D MAT04 –4– ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature Range Storage Temperature Package Type /H9258JA 2 /H9258JC Units 14-Lead Cerdip 108 16 °C/W 14-Lead Plastic DIP 83 39 °C/W 14-Lead SO 120 36 °C/W NOTES 1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2/H9258JA is specified for worst case mounting conditions, i.e., /H9258JA is specified for device in socket for cerdip and P-DIP packages; /H9258JA is specified for device soldered to printed circuit board for SO package. ORDERING GUIDE TA = 25/H11543C Temperature Package Package Model V OS max Range Description Option MAT04EY* 200 µV –25 °C to +85°C Cerdip Q-14 MAT04FY* 400 µV –40 °C to +85°C Cerdip Q-14 MAT04FP 400 µV –40 °C to +85°C P-DIP-14 N-14 MAT04FS 400 µV –40 °C to +85°C 14-Lead SO SO-14 NOTES *Not for new designs; obsolete April 2002. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the MAT04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. DICE CHARACTERISTICS Die Size 0.060 × 0.060 Inch, 3600 Sq. mm 1. Q1 COLLECTOR 2. Q1 BASE 3. Q1 EMITTER 4. SUBSTRATE 5. Q2 EMITTER 6. Q2 BASE 7. Q2 COLLECTOR 8. Q3 COLLECTOR 9. Q3 BASE 10. Q3 EMITTER 11. SUBSTRATE 12. Q4 EMITTER 13. Q4 BASE 14. Q4 COLLECTOR

–5–REV. D TPC 1. Current Gain vs. Collector Current TPC 4. Base-Emitter-On-Voltage vs. Collector Current TPC 7. Saturation Voltage vs. Collector Current TPC 2. Current Gain vs. Temperature TPC 5. Small Signal Input Resistance (hie) vs. Collector Current TPC 8. Noise Voltage Density vs. Frequency TPC 3. Gain Bandwidth vs. Collector Current TPC 6. Small Signal Output Conductance vs. Collector Current TPC 9. Noise Voltage Density vs. Collector Current Typical Performance Characteristics–

Figure 4. Temperature Independent Current Sink, IOUT = 10 V/RΩ A3. To maintain accuracy, 1% metal-film resistors should be used.

Figure 5. Vector Summer lights the low 1/f noise corner at 2 Hz. ized cross quad” which performs the voltage-to-current conversion.

Figure 6. Low Noise, High-Speed Instrumentation Amplifier Figure 7. Spot Noise of the Instrumentation Amplifier Figure 8. Low Frequency Noise Spectrum Showing Low

2 Hz Noise Corner, Gain = 1000

3 V RMS input and easily handles the full 20 Hz –20 kHz audio

more than 110 dB below maximum output. currents which form the stage currents of each differential pair. mum gain of the circuit is 2 (6 dB). may be prudent to use a nonpolarized tanta lum capacitor. Figure 9. Voltage-Controlled Attenuator

REV. D MAT04 –12–

Revision History

Data Sheet changed from REV. C to REV. D. C00285-0-2/02(D) PRINTED IN U.S.A.