MAT03AH

MAT03 AD | Alldatasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Tel: 617/329-4700 Fax: 617/326-8703 MAT03 Low Noise, Matched Dual PNP Transistor

FEATURES

Dual Matched PNP Transistor Low Offset Voltage: 100 mV max Low Noise: 1 nV/ √Hz @ 1 kHz max High Gain: 100 min High Gain Bandwidth: 190 MHz typ Tight Gain Matching: 3% max Excellent Logarithmic Conformance: r BE . 0.3 V typ Available in Die Form PIN CONNECTION TO-78 (H Suffix) GENERAL DESCRIPTION The MAT03 dual monolithic PNP transistor offers excellent parametric matching and high frequency performance. Low noise characteristics (1 nV/ √Hz max @ 1 kHz), high bandwidth (190 MHz typical), and low offset voltage (100 µV max), makes the MAT03 an excellent choice for demanding preamplifier ap- plications. Tight current gain matching (3% max mismatch) and high current gain (100 min), over a wide range of collector cur- rent, makes the MAT03 an excellent choice for current mirrors. A low value of bulk resistance (typically 0.3 Ω ) also makes the MAT03 an ideal component for applications requiring accurate logarithmic conformance. Each transistor is individually tested to data sheet specifications. Device performance is guaranteed at 25°C and over the extended industrial and military temperature ranges. To insure the long- term stability of the matching parameters, internal protection diodes across the base-emitter junction clamp any reverse base- emitter junction potential. This prevents a base-emitter break- down condition which can result in degradation of gain and matching performance due to excessive breakdown current.

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Ty p Max Units Current Gain1 hFE VCB = 0 V, –36 V IC = 1 mA 100 165 100 165 80 165 IC = 100 µA 90 150 90 150 70 150 IC = 10 µA 80 120 80 120 60 120 Current Gain Matching 2 DhFE IC = 100 µA,VCB = 0 V 0.5 3 0.5 3 0.5 6 % Offset Voltage 3 VOS VCB = 0 V, IC = 100 µA 40 100 40 100 40 200 µV Offset Voltage Change DV OS/DVCB IC = 100 µA vs. Collector Voltage V CB1 = 0 V 11 150 11 150 11 200 µV VCB2 = –36 V 11 150 11 150 11 200 µV Offset Voltage Change DV OS/DIC VCB = 0 V 12 50 12 50 12 75 µV vs. Collector Current I C1 = 10 µA, IC2 = 1 mA 12 50 12 50 12 75 µV Offset Current I OS IC = 100 µA, VCB = 0 V 6 35 6 35 6 45 nA Collector-Base Leakage Current I CB0 VCB = –36 V = VMAX 50 200 50 200 50 400 pA Noise Voltage Density 4 eN IC = 1 mA, VCB = 0 fO = 10 Hz 0.8 2 0.8 0.8 nV/ ÷ Hz fO = 100 Hz 0.7 1 0.7 0.7 nV/ ÷ Hz fO = 1 kHz 0.7 1 0.7 0.7 nV/ ÷ Hz fO = 10 kHz 0.7 1 0.7 0.7 nV/ ÷ Hz Collector Saturation –2– REV. B NOTES 1Current gain is measured at collector-base voltages (V CB) swept from 0 to V MAX at indicated collector current. Typicals are measured at V CB = 0 V. 2Current gain matching ( ΔhFE) is defined as: Δ hFE = 100 (ΔIB ) hFE (min ) IC 3Offset voltage is defined as: V OS = VBE1 – VBE2, where VOS is the differential voltage for I C1 = IC2: VOS = VBE1 – VBE2 = KT q In IC1 IC2 . 4Sample tested. Noise tested and specified as equivalent input voltage for each transistor. 5Guaranteed by V OS test (TCVOS = VOS/T for VOS ! VBE) where T = 298°K for TA = 25°C. Specifications subject to change without notice. MAT03–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ TA = +258C, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units Current Gain h FE VCB = 0 V, –36 V IC = 1 mA 70 110 IC = 100 µA 60 100 IC = 10 µA5 0 8 5 Offset Voltage V OS IC = 100 µA, VCB = 0 V 40 150 µV Offset Voltage Drift 5 TCVOS IC = 100 µA, VCB = 0 V 0.3 0.5 µV/°C Offset Current I OS IC = 100 µA, VCB = 0 V 15 85 nA Breakdown Voltage BV CEO 36 54 V (at –558C ≤ TA ≤ +1258C, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Min Typ Max Units Current Gain h FE VCB = 0 V, –36 V IC = 1 mA 70 120 60 120 IC = 100 µA 60 105 50 105 IC = 10 µA 5 09 0 4 09 0 Offset Voltage V OS IC = 100 µA, VCB = 0 V 30 135 30 265 µV Offset Voltage Drift5 TCVOS IC = 100 µA, VCB = 0 V 0.3 0.5 0.3 1.0 µV/°C Offset Current I OS IC = 100 µA, VCB = 0 V 10 85 10 200 nA Breakdown Voltage BV CEO 36 36 V (at –408C ≤ TA ≤ +858C, unless otherwise noted.)

–3–REV. B MAT03N Parameter Symbol Conditions Limits Units Breakdown Voltage BV CEO 36 V min Offset Voltage V OS IC = 100 µA, VCB = 0 V 200 µV max 10 µA ≤ IC ≤ 1 mA 200 µV max Current Gain h FE IC = 1 mA, VCB = 0 V, –36 V 80 min IC = 10 µA, VCB = 0 V, –36 V 60 min Current Gain Match ΔhFE IC = 100 µA, VCB = 0 V 6 % max Offset Voltage Change vs. V CB ΔVOS/ΔVCB VCB1 = 0 V, IC = 100 µA 200 µV max VCB2 = –36 V 200 µV max Offset Voltage Change ΔVOS/ΔIC VCB = 0 75 µV max vs. Collector Current I C1 = 10 µA, IC2 = 1 mA 75 µV max Bulk Resistance r BE 10 µA ≤ IC ≤ 1 mA 0.75 Ω max Collector Saturation Voltage V CE (SAT) IC = 1 mA, IB = 100 µA 0.1 V max NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. WAFER TEST LIMITS(at 258C, unless otherwise noted.) DICE CHARACTERISTICS SUBSTRATE CAN BE CONNECTED TO V– OR FLOATED 1. COLLECTOR (1 ) 2. BASE (1 ) 3. EMITTER (1 ) 4. COLLECTOR (2) 5. BASE (2) 6. EMITTER (2 ) ABSOLUTE MAXIMUM RATINGS 1 Total Power Dissipation Operating Temperature Range NOTES 1Absolute maximum ratings apply to both DICE and packaged devices. 2Rating applies to TO-78 not using a heat sink, and LCC; devices in free air only. For TO-78, derate linearly at 6.3 mW/ °C above 70°C ambient temperature; for LCC, derate at 7.8 mW/ °C. ORDERING GUIDE1 VOS max Temperature Package Model (T A = +258C) Range Option MAT03AH2 100 µV –55 °C to +125°C TO-78 MAT03EH 100 µV –40 °C to +85°C TO-78 MAT03FH 200 µV –40 °C to +85°C TO-78 NOTES 1Burn-in is available on industrial temperature range parts. 2For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the MAT03 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–7–REV. B to bias each side of the differential pair. The 5 k Ω collector re- sistors noise contribution is insignificant compared to the volt- age noise of the MAT03. Since noise in the signal path is referred back to the input, this voltage noise is attenuated by the gain of the circuit. Consequently, the noise contribution of the collector load resistors is only 0.048 nV/ √ Hz. This is consider- ably less than the typical 0.8 nV/ √Hz input noise voltage of the MAT03 transistor. The noise contribution of the OP27 gain stages is also negligible due to the gain in the signal path. The op amp stages amplify the input referred noise of the transistors to increase the signal strength to allow the noise spectral density (e in × 10000) to be measured with a spectrum analyzer. And, since we assume equal noise contributions from each transistor in the MAT03, the output is divided by √ 2 to determine a single transistor’s input noise. Air currents cause small temperature changes that can appear as low frequency noise. To eliminate this noise source, the measurement circuit must be thermally isolated. Effects of extrane- ous noise sources must also be eliminated by totally shielding the circuit. SUPER LOW NOISE AMPLIFIER The circuit in Figure 14a is a super low noise amplifier with equivalent input voltage noise of 0.32 nV/ √ Hz. By paralleling three MAT03 matched pairs, a further reduction of amplifier noise is attained by a reduction of the base spreading resistance by a factor of 3, and consequently the noise by √3. Additionally, the shot noise contribution is reduced by maintaining a high col- lector current (2 mA/device) which reduces the dynamic emitter resistance and decreases voltage noise. The voltage noise is in- versely proportional to the square root of the stage current, and current noise increases proportionally to the square root of the stage current. Accordingly, this amplifier capitalizes on voltage noise reduction techniques at the expense of increasing the cur- rent noise. However, high current noise is not usually important when dealing with low impedance sources. Figure 14a. Super Low Noise Amplifier

Figure 19. Digitally Programmable Current

–11–REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TO-78 Metal Can 0.250 (6.35) MIN 0.750 (19.05) 0.165 (4.19) REFERENCE PLANE 0.050 (1.27) MAX 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) 0.045 (1.14) 0.010 (0.25) 0.040 (1.02) MAX BASE & SEATING PLANE 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 0.034 (0.86) 0.027 (0.69) 0.045 (1.14) 0.027 (0.69) 0.160 (4.06) 0.110 (2.79) 0.100 (2.54) BSC 0.200 (5.08) BSC 0.100 (2.54) BSC 45° BSC

–12– 000000000PRINTED IN U.S.A.