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REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Low Noise, Matched Dual Monolithic Transistor MAT02 Tel: 617/329-4700 Fax: 617/326-8703

FEATURES

Low Offset Voltage: 50 mV max Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/ √Hz max High Gain (h FE): 500 min at I C = 1 mA 300 min at I C = 1 mA Excellent Log Conformance: r BE . 0.3 V Low Offset Voltage Drift: 0.1 mV/8C max Improved Direct Replacement for LM194/394 Available in Die Form ORDERING GUIDE1 VOS max Temperature Package Model (T A = +258C) Range Option MAT02AH2 50 µV –55 °C to +125°C TO-78 MAT02EH 50 µV –55 °C to +125°C TO-78 MAT02FH 150 µV –55 °C to +125°C TO-78 NOTES 1Burn-in is available on commercial and industrial temperature range parts in TO-can packages. 2For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. ABSOLUTE MAXIMUM RATINGS 1 Total Power Dissipation Operating Temperature Range NOTES 1Absolute maximum ratings apply to both DICE and packaged devices. 2Rating applies to applications using heat sinking to control case temperature. Derate linearly at 16.4 mW/ °C for case temperature above 40 °C. 3Rating applies to applications not using a heat sinking; devices in free air only. Derate linearly at 6.3 mW/ °C for ambient temperature above 70 °C. NOTE Substrate is connected to case on TO-78 package. Sub- strate is normally connected to the most negative circuit potential, but can be floated. PIN CONNECTION TO-78 (H Suffix) PRODUCT DESCRIPTION The design of the MAT02 series of NPN dual monolithic tran- sistors is optimized for very low noise, low drift, and low r BE. Precision Monolithics’ exclusive Silicon Nitride “Tri ple- Passivation” process stabilizes the critical device parameters over wide ranges of temperature and elapsed time. Also, the high current gain (hFE) of the MAT02 is maintained over a wide range of collector current. Exceptional characteristics of the MAT02 include offset voltage of 50 µV max (A/E grades) and 150 µV max F grade. Device performance is specified over the full military temperature range as well as at 25 °C. Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection diodes. This results in complete isola- tion between the transistors. The MAT02 should be used in any application where low noise is a priority. The MAT02 can be used as an input stage to make an amplifier with noise voltage of less than 1.0 nV/√ Hz at 100 Hz. Other applications, such as log/antilog circuits, may use the ex- cellent logging conformity of the MAT02. Typical bulk resis- tance is only 0.3 Ω to 0.4 Ω . The MAT02 electrical charac- teristics approach those of an ideal transistor when operated over a collector current range of 1 µA to 10 mA. For applications re- quiring multiple devices see MAT04 Quad Matched Transistor data sheet.

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ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Min Typ Max Units Current Gain h FE IC = 1 mA1 500 605 400 605 IC = 100 µA 500 590 400 590 IC = 10 µA 400 550 300 550 IC = 1 µA 300 485 200 485 Current Gain Match ΔhFE 10 µA ≤ IC ≤ 1 mA2 0.5 2 0.5 4 % Offset Voltage V OS VCB = 0, 1 µA ≤ IC ≤ 1 mA3 10 50 80 150 µV Offset Voltage ΔVOS/ΔVCB 0 ≤ VCB ≤ VMAX,4 10 25 10 50 µV Change vs. VCB 1 µA ≤ IC ≤ 1 mA3 10 25 10 50 µV Offset Voltage Change ΔVOS/ΔIC VCB = 0 V 5 25 5 50 µV vs. Collector Current 1 µA ≤ IC ≤ 1 mA3 52 5 5 5 0 µV Offset Current Change vs. VCB ΔIOS/ΔVCB 0 ≤ VCB ≤ VMAX 30 70 30 70 pA/V Bulk Resistance r BE 10 µA ≤ IC ≤ 10 mA5 0.3 0.5 0.3 0.5 Ω Collector-Base Leakage Current I CBO VCB = VMAX 25 200 25 400 pA Collector-Collector Leakage Current I CC VCC = VMAX 5, 6 35 200 35 400 pA Collector-Emitter V CE = VMAX 5, 6 Leakage Current I CES VBE = 0 35 200 35 400 pA Noise Voltage Density e n IC = 1 mA, VCB = 07 fO = 10 Hz 1.6 2 1.6 3 nV/ √Hz fO = 100 Hz 0.9 1 0.9 2 nV/ √Hz fO = 1 kHz 0.85 1 0.85 2 nV/ √Hz fO = 10 kHz 0.85 1 0.85 2 nV/ √Hz Collector Saturation Voltage V CE(SAT) IC = 1 mA, IB = 100 µA 0.05 0.1 0.05 0.2 V Input Bias Current I B IC = 10 µA2 5 3 4 n A Input Offset Current I OS IC = 10 µA 0.6 1.3 nA Breakdown Voltage BV CEO 40 40 V Gain-Bandwidth Product f T IC = 10 mA, VCE = 10 V 200 200 MHz Output Capacitance C OB VCB = 15 V, IE = 0 23 23 pF Collector-Collector Capacitance C CC VCC = 0 35 35 pF NOTES 1Current gain is guaranteed with Collector-Base Voltage (V CB) swept from 0 to V MAX at the indicated collector currents. 2Current gain match ( ΔhFE) is defined as: ΔhFE = 3Measured at I C = 10 µA and guaranteed by design over the specified range of I C. 4This is the maximum change in V OS as VCB is swept from 0 V to 40 V. 5Guaranteed by design. 6ICC and ICES are verified by measurement of I CBO. 7Sample tested. Specifications subject to change without notice. 100 (ΔIB) (hFE min) IC MAT02–SPECIFICATIONS (@ VCB = 15 V, IC = 10 mA, TA = 258C, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Units Offset Voltage V OS VCB = 0 80 µV 1 µA ≤ IC ≤ 1 mA1 Average Offset Voltage Drift TCV OS 10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ VMAX 2 0.08 0.3 µV/°C VOS Trimmed to Zero3 0.03 0.1 µV/°C Input Offset Current I OS IC = 10 µA9 n A Input Offset Current Drift TCI OS IC = 10 µA4 40 90 pA/ °C Input Bias Current I B IC = 10 µA6 0 n A Current Gain h FE IC = 1 mA5 275 IC = 100 µA 225 IC = 10 µA 125 IC = 1 µA 150 Collector-Base I CBO VCB = VMAX Leakage Current T A = 125°C1 5 n A Collector-Emitter I CES VCE = VMAX, VBE = 0 Leakage Current T A = 125°C5 0 n A Collector-Collector I CC VCC = VMAX Leakage Current T A = 125°C3 0 n A Parameter Symbol Conditions Min Typ Max Min Typ Max Units Offset Voltage V OS VCB = 0 70 220 µV 1 µA ≤ IC ≤ 1 mA1 Average Offset Voltage Drift TCV OS 10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ VMAX 2 0.08 0.3 0.08 1 µV/°C VOS Trimmed to Zero3 0.03 0.1 0.03 0.3 Input Offset Current I OS IC = 10 µA8 1 3 n A Input Offset Current Drift TCI OS IC = 10 µA4 40 90 40 150 pA/ °C Input Bias Current I B IC = 10 µA4 5 5 0 n A Current Gain h FE IC = 1 mA5 325 300 IC = 100 µA 275 250 IC = 10 µA 225 200 IC = 1 µA 200 150 Collector-Base I CBO VCB = VMAX 23 n A Leakage Current Collector-Emitter I CES VCE = VMAX, VBE = 0 3 4 nA Leakage Current Collector-Collector I CC VCC = VMAX 34 n A Leakage Current (VCB = 15 V, –25 8C ≤ TA ≤ +858C, unless otherwise noted.) ELECTRICAL CHARACTERISTICS(VCB = 15 V, –55 8C ≤ TA ≤ +1258C, unless otherwise noted.) MAT02 –3–REV. C NOTES 1Measured at I C = 10 µA and guaranteed by design over the specified range of I C. 2Guaranteed by V OS test (TCVOS ≅ VOS T for VOS ! VBE) T = 298°K for TA = 25°C. 3The initial zero offset voltage is established by adjusting the ratio of IC1 to IC2 at T A = 25°C. This ratio must be held to 0.003% over the entire temperature range. Measurements are taken at the temperature extremes and 25 °C. 4Guaranteed by design. 5Current gain is guaranteed with Collector-Base Voltage (V CB) swept from 0 to V MAX at the indicated collector current. Specifications subject to change without notice.

–4– REV. C MAT02N Parameter Symbol Conditions Limits Units Average Offset TCV OS 10 µA ≤ IC ≤ 1 mA 0.08 µV/°C Voltage Drift 0 ≤ VCB ≤ VMAX Average Offset TCI OS IC = 10 µA 40 pA/ °C Current Drift Gain-Bandwidth f T VCE = 10 V, IC = 10 mA 200 MHz Product Offset Current Change vs. V CB ΔIOS/ΔVCB 0 ≤ VCB ≤ 40 V 70 pA/V MAT02N Parameter Symbol Conditions Limits Units Breakdown Voltage BV CEO 40 V min Offset Voltage V OS 10 µA ≤ IC ≤ 1 mA1 150 µV max Input Offset Current I OS 1.2 nA max Input Bias Current I B VCB = 0 V 34 nA max Current Gain h FE IC = 1 mA, VCB = 0 V 400 min IC = 10 µA, VCB = 0 V 300 Current Gain Match ΔhFE 10 µA ≤ IC ≤ 1 mA, VCB = 0 V 4 % max Offset Voltage ΔVOS/ΔVCB 0 V ≤ VCB ≤ 40 V 50 µV max Change vs. VCB 10 µA ≤ IC ≤ 1 mA1 Offset Voltage Change ΔVOS/ΔIC VCB = 0 50 µV max vs. Collector Current 10 µA ≤ IC ≤ 1 mA1 Bulk Resistance r BE 100 µA ≤ IC ≤ 10 mA 0.5 Ω max Collector Saturation Voltage V CE (SAT) IC = 1 mA 0.2 V max IB = 100 µA NOTES 1Measured at l C = 10 µA and guaranteed by design over the specified range of I C. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the MAT02 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WAFER TEST LIMITS(@ 258C for VCB = 15 V and IC = 10 mA, unless otherwise noted.) (VCB = 15 V, IC = 10 mA, TA = +258C, unless otherwise noted.)TYPICAL ELECTRICAL CHARACTERISTICS Die Size 0.061 × 0.057 inch, 3,477 sq. mils (1.549 × 1.448 mm, 224 sq. mm) 1. COLLECTOR (1) 2. BASE (1) 3. EMITTER (1) 4. COLLECTOR (2) 5. BASE (2) 6. EMITTER (2) 7. SUBSTRATE DICE CHARACTERISTICS

Figure 18. Log Conformance Test Circuit tion from true log conformity as the collector currents vary. the op amps to a collector current ramp through each transistor.

to 1.0, so “m” ranges from RB/(RA + RB) to (RB + RA)/RB. ter than ± 0.1% over a limited operating range. side (full-scale) allows a fast response with wide dynamic range. nally –1 V/decade using the component values indicated. to low noise, the amplifier has very low drift and high CMRR. and total supply current is approximately 2.8 mA. Figure 22. Multifunction Converter