MAT01 (Rev. D)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 12
Technical content
FEATURES
Low VOS (VBE match): 40 µV typical, 100 µV maximum Low TCVOS: 0.5 µV/°C maximum High hFE: 500 minimum Excellent hFE linearity from 10 nA to 10 mA Low noise voltage: 0.23 µV p-p from 0.1 Hz to 10 Hz High breakdown: 45 V min
APPLICATIONS
Low noise, op amp, front end Current mirror and current sink/source Low noise instrumentation amplifiers Voltage controlled attenuators Log amplifiers PIN CONNECTION DIAGRAM Figure 1. GENERAL DESCRIPTION The MAT01 is a monolithic dual NPN transistor. An exclusive silicon nitride triple passivation process provides excellent stability of critical parameters over both temperature and time. Matching characteristics include offset voltage of 40 µV, temperature drift of 0.15 µV/°C, and hFE matching of 0.7%. High hFE is provided over a six decade range of collector current, including an exceptional hFE of 590 at a collector current of only 10 nA. The high gain at low collector current makes the MAT01 ideal for use in low power, low level input stages. MAT01 TOP VIEW (Not to Scale) NOTES 1. SUBSTRATE IS CONNECTED TO CASE. 00282-001 2 5 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©1973–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
REVISION HISTORY
9/14—Rev. C to Rev. D 4/13—Rev. B to Rev. C Added Applications Section, Deleted Figure 2, 2/02—Rev. A to Rev. B Rev. D | Page 2 of 12
ELECTRICAL CHARACTERISTICS
VCB = 15 V , IC = 10 µA, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments MAT01AH MAT01GH Unit Min Typ Max Min Typ Min V O LTAGE Breakdown Voltage BVCEO IC = 100 µA 45 45 V Offset Voltage VOS 0.04 0.1 0.10 0.5 mV Offset Voltage Stability First Month1 VOS/Time 2.0 2.0 µV/Mo Long Term2 0.2 0.2 µV/Mo CURRENT Offset Current IOS 0.1 0.6 0.2 3.2 nA Bias Current IB 13 20 18 40 nA Current Gain hFE IC = 10 nA 590 430 IC = 10 µA 500 770 250 560 IC = 10 mA 840 610 Current Gain Match ∆hFE IC = 10 µA 0.7 3.0 1.0 8.0 % 100 nA ≤ IC ≤ 10 mA 0.8 1.2 % NOISE Broadband Noise Voltage en rms 1 Hz to 10 kHz 0.60 0.60 µV rms Noise Voltage Density en fO = 10 Hz3 7.0 9.0 7.0 9.0 nV/√Hz fO = 100 Hz3 6.1 7.6 6.1 7.6 nV/√Hz fO = 1000 Hz3 6.0 7.5 6.0 7.5 nV/√Hz OFFSET VOLTAGE/CURRENT Offset Voltage Change ∆VOS/∆VCB 0 ≤ VCB ≤ 30 V 0.5 3.0 0.8 8.0 µV/V Offset Current Change ∆IOS/∆VCB 0 ≤ VCB ≤ 30 V 2 15 3 70 pA/V LEAKAGE Collector to Base Leakage Current ICBO VCB = 30 V, IE = 04 15 50 25 200 pA Collector to Emitter Leakage Current ICES VCE = 30 V, VBE = 04, 5 50 200 90 400 pA Collector to Collector Leakage Current ICC VCC = 30 V5 20 200 30 400 pA SATURATION IB = 1 mA, IC = 10 mA 0.8 0.8 V GAIN BANDWIDTH PRODUCT fT VCE = 10 V, IC = 10 mA 450 450 MHz CAPACITANCE Output Capacitance COB VCB = 15 V, IE = 0 2.8 2.8 pF Collector to Collector Capacitance CCC VCC = 0 8.5 8.5 pF 1 Exclude first hour of operation to allow for stabilization. 2 Parameter describes long-term average drift after first month of operation. 3 Sample tested. 4 The collector to base (ICBO) and collector to emitter (ICES) leakage currents can be reduced by a factor of 2 to 10 times by connecting the substrate (package) to a potential that is lower than either collector voltage. 5 ICC and ICES are guaranteed by measurement of ICBO. Rev. D | Page 3 of 12
VCB = 15 V , IC = 10 µA, −55°C ≤ TA ≤ +125°C, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments MAT01AH MAT01GH Unit Min Typ Max Min Typ Min OFFSET VOLTAGE/CURRENT Offset Voltage VOS 0.06 0.15 0.14 0.70 mV Average Offset Voltage Drift1 TCVOS 0.15 0.50 0.35 1.8 µV/°C Offset Current IOS 0.9 8.0 1.5 15.0 nA Average Offset Current Drift2 TCIOS 10 90 15 150 pA/°C BIAS CURRENT ΙΒ 28 60 36 130 nA CURRENT GAIN hFE 167 400 77 300 LEAKAGE CURRENT Collector to Base Leakage Current ICBO TA = 125°C, VCB = 30 V, IE = 03 15 80 25 200 nA Collector to Emitter Leakage Current ICES TA = 125°C, VCE = 30 V, VBE = 01, 3 50 300 90 400 nA Collector to Collector Leakage Current ICC TA = 125°C, VCC = 30 V1 30 200 50 400 nA
1 Guaranteed by VOS test ( ) for BEVOSVT
OSTCV <<≅ , T = 298 K for TA = 25°C. 2 Guaranteed by IOS test limits over temperature. 3 The collector to base (ICBO) and collector to emitter (ICES) leakage currents can be reduced by a factor of 2 to 10 times by connecting the substrate (package) to a potential that is lower than either collector voltage. Rev. D | Page 4 of 12
Rev. D | Page 5 of 12 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter1 Rating Breakdown Voltage of Collector to Base Voltage (BVCBO) 45 V Collector to Emitter Voltage (BVCEO) 45 V Collector to Collector Voltage (BVCC) 45 V Emitter to Emitter Voltage (BVEE) 45 V Emitter to Base Voltage (BVEBO)2 5 V Current Collector (IC) 25 mA Emitter (IE) 25 mA Total Power Dissipation Case Temperature ≤ 40°C3 1.8 W Ambient Temperature ≤ 70°C4 500 mW Temperature Range Operating −55°C to +125°C Junction −55°C to +150°C Storage −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C 1 Absolute maximum ratings apply to packaged devices.
2 Application of reverse bias voltages in excess of rating shown can result in
degradation of hFE and hFE matching characteristics. Do not attempt to measure BVEBO greater than the 5 V rating.
3 Rating applies to applications using heat sinking to control case
temperature. Derate linearity at 16.4 mW/°C for case temperatures above 40°C. 4 Rating applies to applications not using heat sinking; device in free air only. Derate linearity at 6.3 mW/°C for ambient temperatures above 70°C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION
Application of reverse bias voltages to the emitter to base junctions in excess of ratings (5 V) may result in degradation of hFE and hFE matching characteristics. Check circuit designs to ensure that reverse bias voltages above 5 V cannot be applied during transient conditions, such as at circuit turn-on and turn-off. Stray thermoelectric voltages generated by dissimilar metals at the contacts to the input terminals can prevent realization of the predicted drift performance. Maintain both input terminals at the same temperature, preferably close to the temperature of the device package. Rev. D | Page 9 of 12
Figure 13. Precision Reference Figure 14. Basic Digital Thermometer Readout in Degrees Kelvin (K) Figure 15. Digital Thermometer with Readout in °C
- R1 MAY BE ADJUSTED TO MINIMIZE TCVREF.
INCREASING R1 CAUSES A POSITIVE CHANGE IN TCVREF.
- hFE OF Q1 IS REDUCED BY OPERATION OF BREAKDOWN MODE.
100 FEET
Figure 16. 6-Pin Metal Header Package [TO-78] REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Rev. D | Page 12 of 12 NOTES ©1973–2014 Analog Devices, Inc. All ri ghts reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00282-0-9/14(D)