MAT-04 AD | Alldatasheet
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e Matching Guaranteed for All Transistors sue [3] sus (P-Suffix) e Available in Die Form = Ghs pag OR 8, (Bf 218, 14-PIN SO ¢, @}—] fac, (S-Suffix) ORDERING INFORMATION ' PACKAGE T= 425°C | OPERATING Vog MAX CERDIP PLASTIC TEMPERATURE iM) 14-PIN 14-PIN RANGE ABSOLUTE MAXIMUM RATINGS (Note 1)
200 Matocey = ND Collector-Emitter Voltage (BVoeg) snsnnnennnnnnsseneen 40V
400 MATOABY" _ MIL Collector-Collector Voltage (BVig) ssvsnvsssrenessnsttnenanes 40V
400 MATOSFY MATOAFP XIND Emitter-Emitter Voltage (BVec) sicissusnsussineetieseeees 40V
- Fordevices processed in total compliance to MIL-STD-983, add 889 after part Emitter Current ..ovssneecescesesceseeentstectnessenenteee SOMA t Burn-in is available on commercial and industrial temperature range parts in Operating Temperature Range ‘ BOF, panto Di and Toros packages. and PLOG packages, contact MAT-O4AY, BY ...cccscssssssseseesssesseseeesenssnsns 55°C TO +125°C sour local sales ace. packages, MAT-O4EY o..scsesscsssssssssstecssssecessnsseessssees 25°C TO 485°C MAT-O4FY,FP,FS ....scessssscsseessesessecsseeenessnienns 40°C to +85°C Storage Temperature Y PACKAGE oo. ...ecseecssecsstecssessseesnssessesssessesss “BD°C to +150°C GENERAL DESCRIPTION P PACKAGE -oeesvesseesersersteneesersneessenenenen “05°C 10 +125°C The MAT-04 is a quad monolithic NPN transistor that offers Lead Temperature (Soldering, 60 $60) .-vrerennns #300°C excellent parametric matching for precision amplifier and non- PACKAGE TYPE q (Note 2) %& UNITS: linear circuit applications. Performance characteristics of the TI CERI BG MAT-04 include high gain (400 minimum) over a wide range of en er collector current, low noise (2.5nV// Hz maximum at 100Hz, Tae este ee = 1 mA) and excellent logarithmic conformance. The MAT-04 jaPinso(s) tO also features alow offset voltage of 200V and tight current gain NOTES: matching, to within 2%, Each transistor of the MAT-04 is > Absolule maxirum ratings apply 10 both DICE and packaged parts, unless individually tested to data sheet specifications. For matching 2. ©, isspecifiedfor worstcase mounting conditions, 1.2.,@,,isspecified for devics parameters (offset voltage, input offset current, and gain match), in Socket for CerDIP and P-DIP packages; ©,, is specified for device solderec each of the dual transistor combinations are verified to meet to printed circuit board for SO package. stated limits. Device performance is guaranteed at 25°C and over the industrial and military temperature ranges. The long-term stability of matching parameters is guaranteed by the protection diodes across the base-emitter junction of each transistor. These diodes prevent degradation of beta and matching characteristics due to reverse bias base-emitter current. The superior logarithmic conformance and accurate matching characteristics of the MAT-04 makes it an excellent choice for use in log and antilog circuits. The MAT-04 is an ideal choice in applications where low noise and high gain are required. -1-
ELECTRICAL CHARACTERISTICS at T, = 25°C unless otherwise noted. Each transistor is individually tested. For matching parameters (Vog, log, Ahrg) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless other- wise noted. - MAT-O4A/E MAT-04B/F PARAMETER ‘SYMBOL CONDITIONS MIN TYP MAX MIN- TYP MAX UNITS 10uA<Ig<tmA Current Gain bee OV =Vog = 30V 400 800 — 300 600 — (Note 1) is I= 100nA Current Gain Abpe OV Vops30V — 05 2 - 41 4 % (Note2) TOpA<Ig< Ima Offset Voltage Ves OV =Vog=30V — 50 20 — 100 400 Wv (Note 4) Offset Voltage 10,A=Io= 1mA ‘Change vs ANos/Ale Vea = 0V —- 5 2 - 0 6 wv Collector Current (Note4) — 104A Ios tmA Offset Voltage Nos/4Veu OV = Vog = 30V — 60 100 — 100 200 WV ‘Change vs Vos (Note4) TOMAS loss 1mA Bulk Emitter Resistance tee Veg = OV — 04 06 — 04 06 a (Notes) . l= 00,8 InputBias Current I Ov stag 90 — 125 250 165 330 nA InputOffset Current los lo= 100uA — 06 5 —- 2 4 nA Vea = 0V Breakdown Voltage BYce0 Ig = 102A 4 = = 40 = = v Collector Saturation l= 100pA Voeisan tma 0.03 0.08 0.08 0.08 v Collector-Base - - - - - Leakage Current 'ca0 Vos =40v 5 i pA Vea=0V fo= 10Hz —- 2 3 - 2 4 Noise Voge en Ig=1mA_ fo = 100HzZ — 18 25 — 18 3 nviVRz ensity (Notes) fo = 1kHz — 18 25 — 18 3 Gain Bandwidth Ig=tma _ _ Product fr Vog = 10V — 300 ~ 300 Mrz ; Vea=15V Ig=0 _ _ _ _ Output Capacitance Coa eine 10 10 pF Vpe=0V Ig =0 _ _ a - Input Capacitance Cepo (nine 40 40 pF NOTES: 1, Current gain measured at ic = 104, 100A and 1mA. 100 (Alp) (fe rnin)
2 Currentgain matchis defined as: Ahge = SS —
- Sample tested. 4. Measured at |; = 10A and guaranteed by design over the specified range ot le. 5. Guaranteed by design. -2-
ELECTRICAL CHARACTERISTICS at -25°C <T, < +85°C for MAT-04E, 40°C < T, < +85°C for MAT-04F, unless otherwise noted. Each transistor is individually tested. For matching parameters (V<, |g) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted. TT MAT-04E MAT-04F PARAMETER SYMBOL CONDITIONS . MIN” TYP MAX MIN TYP MAX UNITS 10,A= Ios IMA Current Gain hee OV =Vo_=30V 225 6250 200 500 — (Note 1) 10pA< Ic = 1mA Offset Voltage Vos OVS Vo_=30V — 60 260 — 120 520 wv (Note3) Ic = 100pA Average Offset c TCVos, Vop = 0V — 02 1 — 04 2 vmod Votage rit (Note 2) I= 100pA _ = Input Bias Current ly OV =Vop = 20V 160445 200 500 nA Input Offset Current los lo= 100nA - 4 20 - 8 40 nA Vog = OV ‘Average Offset Ig = 1008 _ _ _ _ Current Drift TClos Veg = OV 50 00 pare Breakdown Voltage BVceo lo = 108 4a - = oR v Collector-Base Leakage Current ‘cao Vou = 40V 7 8 7 8 na Collector-Emitter _ _ Leakage Current ‘ces Voe=40v 7 8 - 8 ma Collector-Substrate - Leskage Current les Ves = 40V —- 07 = o7 = nA ELECTRICAL CHARACTERISTICS at —55°C = T, = 125°C unless otherwise noted. Each transistor is individually tested. For matching parameters (Vog, Iog) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted. MAT-04A MAT-04B PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS 40pA< Ios 1mA CurrentGain hee OV =Vog = 30V 175 475 125 4250 — (Note 1) 1OHA< Ios 1mA Offset Voltage Vos OV =Vog = 30V — 70 300 — 140 600 my (Note3) lo= 100nA vote Dat TCVog Vea =0V — 02 1 — o4 2 HVC (Note 2) lp= 100n4 _ _ Input Bias Current ly OV 2 Veg 2200 210 570 235 800 nA Input Offset Current os I= 100nA — 6 30 — 12 60 nA Veg = OV Average Offset bo = 100nA _ — - _ " Current Drift TClos Vop = 0V 50 100 parc Breakdown Voltage BYce0 Io = 100A 0 — = 0 — = v Collector-Base Leakage Current ‘coo Vow = 40V ~ 5 oF -— 8 OF na Collector-Emitter _ _ _ _ _ Leakage Current tees Voe = 40V 100 100 na Collector-Substrate Leakage Current ‘cs Vos = 40V 7 TOF 7 OT na NOTES: 1. Current gain measured at lc = 10uA, 100A and 1mA. 3. Measured at Io = 104A and guaranteed by design over the specified range 2. Guaranteed by Vos test (TCVog = Vos/T for Vos << Vge) T = 298K for Of lo. Ty = 25°C.
g > 1. Q, COLLECTOR _ 2, Q, BASE 3. Q, EMITTER ———) 4, SUBSTRATE SS SSS 5. Q, EMITTER — 6. Q, BASE —— fh 7. Q, COLLECTOR — 8. Q, COLLECTOR === 9. Q, BASE = 10. Q, EMITTER 11. SUBSTRATE 1"; | 12. Q, EMITTER uO | at 13. Q, BASE 14, Q, COLLECTOR DIE SIZE 0.060 x 0.060 inch, 3600 sq. mils (1.52 x 1.52 mm, 2.31 sq. mm) WAFER TEST LIMITS at T, = +25°C unless otherwise noted. Each transistor is individually tested. For matching parameters (Vag, log: Age) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted. A MAT-O4N PARAMETER ‘SYMBOL CONDITIONS LIMITS UNITS I, = 100pA i le Current Gain Pee OV <Vog $30 300 MIN Current Gain Match Ape Ig = 100HA, Veg = OV 4 %o MAX 10pA <1, 1mA Offset Voltage Vos OVS Vog $30V 400 HV MAX (Note 1) Offset Voltage JONAS |, $1mA Change vs AVog/Al Veg = OV 50 nV MAX Collector Current (Note 1) 410A <1, 5 1mA Offset Voltage he AV og /AV, OVS Vo, 5 30V. 200 uV MAX cs! Noe ca Change us VCB (Note 1) 10HA <I, 1mA Bulk Emitter Resistance oe Vog = OV 06 MAX (Note 2) Collector Saturation 1, = 100nA Voltage Voesan I= 1mA 9.06 VMAX Ig= 100pA i lc Input Bias Current I, OVS Vp 5 30V 330 nA MAX 1, = 100pA Input Offset Current los. Veg = 0V 1 nA MAX Breakdown Voltage BVoe0, Iya 10H 40 VMIN NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specications based on dice lot qualifications through sample jot assembly and testing. -4-
Carn | FORMANCE CHARACTERISTICS _ GAIN BANDWIDTH vs on Cun C TEMPER, TURE COLLECTOR CURRENT fe a Se vs coLLEeTOn CURRENT sooo vs TEMPER: : ‘000 = Tt tt a ee —— ne ee wb ay i — 7
0 F264 eee
Sol INN UE TIN TN sae =“ =—2=a5 a A So St enn so cH A Ta tm : +4 5 ———=— ” : a a Sa UL ea re a ee ‘COLLECTOR CURRENT (A) SIGNAL OUTPUT SMALL SIGNAL INPUT SA NDUSTANGE ve OEE oe cure COLLECTOR CURRENT oe COLLECTOR CURRENT COLLECTOR CURRENT wo vs COLLECTOR a ee all i ESS e Se ToS os SS Ait | aa === li A A ee Busconeamerey a _ VOLTAGE DEN: VOLTAGE vs NOISE \\ReOUENGY. siry ee COLLECTOR CURRENT SATURATION 's FREQU COLLECTOR EN es voto ae 3 rT . erie erie eee cere === SS Fee 2 Rt g PS i ESSpS ta I SS Ss Los | === aa 7“ Pe gu _ i ee eS SSS Tr ee. ; ft fF couscroncunnent meauenc
FIGURE 4: Temperature Independent Current Sink, lout = 10V/RO wav four = 494 four four our z 9 ° 9 V 1009 }-—+—-+---4—----5
8 AN |, |
NONLINEAR FUNCTIONS This circuit uses two MAT-04AYs and maintains an accuracy of An application where precision matched-transistors are a power- better than 0.5% over an input range of 10mV to 10V. The layout ful tool is in the generation of nonlinear functions. These circuits of the MAT-04s reduces errors due to matching and temperature are based on the transistor’s logarithmic property which takes the differences between the two precision quad matched-transistors. following idealized form: Op amps A1 and A2 translate the input voltages into logarithmic kT, Io valued currents (I, and Ip in Figure 5) that flow through transistor Vee = a Inge Qg and Qs. These currents are summed by transistor Q4 a s_ . (lo = la + Ip = Vy? +12) which feeds the current-to-voltage The MAT-04, with its excellent logarithmic conformance, main- converter consisting of op amp A3. To maintain accuracy, 1% tains this idealized function over many decades of collector cur- metal-film resistors should be used. rent. This, in addition to the stringent parametric matching of the MAT-04, enables the implementation of extremely accurate log/ antilog circuits. The circuit of Figure 5 is a vector summer that adds and subtracts logged inputs to generate the following transfer function: Vout = + VVa? + Ve? om
FIGURE 5: Vector Summer Re vour= Se rrr ro OVour | | | ware -o/ fT) | md | | batt, TV A AL ee ne —-f2__ | I lo 7 L 8 in | | | | | | St a 1000pF i}, 1 in MAT-o4 o ia om) Ud PP ow Rt 2 53, a i pea i 6 3 d 1s el Is ee | ¥ ov. ov Vv Vv LOW NOISE, HIGH SPEED INSTRUMENTATION AMPLIFIER TABLE |: Instrumentation Amplifier Characteristics The circuit of Figure 6 is a very low noise, high speed amplifier, §—§ ————.q999 a ideal for use in precision transducer and professional audio appli- InputNolse G= 100 3.6nV/ VHz cations. The performance of the amplifier is summarized in Voltage Density G=10 ‘30nV/ (Hz Table |. Figure 7 shows the input referred spot noise over the 00 OK 0-25kHz bandwidth to be flat at 1.2nV/ VHz. Figure 8 highlights Bandwidth G= 100 {MHz the low 1/f noise corner at 2Hz. G=10 4.2MHz The circuit uses a high speed op amp, the OP-17, preceded by an ‘Slew Rate 40V/us input amplifier. This consists of a precision dual matched-transis- Common-Mode tor, the MAT-02, and a feedback V-to-I converter, the MAT-04. Rejection G= 1000 13008 The arrangement of the MAT-04 is known as a “linearized cross egg quad" which performs the voltage-to-current conversion. The Distortion f= 20Hz to 20kHz 0.03% OP-17 acts as an overall nulling amplifier to complete the feed-_—_—§ <2 back loop. Resistors R1, R2, and R3, R4 form voltage dividers Settling Time G= 1000 104s that attenuate the output voltage swing since the “cross quad” ar- Power Consumption 350mW rangement has a limited input range. Biasing for the input stage is set by zener diode Z1. At low currents the effective zener voltage is about 3.3V due to the soft knee characteristic of the zener diode. This results in a bias current of 530,.A per side for the input stage. The gain of this amplifier with the values shown in Figure 6 is: Vout_ _ 33000 Vin Re
FIGURE 9: Voltage-Controlled Attenuator ove
3 Re ca re
3 .) — 7 ee ee oe a | qi 1 | ) 2, aye ° 8 Yow oN ls gus” sg rs if vec ca = TOF <a ba ne San See Lc > s Zax S10KO $OKA>= OOF my a az ane | v J Re Bs 30K Sok — Ov. VOLTAGE-CONTROLLED ATTENUATOR The ideal transfer function for the voltage-controlled attenuator is: The voltage-controlled attenuator (VCA) of Figure 9, widely used 2 in professional audio circles, can easily be implemented using a Vour/Vin = Ria ‘iT MAT-04. The excellent matching characteristics of the MAT-04 1+ exp (‘Hoorn (aa yl ( “) enables the VCA to have a distortion level of under 0.03% over a 13 + R14 q wide range of control voltages. The VCA accepts a 3V RMS input = 23 and easily handles the full 20H2-20kHz audio bandwidth as Where K = tompoature nk 1.88 x 10° 4I"K shown in Figure 10. Noise level for the VCA is more than 110dB q = electronic charge = 1.602 x 10-C below maximum output. From th fer b hat th rom the transfer function it can be seen that the maximum gain In the voltage-controlled attenuator, the input signal modulates of the circuit is 2 (6dB). 9 the stage current of each differential pair. Op amps A2 and A3 in " conjunction with transistors Q5 and Q6 form voltage-to-current To insure best performance, resistors R2 through R7 should be converters that transform a single input voltage into differential 1% metal film resistors. Since capacitor C2 can see small currents which form the stage currents of each differential pair. amounts of reverse bias when the control voltage is positive, it The control voltage shifts the current between each side of the may be prudent to use a nonpolarized tantalum capacitor. two differential pairs, regulating the signal level reaching the out- put stage which consists of op amp A. Figure 11 shows the in- crease in signal attenuation as the control voltage becomes more negative. -10-
FIGURE 10: Voltage-Controlled Attenuator, FIGURE 11: Voltage-Controlled Attenuator, Attenuation vs Frequency Attenuation vs Control Voltage JT TM 7 TTT et | aT 7 4 a wa EAD oe ary 100 tk 10k 100k “85 2 a ° 1 FREQUENCY (Hz) CONTROL VOLTAGE (VOLTS) -11-
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